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CN104465382B - Mos transistor source and drain forming method - Google Patents

Mos transistor source and drain forming method Download PDF

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Publication number
CN104465382B
CN104465382B CN201310435686.2A CN201310435686A CN104465382B CN 104465382 B CN104465382 B CN 104465382B CN 201310435686 A CN201310435686 A CN 201310435686A CN 104465382 B CN104465382 B CN 104465382B
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drain
source
lightly doped
mos transistor
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CN104465382A (en
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

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Abstract

本发明提供了一种MOS晶体管源漏形成方法,包括:在形成有栅极结构的硅片中,在栅极结构两侧分别形成源极轻掺杂区和漏极轻掺杂区;在栅极结构两侧形成栅极侧壁;在形成栅极侧壁的栅极结构两侧的硅片中分别形成源极区域和漏极区域;在栅极结构所在的层,在硅片上形成阻挡层;此后,去除栅极结构两侧的侧壁,从而在栅极结构和阻挡层之间留下凹槽结构;利用栅极结构和阻挡层作为掩膜,对硅片进行离子注入,从而在硅片表面形成新源极轻掺杂区和新漏极轻掺杂区;在栅极结构和阻挡层之间留下凹槽结构中填充介质。

The invention provides a method for forming the source and drain of a MOS transistor, comprising: forming a lightly doped source region and a lightly doped drain region on both sides of the gate structure in a silicon wafer formed with a gate structure; The gate sidewalls are formed on both sides of the gate structure; the source region and the drain region are respectively formed in the silicon wafers on both sides of the gate structure forming the gate sidewall; on the layer where the gate structure is located, barriers are formed on the silicon wafer layer; thereafter, the sidewalls on both sides of the gate structure are removed, thereby leaving a groove structure between the gate structure and the barrier layer; using the gate structure and the barrier layer as a mask, ion implantation is performed on the silicon wafer, thereby A new source lightly doped region and a new drain lightly doped region are formed on the surface of the silicon wafer; a groove structure is left between the gate structure and the barrier layer to fill the medium.

Description

MOS晶体管源漏形成方法Method for forming source and drain of MOS transistor

技术领域technical field

本发明涉及半导体制造领域,更具体地说,本发明涉及一种MOS晶体管源漏形成方法。The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for forming a source and drain of a MOS transistor.

背景技术Background technique

金属-氧化物-半导体(Metal-Oxide-Semiconductor)结构的晶体管简称MOS晶体管。现如今,MOS晶体管已经被广泛地用于大部分的数字电路及部分模拟电路中。Metal-oxide-semiconductor (Metal-Oxide-Semiconductor) transistors are referred to as MOS transistors for short. Nowadays, MOS transistors have been widely used in most digital circuits and some analog circuits.

MOS晶体管包括布置在衬底中的源极和漏极,以及布置在衬底上的位于源极和漏极之间的栅极。The MOS transistor includes a source and a drain arranged in a substrate, and a gate arranged on the substrate between the source and the drain.

图1至图3示意性地示出了根据现有技术的MOS晶体管源漏形成方法的各个步骤。1 to 3 schematically show various steps of a method for forming a source and drain of a MOS transistor according to the prior art.

具体地说,如图1至图3所示,根据现有技术的MOS晶体管源漏形成方法包括:首先,在形成有栅极结构40(例如,栅极结构40包括栅极氧化层和多晶硅层)的硅片10中,在栅极结构40两侧分别形成源极轻掺杂区20和漏极轻掺杂区30(如图1所示);随后,在栅极结构40两侧形成栅极侧壁50(如图2所示);随后,在形成栅极侧壁50的栅极结构40两侧的硅片中分别形成源极区域60和漏极区域70(如图3所示)。其中,例如,源极区域60和漏极区域70的截面为U形、sigma形或三角形。Specifically, as shown in FIGS. 1 to 3 , the method for forming the source and drain of a MOS transistor according to the prior art includes: first, after forming a gate structure 40 (for example, the gate structure 40 includes a gate oxide layer and a polysilicon layer ) in the silicon wafer 10, a lightly doped source region 20 and a lightly doped drain region 30 are respectively formed on both sides of the gate structure 40 (as shown in FIG. 1 ); subsequently, a gate is formed on both sides of the gate structure 40 pole sidewall 50 (as shown in FIG. 2 ); subsequently, a source region 60 and a drain region 70 are respectively formed in the silicon wafer on both sides of the gate structure 40 forming the gate sidewall 50 (as shown in FIG. 3 ). . Wherein, for example, the cross sections of the source region 60 and the drain region 70 are U-shaped, sigma-shaped or triangular.

但是,在根据现有技术的MOS晶体管源漏形成方法中,如图3所示,形成源极区域60和漏极区域70之后剩下的残留源极轻掺杂区21和残留漏极轻掺杂区31变得相当小。而在很多应用中,仅仅留下很小部分的残留源极轻掺杂区21 和残留漏极轻掺杂区31是不期望的。However, in the method for forming the source and drain of MOS transistors according to the prior art, as shown in FIG. 3 , the remaining lightly doped source region 21 and lightly doped drain remaining The impurity region 31 becomes considerably smaller. However, in many applications, it is not desirable to leave only a small portion of the residual source lightly doped region 21 and the residual drain lightly doped region 31 .

因此,希望能够提供一种能够在源极区域和漏极区域上方分别形成较大的源极轻掺杂区和漏极轻掺杂区的方案。Therefore, it is desirable to provide a solution capable of forming larger source lightly doped regions and drain lightly doped regions above the source region and the drain region respectively.

发明内容Contents of the invention

本发明所要解决的技术问题是针对现有技术中存在上述缺陷,提供一种能够在源极区域和漏极区域上方分别形成加大区域的源极轻掺杂区和漏极轻掺杂区的MOS晶体管源漏形成方法。The technical problem to be solved by the present invention is to provide a lightly doped source region and a lightly doped drain region that can respectively form enlarged regions above the source region and the drain region in view of the above-mentioned defects in the prior art. MOS transistor source and drain formation method.

为了实现上述技术目的,根据本发明,提供了一种MOS晶体管源漏形成方法,其包括:在形成有栅极结构的硅片中,在栅极结构两侧分别形成源极轻掺杂区和漏极轻掺杂区;在栅极结构两侧形成栅极侧壁;在形成栅极侧壁的栅极结构两侧的硅片中分别形成源极区域和漏极区域;在栅极结构所在的层,在硅片上形成阻挡层;此后,去除栅极结构两侧的侧壁,从而在栅极结构和阻挡层之间留下凹槽结构;利用栅极结构和阻挡层作为掩膜,对硅片进行离子注入,从而在硅片表面形成新源极轻掺杂区和新漏极轻掺杂区;在栅极结构和阻挡层之间留下凹槽结构中填充介质。In order to achieve the above technical purpose, according to the present invention, a method for forming the source and drain of a MOS transistor is provided, which includes: forming lightly doped source regions and Drain lightly doped region; gate sidewalls are formed on both sides of the gate structure; source regions and drain regions are respectively formed in the silicon wafers on both sides of the gate structure forming the gate sidewalls; where the gate structure is located A barrier layer is formed on the silicon wafer; thereafter, the sidewalls on both sides of the gate structure are removed, thereby leaving a groove structure between the gate structure and the barrier layer; using the gate structure and the barrier layer as a mask, Ion implantation is performed on the silicon wafer to form a new source lightly doped region and a new drain lightly doped region on the surface of the silicon wafer; a groove structure is left between the gate structure and the barrier layer to fill the medium.

优选地,源极区域和漏极区域的截面为U形、sigma形或三角形。Preferably, the cross sections of the source region and the drain region are U-shaped, sigma-shaped or triangular.

优选地,源极区域和漏极区域的材料为SiGe或者SiC。Preferably, the material of the source region and the drain region is SiGe or SiC.

优选地,刻蚀阻挡层的材料为SiO2,SiON或SiN中的一种。Preferably, the material of the etching barrier layer is one of SiO2, SiON or SiN.

优选地,栅极侧壁的材料为氮化硅。Preferably, the material of the gate sidewall is silicon nitride.

优选地,对于NMOS,离子注入中注入的离子为As离子、P离子、N离子、C离子和Ge离子等中的一种或几种。Preferably, for NMOS, the ions implanted in the ion implantation are one or more of As ions, P ions, N ions, C ions and Ge ions.

优选地,对于PMOS,离子注入中注入的离子为BF2离子、In离子和B离子、N离子、C离子和Ge离子等中的一种或几种。Preferably, for PMOS, the ions implanted in the ion implantation are one or more of BF2 ions, In ions, B ions, N ions, C ions, and Ge ions.

优选地,栅极结构包括栅极氧化层和多晶硅层。Preferably, the gate structure includes a gate oxide layer and a polysilicon layer.

优选地,介质的材料与栅极侧壁的材料相同。Preferably, the material of the dielectric is the same as that of the sidewall of the gate.

优选地,介质的材料为氮化硅。Preferably, the material of the dielectric is silicon nitride.

在根据本发明的MOS晶体管源漏形成方法中,在源极区域和漏极区域上方分别形成较大的新源极轻掺杂区和新漏极轻掺杂区,克服了原本的源极轻掺杂区及漏极轻掺杂区较小带来的缺陷。In the method for forming the source and drain of a MOS transistor according to the present invention, a larger new source lightly doped region and a new drain lightly doped region are respectively formed above the source region and the drain region, which overcomes the original source lightly doped region. The defects caused by the small doped region and the lightly doped region of the drain.

附图说明Description of drawings

结合附图,并通过参考下面的详细描述,将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征,其中:A more complete understanding of the invention, and its accompanying advantages and features, will be more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which:

图1至图3示意性地示出了根据现有技术的MOS晶体管源漏形成方法的各个步骤。1 to 3 schematically show various steps of a method for forming a source and drain of a MOS transistor according to the prior art.

图4至图7示意性地示出了根据本发明优选实施例的MOS晶体管源漏形成方法的各个步骤。4 to 7 schematically show various steps of the method for forming the source and drain of the MOS transistor according to the preferred embodiment of the present invention.

需要说明的是,附图用于说明本发明,而非限制本发明。注意,表示结构的附图可能并非按比例绘制。并且,附图中,相同或者类似的元件标有相同或者类似的标号。It should be noted that the accompanying drawings are used to illustrate the present invention, but not to limit the present invention. Note that drawings showing structures may not be drawn to scale. And, in the drawings, the same or similar elements are marked with the same or similar symbols.

具体实施方式detailed description

为了使本发明的内容更加清楚和易懂,下面结合具体实施例和附图对本发明的内容进行详细描述。In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

图4至图7示意性地示出了根据本发明优选实施例的MOS晶体管源漏形成方法的各个步骤。4 to 7 schematically show various steps of the method for forming the source and drain of the MOS transistor according to the preferred embodiment of the present invention.

具体地说,如图1至图7所示,根据本发明优选实施例的MOS晶体管源漏形成方法包括:Specifically, as shown in FIGS. 1 to 7, the method for forming the source and drain of a MOS transistor according to a preferred embodiment of the present invention includes:

首先,在形成有栅极结构40(例如,栅极结构40包括栅极氧化层和多晶硅层)的硅片10中,在栅极结构40两侧分别形成源极轻掺杂区20和漏极轻掺杂区30(如图1所示);First, in the silicon wafer 10 formed with the gate structure 40 (for example, the gate structure 40 includes a gate oxide layer and a polysilicon layer), the source lightly doped region 20 and the drain are respectively formed on both sides of the gate structure 40 Lightly doped region 30 (as shown in FIG. 1 );

随后,在栅极结构40两侧形成栅极侧壁50(如图2所示);优选地,栅极侧壁50的材料为氮化硅。Subsequently, gate sidewalls 50 are formed on both sides of the gate structure 40 (as shown in FIG. 2 ); preferably, the material of the gate sidewalls 50 is silicon nitride.

随后,在形成栅极侧壁50的栅极结构40两侧的硅片中分别形成源极区域60和漏极区域70(如图3所示);其中,例如,优选地,源极区域60和漏极区域70的截面为U形、sigma形或三角形。而且,优选地,源极区域60和漏极区域70的材料为SiGe或者SiC;本发明尤其对源极区域60和漏极区域70的材料为SiGe或者SiC的应用的改进效果明显。Subsequently, a source region 60 and a drain region 70 are respectively formed in the silicon wafer on both sides of the gate structure 40 forming the gate sidewall 50 (as shown in FIG. 3 ); wherein, for example, preferably, the source region 60 The cross-section of the drain region 70 is U-shaped, sigma-shaped or triangular. Moreover, preferably, the material of the source region 60 and the drain region 70 is SiGe or SiC; the present invention has an obvious improvement effect especially on the application where the material of the source region 60 and the drain region 70 is SiGe or SiC.

可以采用现有技术中已知的任何适当方法来形成源极区域60和漏极区域70。例如,可通过硅衬底刻蚀、外延生长等步骤来形成源极区域60和漏极区域70。Source region 60 and drain region 70 may be formed using any suitable method known in the art. For example, the source region 60 and the drain region 70 can be formed by silicon substrate etching, epitaxial growth and other steps.

此后,在栅极结构40所在的层,在硅片10上形成阻挡层80;优选地,刻蚀阻挡层80的材料为SiO2,SiON或SiN中的一种(如图4所示);Thereafter, a barrier layer 80 is formed on the silicon wafer 10 at the layer where the gate structure 40 is located; preferably, the material of the etch barrier layer 80 is one of SiO2, SiON or SiN (as shown in FIG. 4 );

此后,去除栅极结构40两侧的侧壁,从而在栅极结构40和阻挡层80之间留下凹槽结构(如图5所示);Thereafter, the sidewalls on both sides of the gate structure 40 are removed, thereby leaving a groove structure between the gate structure 40 and the barrier layer 80 (as shown in FIG. 5 );

此后,利用栅极结构40和阻挡层80作为掩膜,对硅片10进行离子注入(如图6中的箭头所示),从而在硅片10表面形成新源极轻掺杂区80和新漏极轻掺杂区90(如图6所示);实际上,新源极轻掺杂区80和新漏极轻掺杂区90取代原本的残留源极轻掺杂区21和残留漏极轻掺杂区31,使得源极轻掺杂区和漏极轻掺杂区可以更大。Thereafter, using the gate structure 40 and the barrier layer 80 as a mask, ion implantation is performed on the silicon wafer 10 (as shown by the arrow in FIG. 6 ), thereby forming a new source lightly doped region 80 and a new Drain lightly doped region 90 (as shown in FIG. 6 ); in fact, new source lightly doped region 80 and new drain lightly doped region 90 replace the original residual source lightly doped region 21 and residual drain The lightly doped region 31 makes the source lightly doped region and the drain lightly doped region larger.

例如,对于NMOS,离子注入中注入的离子为As离子、P离子、N离子、C离子和Ge离子等中的一种或几种;对于PMOS,离子注入中注入的离子为BF2离子、In离子和B离子、N离子、C离子和Ge离子等中的一种或几种。For example, for NMOS, the ions implanted in ion implantation are one or more of As ions, P ions, N ions, C ions, and Ge ions; for PMOS, the ions implanted in ion implantation are BF2 ions, In ions, etc. And one or more of B ions, N ions, C ions, and Ge ions.

此后,可以在栅极结构40和阻挡层80之间留下凹槽结构中填充介质100。优选地,介质100的材料与栅极侧壁50的材料相同;例如,介质100的材料为氮化硅。Thereafter, a recess structure may be left between the gate structure 40 and the barrier layer 80 to fill the dielectric 100 . Preferably, the material of the dielectric 100 is the same as that of the gate sidewall 50; for example, the material of the dielectric 100 is silicon nitride.

在根据本发明优选实施例的MOS晶体管源漏形成方法中,在源极区域和漏 极区域上方分别形成较大的新源极轻掺杂区和新漏极轻掺杂区,克服了原本的源极轻掺杂区及漏极轻掺杂区较小带来的缺陷。In the method for forming the source and drain of a MOS transistor according to a preferred embodiment of the present invention, a larger new source lightly doped region and a new new drain lightly doped region are respectively formed above the source region and the drain region, which overcomes the original Defects caused by small lightly doped source regions and lightly doped drain regions.

此外,需要说明的是,除非特别说明或者指出,否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等,而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。In addition, it should be noted that, unless otherwise specified or pointed out, the terms “first”, “second”, “third” and other descriptions in the specification are only used to distinguish each component, element, step, etc. in the specification, and It is not used to represent the logical relationship or sequential relationship between various components, elements, and steps.

可以理解的是,虽然本发明已以较佳实施例披露如上,然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言,在不脱离本发明技术方案范围情况下,都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. a kind of MOS transistor source and drain forming method, it is characterised in that including:
In the silicon chip of grid structure is formed with, source electrode lightly doped district is formed respectively in grid structure both sides and drain electrode is lightly doped Area;
Gate lateral wall is formed in grid structure both sides;
Source region and drain region are formed respectively in the silicon chip of grid structure both sides of gate lateral wall is formed, and are left residual source Pole lightly doped district and residual drain electrode lightly doped district;
In the layer where grid structure, barrier layer is formed on silicon chip;
Hereafter, the side wall of grid structure both sides is removed, so as to leave groove structure between grid structure and barrier layer;
By the use of grid structure and barrier layer as mask, ion implanting is carried out to silicon chip, so as to form new source electrode in silicon chip surface Lightly doped district and new drain electrode lightly doped district, new source electrode lightly doped district and the new drain electrode lightly doped district substitution residual source electrode are lightly doped Area and residual drain electrode and become much larger lightly doped district;
Filled media in groove structure is left between grid structure and barrier layer.
2. MOS transistor source and drain forming method according to claim 1, it is characterised in that source region and drain region Section be U-shaped, sigma shapes or triangle.
3. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that source region and drain region The material in domain is SiGe or SiC.
4. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material on barrier layer is One kind in SiO2, SiON or SiN.
5. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material of gate lateral wall is Silicon nitride.
6. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that for NMOS, ion note The ion for entering injection is the one or more in As ions, P ion, N ions, C ions and Ge ions.
7. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that for PMOS, ion note The ion for entering middle injection is BF2One or more in ion, In ions and B ions, N ions, C ions and Ge ions.
8. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that grid structure includes grid Oxide layer and polysilicon layer.
9. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material and grid of medium The material of side wall is identical.
10. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material of medium is nitrogen SiClx.
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US5534447A (en) * 1995-11-13 1996-07-09 United Microelectronics Corporation Process for fabricating MOS LDD transistor with pocket implant
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