CN104462009A - Multiprocessor system and full interconnection method thereof - Google Patents

Abstract

The present invention provides a multiprocessor system and a full interconnection method of the multiprocessor system. The multiprocessor system includes: more than two minimum logic units, and the two sides of each minimum logic unit are respectively connected with The coprocessor of the unit; the minimum logic unit includes at least one computing module, and each computing module includes two interconnected central processing units CPU; each computing module is respectively associated with the corresponding coprocessors on both sides of the minimum logic unit where it is located Each coprocessor located on the same side of each minimum logic unit is connected to realize the connection of CPUs in any two minimum logic units. According to the above scheme, the connection of the CPUs in any two minimum logic units is realized by each coprocessor located on the same side of the minimum logic unit, thereby reducing the jump between the CPUs in any two minimum logic units and improving the CPU performance. communication efficiency.

Description

A kind of multiprocessor system and the full interconnection method of multiprocessing system

technical field

The invention relates to the technical field of computers, in particular to a multiprocessor system and a full interconnection method of the multiprocessor system.

Background technique

With the rapid development of computer technology, in order to meet the needs of economic and social development, high-performance computer systems have become a key factor restricting social development. Key fields such as finance and telecommunications have extremely high performance requirements for computer systems, so it is necessary to build multi-processor systems to meet the performance requirements of various fields.

At present, each central processing unit (CPU) in a multiprocessor system is connected to each other. When any two CPUs in a multiprocessor system communicate with each other, it is necessary to perform Multiple hops can be realized, resulting in low efficiency of communication between CPUs.

Contents of the invention

The invention provides a multi-processor system and a full interconnection method of the multi-processor system to solve the problem of low efficiency in communication between CPUs in the prior art.

The embodiment of the present invention provides a multiprocessor system, comprising: more than two minimum logic units, each of the two sides of the minimum logic unit is respectively connected with a coprocessor corresponding to the minimum logic unit; the minimum logic unit Including at least one computing module, each computing module includes two interconnected central processing units CPU;

Wherein, each calculation module is connected to the corresponding coprocessors on both sides of the minimum logic unit where it is located, and each coprocessor located on the same side of each minimum logic unit is connected to realize the connection of CPUs in any two minimum logic units .

Preferably, it includes 8 minimum logic units;

On the same side of the 8 minimum logic units, 8 coprocessors corresponding to the 8 minimum logic units are connected in pairs.

Preferably, it includes 16 minimum logic units;

On the same side of the 16 smallest logical units, the 16 coprocessors corresponding to the 16 smallest logical units are respectively located in two groups, each group includes 8 coprocessors, and the 8 coprocessors located in the same group The coprocessors are connected in pairs, and the coprocessors in one group are connected to the coprocessors in the other group in one-to-one correspondence.

Preferably, the minimum logic unit includes two computing modules, wherein the CPU in one computing module is connected to the CPU in the other computing module in a one-to-one correspondence.

The embodiment of the present invention also provides a method for full interconnection of a multiprocessor system, which is applied to the above-mentioned multiprocessor system. The multiprocessor system includes: more than two minimum logic units, each of the minimum logic units Both sides are respectively connected with coprocessors corresponding to the minimum logic unit; the minimum logic unit includes at least one computing module, and each computing module includes two interconnected central processing units CPU; the full interconnection method includes:

Connect each computing module to the corresponding coprocessors on both sides of the smallest logic unit where the computing module is located;

The coprocessors located on the same side of each minimum logic unit are connected to realize the connection of CPUs in any two minimum logic units.

Preferably, the connecting the coprocessors located on the same side of each minimum logic unit includes:

When the multiprocessor system includes 8 minimum logic units, the 8 coprocessors located on the same side of the 8 minimum logic units and corresponding to the 8 minimum logic units are connected in pairs.

Preferably, the connecting the coprocessors located on the same side of each minimum logic unit includes:

When the multiprocessor system includes 16 minimum logic units, the 16 coprocessors corresponding to the 16 minimum logic units on the same side of the 16 minimum logic units are divided into two groups, wherein each A group includes 8 coprocessors;

The 8 coprocessors in the same group are connected two by two, and the coprocessors in one group are connected with the coprocessors in another group in one-to-one correspondence.

Preferably, further comprising:

When the minimum logic unit includes two calculation modules, the CPU in one calculation module is connected to the CPU in the other calculation module in one-to-one correspondence.

The embodiment of the present invention provides a multiprocessor system and a full interconnection method of the multiprocessor system. The multiprocessor system includes more than two minimum logic units, and the two sides of each minimum logic unit are respectively connected with corresponding The coprocessor of the minimum logic unit realizes the connection of CPUs in any two minimum logic units by connecting each coprocessor on the same side of the minimum logic unit, thereby reducing the jump between CPUs in any two minimum logic units Step, improve the communication efficiency of CPU.

Description of drawings

FIG. 1 is a schematic structural diagram of a multiprocessor system provided by an embodiment of the present invention;

Fig. 2 is a schematic diagram of the connection relationship of 8 protocol processors on one side provided by the embodiment of the present invention;

Fig. 3 is a schematic diagram of the connection relationship of 16 protocol processors on one side provided by the embodiment of the present invention;

FIG. 4 is a flowchart of a full interconnection method for a multiprocessor system provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In order to solve the shortcomings of the prior art, the present invention takes into account the characteristics that multiple processors can share memory, and considers the requirement of linear growth of multi-processor system as the system scale increases, expanding the performance of the system, as shown in Figure 1 , the embodiment of the present invention provides a multiprocessor system, the multiprocessor system may include:

More than two minimum logic units 10, each of the two sides of the minimum logic unit 10 is respectively connected with a coprocessor (CC, coprocessor) 11 corresponding to the minimum logic unit 10, wherein the multiprocessor system uses each minimum logic unit Unit 10 is a centrally symmetrical structure. The minimum logic unit 10 includes at least one path computing module 12, and each path computing module 12 includes two interconnected central processing units; each path computing module 12 is connected to the corresponding coprocessor 11 on both sides of the minimum logic unit 10 where it is located, and The coprocessors 11 located on the same side of each minimum logic unit 10 are connected to realize the connection of CPUs in any two minimum logic units 10 . Wherein, the connection relationship of each coprocessor 11 on both sides of each minimum logic unit 10 is the same.

In Fig. 1, only two minimum logic units 10 are shown, and each minimum logic unit 10 includes two-way calculation modules 12, and each way calculation module 12 includes two interconnected central processing units (CPU, Central Processing Unit).

Wherein, the connection relationship between the two calculation modules 12 included in each minimum logic unit 10 is: one calculation module 12 is connected to the CPU in the other calculation module 12 in a one-to-one correspondence. This ensures that all CPUs in each minimum logic unit 10 can be directly or indirectly connected. In addition, each minimum logic unit 10 also includes: independent computing resources, memory resources and I/O resources. All CPUs in the minimum logic unit 10 share these resources, so as to implement an operating system that each minimum logic unit 10 runs independently.

In this embodiment, in order to ensure that the CPUs between each minimum logic unit 10 can communicate, each coprocessor 11 on the same side of each minimum logic unit 10 is connected through an internal high-speed interconnection network, which is used to maintain the multiprocessor system. cache consistency,

In this embodiment, the multiprocessor system is in a tightly coupled form, that is, the connection relationship between the coprocessors on both sides of each minimum logic unit 10 needs to be changed every time it is expanded.

Wherein, since each minimum logic unit 10 includes 4 CPUs, when the multiprocessor system includes 8 minimum logic units, the multiprocessor system is extended to a 32-way system. As shown in FIG. 2 , it is a schematic diagram of the connection relationship of each coprocessor 11 on the same side of the eight minimum logic units 10 . The connection relationship is: on the same side of the 8 smallest logic units 10, the 8 coprocessors 11 corresponding to the 8 smallest logic units 10 are connected in pairs, that is, any coprocessor 11 is connected to the other 7 Coprocessors 11 are connected to ensure system performance. Since the coprocessors 11 on both sides of the smallest processor unit 10 do not need to access, the coprocessors 11 on both sides of the eight smallest logic units 10 are not connected.

Among them, when the multiprocessor system includes 16 minimum logic units, the multiprocessor system is extended to a 64-way system. As shown in FIG. 3 , it is a schematic diagram of the connection relationship of each coprocessor 11 on the same side of the 16 minimum logic units 10 . The connection relationship is: on the same side of the 16 smallest logic units, the 16 coprocessors corresponding to the 16 smallest logic units are respectively located in two groups, such as group one and group two, group one and group two The second division includes 8 coprocessors, the 8 coprocessors in the group one are connected in pairs, the schematic diagram of the pairwise connection is shown in Figure 2, and the 8 coprocessors in the group two are connected in pairs, the two A schematic diagram of the two connections is shown in Figure 2. And the coprocessors in one group are connected with the coprocessors in another group in one-to-one correspondence. For example, the numbers of the 8 coprocessors in group 1 are 100, 110, 120, ... 170, and the numbers of the 8 coprocessors in group 2 are 200, 210, 220 ... 270, then group 1 and group 2 The connection relationship among is as shown in Figure 3, coprocessor 100 is connected with coprocessor 200, coprocessor 110 is connected with coprocessor 210, coprocessor 120 is connected with coprocessor 220, ..., coprocessor 170 Connected to coprocessor 270 . Since the coprocessors 11 on both sides of the smallest processor unit 10 do not need to be accessed, the coprocessors 11 on both sides of the 16 smallest logic units 10 are not connected.

According to the above scheme, the multiprocessor system includes more than two minimum logic units, and the two sides of each minimum logic unit are respectively connected with coprocessors corresponding to the minimum logic unit. The coprocessor realizes the connection of the CPUs in any two smallest logic units, thereby reducing the jump between the CPUs in any two smallest logic units, and improving the communication efficiency of the CPUs.

As shown in FIG. 4 , the embodiment of the present invention also provides a method for full interconnection of a multiprocessor system, which is applied to the above multiprocessor system. The multiprocessor system includes: more than two minimum logic units, each Coprocessors corresponding to the minimum logic unit are respectively connected to both sides of a minimum logic unit; the minimum logic unit includes at least one computing module, and each computing module includes two interconnected central processing units CPU; Interconnection methods include:

Step 401: Connect each computing module to the corresponding coprocessors on both sides of the smallest logic unit where the computing module is located;

Step 402: Connect the coprocessors located on the same side of each minimum logic unit, so as to realize the connection of CPUs in any two minimum logic units.

Said connecting the coprocessors located on the same side of each minimum logic unit includes: when the multiprocessor system includes 8 minimum logic units, connecting the coprocessors located on the same side of the 8 minimum logic units, corresponding to the The 8 coprocessors of the 8 smallest logic units are connected in pairs.

The connecting the coprocessors located on the same side of each minimum logic unit includes: when the multiprocessor system includes 16 minimum logic units, connecting the coprocessors located on the same side of the 16 minimum logic units, corresponding to the The 16 coprocessors of the 16 smallest logical units are divided into two groups, wherein each group includes 8 coprocessors;

The 8 coprocessors in the same group are connected two by two, and the coprocessors in one group are connected with the coprocessors in another group in one-to-one correspondence.

Further includes:

When the minimum logic unit includes two calculation modules, the CPU in one calculation module is connected to the CPU in the other calculation module in one-to-one correspondence.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (8)

1. a multicomputer system, is characterized in that, comprising: plural minimum logical block, and the both sides of each minimum logical block are connected to the coprocessor corresponding to this minimum logical block; Described minimum logical block comprises at least one road computing module, and each road computing module comprises two interconnective central processor CPUs;

Wherein, the coprocessor that each road computing module is corresponding with minimum logical block both sides, self place is respectively connected, and each coprocessor being positioned at each minimum logical block the same side is connected, and realizes the connection of CPU in any two described minimum logical blocks.

2. multicomputer system according to claim 1, is characterized in that, comprises 8 minimum logical blocks;

Be positioned at the same side of described 8 minimum logical blocks, 8 coprocessors corresponding to described 8 minimum logical blocks connect between two.

3. multicomputer system according to claim 1, is characterized in that, comprises 16 minimum logical blocks;

Be positioned at the same side of described 16 minimum logical blocks, 16 coprocessors corresponding to these 16 minimum logical blocks lay respectively in two groupings, each grouping comprises 8 coprocessors, 8 coprocessors being positioned at same grouping connect between two, and one grouping in coprocessor and another divide into groups in coprocessor connect one to one.

4., according to described multicomputer system arbitrary in claims 1 to 3, it is characterized in that, described minimum logical block comprises two-way computing module, and wherein the CPU in a road computing module and the CPU in another road computing module connects one to one.

5. the totally interconnected method of a multicomputer system, it is characterized in that, be applied to arbitrary described multicomputer system in the claims 1 to 4, described multicomputer system comprises: plural minimum logical block, and the both sides of each minimum logical block are connected to the coprocessor corresponding to this minimum logical block; Described minimum logical block comprises at least one road computing module, and each road computing module comprises two interconnective central processor CPUs; Described totally interconnected method comprises:

The coprocessor that each road computing module is corresponding with these minimum logical block both sides, computing module place, road is respectively connected;

Each coprocessor being positioned at each minimum logical block the same side is connected, is connected with the CPU realized in any two described minimum logical blocks.

6. totally interconnected method according to claim 5, is characterized in that, is describedly connected by each coprocessor being positioned at each minimum logical block the same side, comprising:

When described multicomputer system comprises 8 minimum logical blocks, will be positioned at described 8 minimum logical block the same sides, 8 coprocessors corresponding to described 8 minimum logical blocks are connected between two.

7. totally interconnected method according to claim 5, is characterized in that, is describedly connected by each coprocessor being positioned at each minimum logical block the same side, comprising:

When described multicomputer system comprises 16 minimum logical blocks, will be positioned at described 16 minimum logical block the same sides, 16 coprocessors corresponding to described 16 minimum logical blocks are divided into two groupings, and wherein, each grouping comprises 8 coprocessors;

8 coprocessors being positioned at same grouping are connected between two, and the coprocessor in dividing into groups is connected with the coprocessor one_to_one corresponding during another divides into groups.

8. totally interconnected method according to claim 5, is characterized in that, comprise further:

When described minimum logical block comprises two-way computing module, the CPU in the CPU in a road computing module and another road computing module is connected one to one.