CN104460140B - Array base palte and display device - Google Patents

Abstract

The invention provides an array substrate and a display device, belonging to the field of display technology, which can solve the problem of poor display of the array substrate caused by a large jump voltage of a data line on the existing array substrate. The array substrate of the present invention includes pixel units arranged in a matrix, each of the pixel units is provided with a pixel electrode and a common electrode that are insulated from each other, and is provided between the layer where the pixel electrode is located and the layer where the common electrode is located. The conductive electrode in between is insulated from the pixel electrode, and the projections of the two on the substrate are at least partially overlapped, and the conductive electrode is electrically connected to the common electrode. The display device of the present invention includes the above-mentioned array substrate. The display effect of the display device using the array substrate of the present invention is obviously improved.

Description

Array substrate and display device

technical field

The invention belongs to the field of display technology, and in particular relates to an array substrate and a display device.

Background technique

A liquid crystal display panel is mainly composed of an array substrate and a color filter substrate pair box. Wherein, as shown in FIG. 1 , the array substrate is provided with gate lines 2 and data lines 3 which are arranged in a grid shape crosswise (because they are located in different layers, they will not conduct when they cross), the gate lines 2 and data lines Each intersection position of the line 3 defines a pixel unit 1, so that a plurality of pixel units are arranged in a matrix form; for a color liquid crystal display panel, each pixel unit 1 corresponds to a sub-pixel (also known as a sub-pixel) of the display screen, and by The three sub-pixels of red, green and blue constitute a visible pixel on the display screen; for an achromatic display, one pixel unit 1 can also directly correspond to one pixel on the display screen.

Each pixel unit 1 includes a thin film transistor 11 and a pixel electrode 12 connected to the drain of the thin film transistor 11, the gates of the thin film transistors 11 of a row of pixel units 1 are connected to the same gate line 2, and the thin film transistors of a column of pixel units 1 The source of 11 is connected to the same data line 3 . When a certain gate line 2 is turned on, as long as the signal of each data line 3 is controlled, a row of pixel units 1 corresponding to the gate line 2 can display the required content at the same time, so it is only necessary to make each gate line 2 turn on ( Also known as scanning), you can display what you want.

The inventor has found that at least the following problems exist in the prior art: when a certain row of pixel units is scanned, the potential on the gate line 2 that selects the row of pixel units changes from high potential to low potential (or from low potential to is a high potential), the data voltage signal applied to the corresponding pixel unit by the data line 3 will jump at this moment, and the jump voltage generated on the data line 3 is ΔVp. It is known to those skilled in the art that ΔVp= Cgs_on*(Vgh-Vgl)/(Cgs_on+Cst+Clc), where Cgs_on is the gate-source capacitance; Vgh is the high potential applied to the gate line; Vgl is the low potential applied to the gate line; Cst is the pixel capacitance; Clc is the liquid crystal capacitance. Therefore, reducing the jump voltage is extremely important for improving the display effect of the liquid crystal display.

Contents of the invention

The technical problems to be solved by the present invention include, aiming at the above-mentioned problems existing in the existing array substrate, providing an array substrate and a display device that can reduce the jump voltage of the data lines on the array substrate and improve the uniformity of the common electrode voltage .

The technical solution adopted to solve the technical problem of the present invention is an array substrate, which includes pixel units arranged in a matrix, each pixel unit is provided with a pixel electrode and a common electrode that are insulated from each other, and a a conductive electrode between the layer where the common electrode is located and the layer where the common electrode is located,

The conductive electrode is insulated from the pixel electrode, and the projections of the two on the substrate are at least partially overlapped, and the conductive electrode is electrically connected to the common electrode.

Preferably, the array substrate further includes a plurality of gate lines and a plurality of data lines intersecting and insulated, and each of the pixel units is connected to one data line and one gate line.

Further preferably, the gate lines in two adjacent rows are connected to the pixel units in the same row at the same time, and each data line is connected to the pixel units in two adjacent columns at the same time, and the two pixel units in the same row of pixel units connected to the same data line different grid lines connected to each of the pixel units.

Still further preferably, the conductive electrode is arranged between two adjacent columns of pixel units connected to two different data lines.

Further preferably, the common electrode and the gate line are arranged in the same layer and made of the same material.

Further preferably, each of the pixel units includes a thin film transistor, the source of the thin film transistor is connected to the data line, the drain is connected to the pixel electrode, and the gate is connected to the gate line.

More preferably, a gate insulating layer and a passivation layer are also arranged between the layer where the pixel electrode is located and the layer where the common electrode is located; the conductive electrode is arranged between the gate insulating layer and the passivation layer. between the gate insulating layers, and the conductive electrode is electrically connected to the common electrode through a first via hole penetrating through the gate insulating layer.

Still further preferably, the drain of the thin film transistor is electrically connected to the pixel electrode through a second via hole penetrating the passivation layer.

The technical solution adopted to solve the technical problem of the present invention is a display device, which includes the above-mentioned array substrate.

The present invention has following beneficial effect:

In the array substrate of the present invention, by forming a conductive electrode electrically connected to the common electrode between the pixel electrode and the common electrode, and at least partially overlapping the conductive electrode with the pixel electrode, the connection structure between the conductive electrode and the common electrode The pixel electrode forms a pixel capacitance Cst. It can be understood that the conductive electrode is closer to the pixel electrode than the common electrode, thus reducing the distance between the two plates constituting the pixel capacitance Cst, thereby increasing the value of the pixel capacitance Cst, according to the jump voltage The calculation formula of ΔVp: ΔVp=Cgs_on*(Vgh-Vgl)/(Cgs_on+Cst+Clc), where Cgs_on is the gate-source capacitance; Vgh is the high potential applied to the gate line; Vgl is the low potential applied to the gate line; Cst is the pixel capacitance; Clc is the liquid crystal capacitance, it can be seen that the value of the pixel capacitance Cst increases, and the jump voltage ΔVp decreases, thereby solving the problem of poor display caused by the large jump voltage ΔVp in the prior art.

At the same time, in the array substrate of the present invention, since the conductive electrodes are electrically connected to the common electrodes, the connection structure between the conductive electrodes and the common electrodes is equivalent to the common electrodes in the prior art, and the conductive electrodes are connected in parallel with the common electrodes, so it is more advanced. Compared with the resistance of the common electrode in the prior art, the resistance of the connection structure between the conductive electrode and the common electrode in the present invention is relatively small, so the uniformity of the voltage of the common electrode of the display panel can be improved.

The display device provided by the present invention includes the above-mentioned array substrate, so its display effect is obviously improved and its quality is better.

Description of drawings

FIG. 1 is a schematic structural view of an existing array substrate;

FIG. 2 is a schematic structural view of the array substrate according to Embodiment 1 of the present invention;

Fig. 3 is a sectional view of AA' of Fig. 2;

FIG. 4 is another schematic structural view of the array substrate according to Embodiment 1 of the present invention;

FIG. 5 is a cross-sectional view of AA' of FIG. 4 .

The reference signs are: 1, pixel unit; 2, gate line; 3, data line; 11, thin film transistor; 12, pixel electrode; 101, base; 102, common electrode; 103, gate insulating layer; 104, conductive Electrode; 105, passivation layer.

detailed description

In order to enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

An array substrate comprising pixel units arranged in a matrix, each pixel unit is provided with a pixel electrode and a common electrode insulated from each other, and is provided between the layer where the pixel electrode is located and the layer where the common electrode is located. The conductive electrode is insulated from the pixel electrode, and the projections of the two on the substrate are at least partially overlapped, and the conductive electrode is electrically connected to the common electrode.

Those skilled in the art can understand that the bipolar plates of the pixel capacitance Cst on the array substrate are formed by the overlapping parts of the pixel electrode and the common electrode, and the value of the pixel capacitance Cst is related to the distance between the pixel electrode and the common electrode. The spacing is inversely proportional, that is, the larger the spacing between the pixel electrode and the common electrode, the smaller the value of the pixel capacitance Cst, otherwise the reverse is true. In the array substrate of this embodiment, by forming a conductive electrode electrically connected to the common electrode between the pixel electrode and the common electrode, and at least partially overlapping the conductive electrode with the pixel electrode, the connection between the conductive electrode and the common electrode The structure and the pixel electrode form a pixel capacitance Cst. It can be understood that the conductive electrode is closer to the pixel electrode than the common electrode, thus reducing the distance between the two plates constituting the pixel capacitance Cst, thereby increasing the value of the pixel capacitance Cst, according to the jump voltage The calculation formula of ΔVp: ΔVp=Cgs_on*(Vgh-Vgl)/(Cgs_on+Cst+Clc), where Cgs_on is the gate-source capacitance; Vgh is the high potential applied to the gate line; Vgl is the low potential applied to the gate line; Cst is the pixel capacitance; Clc is the liquid crystal capacitance, it can be seen that the value of the pixel capacitance Cst increases, and the jump voltage ΔVp decreases, thereby solving the problem of poor display caused by the large jump voltage ΔVp in the prior art.

At the same time, in the array substrate of this embodiment, since the conductive electrodes are electrically connected to the common electrodes, the connection structure between the conductive electrodes and the common electrodes is equivalent to the common electrodes in the prior art, and the conductive electrodes are connected in parallel with the common electrodes, so Compared with the resistance of the common electrode in the prior art, the resistance of the connection structure between the conductive electrode and the common electrode in this embodiment is relatively small, so the uniformity of the voltage of the common electrode of the display panel can be improved.

The array substrate of this embodiment will be described below in combination with specific implementation methods.

Example 1:

This embodiment provides an array substrate, which includes a plurality of gate lines and a plurality of data lines arranged crosswise, pixel units arranged in a matrix, each pixel unit is provided with a pixel electrode and a common electrode insulated from each other, and A conductive electrode disposed between the layer where the pixel electrode is located and the layer where the common electrode is located, the conductive electrode is insulated from the pixel electrode, and the projections of the two on the substrate at least partially overlap, the conductive electrode and the pixel electrode are at least partially overlapped. The common electrode is electrically connected. Wherein, each pixel unit is connected with a gate line and a data line.

As shown in FIGS. 2 and 3 , as a preferred mode of this embodiment, each row of pixel units 1 is connected to the same gate line 2 , and each column of pixel units 1 is connected to the same data line 3 . Wherein, each pixel unit 1 includes a thin film transistor 11 , the source of the thin film transistor 11 is connected to the data line 3 , and the drain is connected to the pixel electrode 12 .

The structure of the array substrate will be further described below in combination with the method for preparing the array substrate.

Firstly, on the substrate 101 through a patterning process, form the gate of the thin film transistor 11 in each pixel unit 1 and the gate line 2 connected to the gate. Preferably, the common electrode 102 of each pixel unit 1 is also formed at the same time , and a common electrode line (not shown) that connects each common electrode 102 together; at this time, deposit a gate insulating layer 103; form the active region of the thin film transistor 11 through a patterning process on the gate insulating layer 103 pattern; then, form the first via hole through the gate insulating layer 103 through a patterning process for electrically connecting the common electrode 102 and the conductive electrode 104; form the source of the thin film transistor 11 through a patterning process on the layer where the active layer is located , the drain electrode and the pattern of the data line 3 connected to the source electrode, preferably at the same time, a conductive electrode 104 is also formed, so far the electrical connection between the conductive electrode 104 and the common electrode 102 is completed; then the passivation layer 105 is formed; next Form through the passivation layer 105 through the patterning process, the second via hole used to connect the drain of the thin film transistor 11 and the pixel electrode 12, and finally form the pixel electrode 12, at this time, the pixel electrode 12 is connected to the thin film transistor 11 through the second via hole The drain is electrically connected.

It can be seen from the above that, preferably, the common electrode 102 is arranged on the same layer as the gate line 2 and made of the same material; the conductive electrode 104 is arranged on the same layer as the data line 3 and made of the same material. At this time, the common electrodes 102 and the gate lines 2 can be formed by one patterning process, and the conductive electrodes 104 and the data lines 3 can be formed by one patterning process, so process steps can be saved and production efficiency can be improved. Of course, the conductive electrode 104 can also be prepared separately, as long as it is disposed between the pixel electrode 12 and the common electrode 102 and at least partially overlaps with the pixel electrode 12 .

As shown in Figures 4 and 5, as another preferred mode of this embodiment, the gate lines 2 in two adjacent rows are connected to the pixel units 1 in the same row at the same time, and each data line 3 is connected to the pixel units in two adjacent columns at the same time. The above-mentioned pixel units 1, and the different gate lines 2 connected to the two pixel units 1 connected to the same data line 3 in the same row of pixel units 1. Wherein, each pixel unit 1 includes a thin film transistor 11 , the source of the thin film transistor 11 is connected to the data line 3 , and the drain is connected to the pixel electrode 12 . It can be understood that the arrangement of the pixel units 1 on the array substrate is a double gate structure.

Preferably, the conductive electrode 104 is disposed between two adjacent columns of pixel units 1 connected to two different data lines 3 . That is to say, each conductive electrode 104 spans and overlaps the pixel electrodes 12 in two pixel units 1 . The reason for this setting is that there is a certain gap between two adjacent pixel units 1, at this time, setting the conductive electrode 104 here not only has less influence on the aperture ratio of the array substrate, but also can block the gap between the two adjacent pixel units 1. The gap between the pixel units 1 prevents light leakage, thereby further reducing the area of the black matrix and increasing the aperture ratio. It should be noted that the shape and size of the conductive electrodes 104 are not limited in this embodiment.

Specifically, a gate insulating layer 103 and a passivation layer 105 are also provided between the layer where the pixel electrode 12 is located and the layer where the common electrode 102 is located, and the conductive electrode 104 is provided between the gate insulating layer 103 and the passivation layer 105, wherein The conductive electrode 104 is electrically connected to the common electrode 102 through the first via hole penetrating the gate insulating layer 103 , and the drain of the thin film transistor 11 is electrically connected to the pixel electrode 12 through the second via hole penetrating the passivation layer 105 .

Preferably, the conductive electrode 104 is arranged on the same layer as the data line 3 and made of the same material, and the common electrode 102 is arranged on the same layer as the gate line 2 and made of the same material. At this time, the conductive electrodes 104 and the data lines 3 can be formed by a single patterning process, and the common electrodes 102 and the gate lines 2 can be formed by a single patterning process, thereby greatly saving process steps and improving production efficiency.

It should be noted that the order of the preparation method of this preferred mode is roughly the same as that of the above-mentioned method, but the position of each structure on the formed array substrate is different, so it will not be described in detail.

To sum up, in the array substrate provided in this embodiment, the distance between the conductive electrode 104 and the pixel electrode 12 is closer than that of the common electrode 102, so the distance between the two plates constituting the pixel capacitance Cst is reduced, thereby increasing The value of the pixel capacitance Cst is calculated according to the calculation formula of the jump voltage ΔVp: ΔVp=Cgs_on*(Vgh-Vgl)/(Cgs_on+Cst+Clc), wherein, Vgh is the high potential applied by the gate line 2; Vgl is the gate line 2 applied low potential; Cst is the pixel capacitance; Clc is the liquid crystal capacitance, it can be seen that the value of the pixel capacitance Cst increases, and the jump voltage ΔVp decreases, thereby solving the problem caused by the large jump voltage ΔVp in the prior art Show bad questions.

Meanwhile, in the array substrate of this embodiment, since the conductive electrode 104 is electrically connected to the common electrode 102, the connection structure between the conductive electrode 104 and the common electrode 102 is equivalent to the common electrode 102 in the prior art, and the conductive electrode 104 is connected to the common electrode 102. The common electrodes 102 are connected in parallel, so compared with the resistance of the common electrodes 102 in the prior art, the resistance of the connection structure between the conductive electrodes 104 and the common electrodes 102 in this embodiment is smaller, so the voltage of the common electrodes 102 of the display panel can be increased of uniformity.

Example 2:

This embodiment provides a display device, which includes the array substrate described in any one of the above embodiments.

An embodiment of the present invention also provides a display device, which includes any one of the above-mentioned array substrates. The display device may be any product or component with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Since the display device of this embodiment adopts the above-mentioned array substrate, it has a large aperture ratio, low energy consumption, high refresh rate, and good display quality.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (7)

1. a kind of array base palte, it includes the pixel cell for being arranged in matrix, is provided with each pixel cell mutually absolutely The pixel electrode and public electrode of edge, it is characterised in that the array base palte also includes being arranged on layer where the pixel electrode With the public electrode conductive electrode between layers,

The conductive electrode and pixel electrode insulation set, and both projections in substrate at least partly coincidence, the conduction Electrode is electrically connected with the public electrode；

The array base palte also includes a plurality of grid line and a plurality of data lines of intersection and insulation set, and each pixel cell connects Connect a data line and a grid line；

Grid line described in two adjacent lines is connected with pixel cell described in a line simultaneously, is connected simultaneously described in two adjacent columns per data line Pixel cell, and with the different grid lines connected in one-row pixels unit from two pixel cells that same data wire is connected；

The conductive electrode is between two adjacent column pixel cells of two different pieces of information lines of connection.

2. array base palte according to claim 1, it is characterised in that the conductive electrode is set with the data wire with layer Put, and material is identical.

3. array base palte according to claim 1, it is characterised in that the public electrode is set with the grid line with layer, And material is identical.

4. array base palte according to claim 1, it is characterised in that each pixel cell includes a film crystal Pipe, the source electrode of the thin film transistor (TFT) connects the data wire, and drain electrode connection pixel electrode, grid connects the grid line.

5. array base palte according to claim 4, it is characterised in that layer and the common electrical where the pixel electrode Pole is additionally provided with gate insulator and passivation layer between layers；The conductive electrode be arranged on the gate insulator with it is described Between passivation layer, and the conductive electrode is electrically connected by the first via through the gate insulator and the public electrode Connect.

6. array base palte according to claim 5, it is characterised in that the drain electrode of the thin film transistor (TFT) passes through through passivation Second via of layer is electrically connected with the pixel electrode.

7. a kind of display device, it is characterised in that the display device includes the array described in any one in claim 1-6 Substrate.