CN104426548B - A kind of analog-to-digital conversion sample circuit and computation chip - Google Patents
A kind of analog-to-digital conversion sample circuit and computation chip Download PDFInfo
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Abstract
The present invention provides a kind of analog-to-digital conversion sample circuit and computation chip, and the analog-to-digital conversion sample circuit includes：Modulator, digital filtering and extracting unit, phase-correcting circuit；The phase-correcting circuit includes the first delay unit and the second delay unit, the input of first delay unit output end respectively with the modulator, the digital filtering and extracting unit is connected, and second delay unit is connected with the output end of the digital filtering and extracting unit.The data signal that the present invention is exported by the data signal and digital filtering and extracting unit that are exported respectively to modulator carries out delay process, reduces the area of analog-to-digital conversion sample circuit, reduces the manufacture difficulty, cost and power consumption of analog-to-digital conversion sample circuit.
Description
Technical field
The present invention relates to metering field, more particularly to a kind of analog-to-digital conversion sample circuit and computation chip.
Background technology
China is that an electric energy meter applies big country, annual whole nation demand about 30,000,000, and the electric energy meter of current China is main
There are stem-winder, Mechatronics energy meter and all-electronin electric energy meter.The metering device of all-electronin electric energy meter is mainly by special
Computation chip is constituted with peripheral associated hardware circuitry, development and the hair of progressive and electric energy meter technology with electronic technology
Exhibition, reliability, stability, the economy of special computation chip are all greatly improved.
The electric energy computation chip of current main flow, inside uses analog-digital converter（Analog to Digital
Converter, abbreviation ADC）Sample circuit, logical circuit of arithmetic and the structure for controlling circuit.Computation chip uses arithmetical logic
Processing of circuit analog-to-digital conversion sample circuit collection electric current and voltage signal, and obtain corresponding power, virtual value with it is other
Electric parameter information, while the output pulse signal related to electric flux.
Generally, analog-to-digital conversion sample circuit includes：Modulator, digital filtering and extracting unit, delay unit.Wherein, prolong
Shi Danyuan is used for the phase for adjusting the data signal of modulator output, in order to realize accurate phasing, delay unit correction
Minimum interval it is equal with the sampling clock cycle of modulator, while in order to meet maximum phase correction demand, modulus
Change the very huge of time-delay unit circuit design in sample circuit so that the area of analog-to-digital conversion sample circuit, manufacture
Difficulty and cost are all than larger.
At present, the logical circuit of arithmetic in computation chip mainly includes electric voltage frequency and phase angle measurement circuit, power measurement
Circuit and voltage, current effective value measuring circuit.Wherein, realized more than electric voltage frequency and phase angle measurement using software mode, power,
Voltage, the separate setting of measuring circuit of current effective value measure different electric parameters, substantial amounts of electric parameter metering electricity respectively
Road causes the area and power consumption of computation chip all than larger, and cost is higher.
The content of the invention
The present invention provides a kind of analog-to-digital conversion sample circuit and computation chip, to solve existing analog-to-digital conversion sample circuit
Time-delay unit circuit is huge and computation chip in computation chip area, power consumption, manufacture difficulty caused by numerous measuring circuit
With cost all than it is larger the problem of.
One aspect of the present invention provides a kind of analog-to-digital conversion sample circuit, it is characterised in that including：Modulator, numeral
Filtering and extracting unit, phase-correcting circuit；The phase-correcting circuit includes the first delay unit and the second delay unit, institute
The input for stating output end of first delay unit respectively with the modulator, the digital filtering and extracting unit is connected, institute
The output end that the second delay unit is stated with the digital filtering and extracting unit is connected.
Another aspect of the present invention provides a kind of computation chip, it is characterised in that including：Three analog-to-digital conversion sampling electricity
Road, the first electric parameter metering circuit being connected respectively with three analog-to-digital conversion sample circuits；
Three analog-to-digital conversion sample circuits, for voltage signal respectively to input, live wire current signal, zero line electricity
Stream signal is sampled, and voltage signal, live wire current signal, neutral line current signal that sampling is obtained are respectively outputted to voltage
Output end, live wire current output terminal, neutral line current output end；
The first electric parameter metering circuit, for according to sample obtained voltage signal, live wire current signal, zero
Line current signal is calculated, and obtains respective value, the voltage and zero of the phase angle of respective value, voltage and the live wire electric current of electric voltage frequency
The respective value of the phase angle of line current.
The analog-to-digital conversion sample circuit that the present invention is provided, by being exported respectively to modulator and digital filtering and extracting unit
Data signal carry out delays time to control so that the quantity of the time-delay trigger in analog-to-digital conversion sample circuit can be reduced, and then
Reduce the area of analog-to-digital conversion sample circuit, reduce manufacture difficulty, cost and the power consumption of analog-to-digital conversion sample circuit, in addition, this
The computation chip that invention is provided realizes the measurement of electric voltage frequency and phase angle using hardware circuit, and the manufacture for reducing computation chip is difficult
Degree, saves the manufacturing cost of computation chip.
Brief description of the drawings
The analog-to-digital conversion sample circuit structural representation that Fig. 1 provides for prior art；
The analog-to-digital conversion sampling circuit embodiment structural representation that Fig. 2 provides for the present invention；
The structural representation of computation chip embodiment one that Fig. 3 provides for the present invention；
Fig. 4 be Fig. 3 shown in computation chip embodiment one in the first electric parameter metering circuit structural representation；
Fig. 5 show the signal principle figure of the first electric parameter metering circuit shown in Fig. 4；
Fig. 6 show the structural representation for the computation chip embodiment two that the present invention is provided；
Fig. 7 be Fig. 6 shown in computation chip embodiment two in the second electric parameter metering circuit structural representation；
Fig. 8 show the structural representation for the computation chip embodiment three that the present invention is provided；
Fig. 9 be Fig. 8 shown in computation chip embodiment three in the 3rd electric parameter metering circuit structural representation；
Figure 10 show the structural representation for the computation chip example IV that the present invention is provided.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The analog-to-digital conversion sample circuit structural representation that Fig. 1 provides for prior art.As shown in figure 1, the analog-to-digital conversion is adopted
Sample circuit includes：Modulator 10, digital filtering and extracting unit 11, delay unit 12.Wherein, modulator input input simulation
Signal, the output end of modulator connects the input of delay unit, and the output end connection digital filtering of delay unit and extraction are single
The input of member.Modulator is used to analog signal being modulated into the data signal of 1；Delay unit is used for according in computation chip
Control circuit（Not shown in Fig. 1）The phase correcting value stored in middle register and communication module carries out phasing, passes through
It is delayed to adjust the phase of data signal, if being generally made up of stem structure, function identical time-delay trigger；Digital filtering and take out
Take element circuit to be used to the data signal of 1 being converted into N position digital signals, and the data signal of N be subjected to filtering extraction,
To improve the analog-to-digital conversion sample circuit signal to noise ratio, wherein, N is the analog-to-digital conversion sample circuit actual design bit wide.
The analog-to-digital conversion sampling circuit embodiment structural representation that Fig. 2 provides for the present invention, as shown in Fig. 2 the modulus turns
Changing sample circuit includes：Modulator 20, digital filtering and extracting unit 21, phase-correcting circuit 22；The phase-correcting circuit
Including the first delay unit 220 and the second delay unit 221, the output of first delay unit respectively with the modulator
The input connection at end, the digital filtering and extracting unit, second delay unit and the digital filtering and extraction are single
The output end connection of member.
In the present embodiment, the modulator is used to analog signal being modulated into the data signal of L；The phasing electricity
Road is used to adjust the phase of data signal by carrying out delays time to control to data signal, and specifically, the first delay unit is used for
The phase of the data signal of modulator output is adjusted, the second delay unit is used for the number for adjusting digital filtering and extracting unit output
The phase of word signal；The digital filtering and extracting unit are used to carry out the data signal of input down-sampled processing, output and
The equal data signal of bit wide of analog-to-digital conversion sample circuit design.
Specifically, first delay unit includes M time-delay trigger, and second delay unit includes K delay
Trigger, M=（X-1）* L, X are the down-sampled multiple of the digital filtering and extracting unit, and L is the number that the modulator is exported
The digit of word signal, K=Y*N, N is the digit for the data signal that the digital filtering and extracting unit are exported, and Y believes for N bit digitals
The corresponding time-delay trigger number of bits per inch word signal difference in number, M, K, X, N, L, Y is positive integer.
In a kind of feasible implementation, the first delay unit and the second delay unit are by structure identical time-delay trigger
Constitute, the first delay unit be used for modulator export L position digital signals carry out delays time to control, the second delay unit be used for pair
Digital filtering and the N position digital signals of extracting unit output carry out delays time to control.
Further, the minimum interval of the first delay unit correction is equal to the sampling clock cycle of modulator, second
The minimum interval of delay unit correction is equal to the clock cycle of digital filtering and extracting unit.For example, if modulator
Sample frequency be fs, the down-sampled multiple of digital filtering and extracting unit is for the frequency of X, i.e. digital filtering and extracting unit
fs/ X, then the minimum interval of the first delay unit correction is 1/fs, the minimum interval of the second delay unit correction is X/
fs, it can be seen that the first delay unit is accomplished that smart phasing, and the second delay unit is accomplished that thick phasing.
Generally, when carrying out delay process to the L position digital signals that modulator is exported, at least need L time-delay trigger same
When the L position digital signals are handled, and in order to the L position digital signals in X/fsDelays time to control can be carried out in time,
Then the quantity M of time-delay trigger need to be designed as the down-sampled multiple of digital filtering and extracting unit in the first delay unit（X-1）
Individual L, i.e. M=（X-1）*L；Similarly, when N position digital signals progress delay process is output as to digital filtering and extracting unit, extremely
N number of time-delay trigger is needed less while handling the N position digital signals, in order to realize full-time to the N position digital signals
In the range of delay process, the quantity of time-delay trigger need to be set to N integral multiple, i.e. K=Y*N, Y tables in the second delay unit
Show the number for the time-delay trigger that respectively N is set for the bits per inch word signal in data signal, Y is positive integer, and Y is according to numeral
The clock cycle of filtering and extracting unit combines different application occasion value.
Preferably, L=1, modulator herein can be sigma-delta modulator, or other output one bit digital signals
Modulator, the present embodiment do not limited this.To realize analog signal to the high-precision conversion of data signal, modulator is adopted
Sample frequency is typically much deeper than the bandwidth of analog signal of the sample frequency much larger than 2 times of Nyquist rate, i.e. modulator.Accordingly
Ground, the first delay unit is used to carry out delay process to the one bit digital signal that modulator is exported, and digital filtering is used with extracting unit
N position digital signals are converted into the one bit digital signal for exporting the first delay unit, and the data signal of N is extracted
Filtering, to improve the signal to noise ratio of analog-to-digital conversion sampling.
Specifically, the usage quantity of each delay unit is controlled to store in register and communication module in circuit by computation chip
Phase correcting value determine that the minimum interval that phase correcting value is corrected by phase deviation and each delay unit is determined.For
Modulator output signal is 1, and design bit wide is the analog-to-digital conversion sample circuit of N, when the phase value for needing to correct is corresponding
Delay time t is between 1/fsAnd X/fsBetween when, ［ t*f is accessed in circuitsTime-delay trigger in individual first delay unit；When
The corresponding delay time t of phase value of correction is needed to be equal to X/fsWhen circuit in access N number of delay in the second delay unit and touch
Send out device；When the corresponding delay time t of phase value for needing to correct is between X/fsAnd 2*X/fsWhen, the delay of access second is single in circuit
［ (the t-X/f in N number of time-delay trigger and the first delay unit in members)*fsIndividual time-delay trigger, the like, when t is big
In R*X/fsWhen, the ［ (t-R* in R*N time-delay trigger and the first delay unit in the second delay unit is accessed in circuit
X/fs)*fsIndividual time-delay trigger.For example, it is assumed that the clock frequency of the analog-to-digital conversion sample circuit containing sigma-delta modulator is
2.048 megahertz（MHz）, bit wide is 20, after 256 times of digital filterings and extraction, and the clock frequency of output data is 8 kilo hertzs
Hereby（kHz）, the cycle is 125 microseconds（μs）, according to the solution of the present invention, time-delay trigger is designed in the quantity of the first delay unit
It is that the bits per inch word signal in 20 position digital signals sets 2 time-delay triggers, i.e., second respectively in the present embodiment for 255
The quantity of time-delay trigger is 40 in delay unit, and the phase value if desired corrected is 3.6 °, for 50Hz industrial-frequency alternating currents
For, the time quantum that need to be corrected is 200 μ s, between 125 μ s and 250 μ s, then when Shi Jishiyong, and second prolongs in access circuit
The quantity of time-delay trigger in Shi Danyuan is 20, the quantity of the time-delay trigger of the first delay unit for（200-125）*
2.048 ］ it is individual, i.e., at 154 so that 3.6035 ° of signal lag, required precision can be met.If by the solution of the present invention, by first
Delay unit and the second delay unit composition the achievable maximum correction scope of phase-correcting circuit for 2*125 μ s+125 μ s=
375 μ s, if by prior art, being that can reach the delay unit identical maximum correction scope designed by the solution of the present invention, prolonging
The quantity of time-delay trigger need to be designed as in Shi Danyuan：375 μ s/ (1/2.048MHz)=768.If prior art is when using
Realize with identical correction accuracy of the present invention, correct 3.6 ° of phase error needs 410 time-delay triggers altogether.As can be seen that
The quantity of time-delay trigger in still actual use prior art delay unit is either designed all than the technology of the present invention
How many quantity of scheme is.
The analog-to-digital conversion sample circuit that the present embodiment is provided, is filtered by the data signal and numeral that are exported respectively to modulator
Ripple and the data signal of extracting unit output carry out delay process, reduce time-delay trigger in analog-to-digital conversion sample circuit
Quantity, the area for reducing analog-to-digital conversion sample circuit, the manufacture difficulty for reducing circuit, cost and power consumption.
Fig. 3 show the structural representation for the computation chip embodiment one that the present invention is provided, as shown in figure 3, the metering core
Piece includes：Three analog-to-digital conversion sample circuits 30,31,32, first be connected respectively with three analog-to-digital conversion sample circuits
Electric parameter metering circuit 33；Wherein, three analog-to-digital conversion sample circuits, for voltage signal respectively to input, live wire
Current signal, neutral line current signal are sampled, and will sample obtained voltage signal, live wire current signal, neutral line current are believed
Number it is respectively outputted to voltage output end, live wire current output terminal, neutral line current output end；The first electric parameter metering circuit,
Voltage signal, live wire current signal, neutral line current signal for being obtained according to the sampling are calculated, and obtain electric voltage frequency
Respective value, the respective value of the phase angle of voltage and live wire electric current, the respective value of the phase angle of voltage and neutral line current.
Preferably, in the present embodiment, the modulus that three analog-to-digital conversion sample circuits can be provided using the present invention turns
Change sample circuit.
Fig. 4 is the structural representation of the first electric parameter metering circuit in the computation chip embodiment one shown in Fig. 3, such as Fig. 4
Shown, the first electric parameter metering circuit 33 includes：First low pass filter 400, the second low pass filter 401, the 3rd low pass filtered
Ripple device 402, the first zero-crossing pulse generator 403, the second zero-crossing pulse generator 404, the 3rd zero-crossing pulse generator 405, electricity
Press frequency counter 406, the first phase angle counter 407, the second phase angle counter 408；
The input of first low pass filter connects the voltage output end, the output of first low pass filter
The input of end connection the first zero-crossing pulse generator, the output end of the first zero-crossing pulse generator connects the electricity
Press input, the first input end of the first phase angle counter, the first input end of the second phase angle counter, institute of frequency counter
Stating the output end of electric voltage frequency counter is used for the respective value of output voltage frequency；
The input of second low pass filter connects the live wire current output terminal, second low pass filter
Output end connects the input of the second zero-crossing pulse generator, the output end connection institute of the second zero-crossing pulse generator
The second input of the first phase angle counter is stated, the output end of the first phase angle counter is used for output voltage and live wire electric current
The respective value of phase angle；
The input of 3rd low pass filter connects the neutral line current output end, the 3rd low pass filter
Output end connects the input of the 3rd zero-crossing pulse generator, the output end connection institute of the 3rd zero-crossing pulse generator
The second input of the second phase angle counter is stated, the output end of the second phase angle counter is used for output voltage and neutral line current
The respective value of phase angle.
In the present embodiment, the voltage signal that analog-to-digital conversion sampling circuit samples are obtained filters out harmonic wave through the first low pass filter
After component signal, then the first zero-crossing pulse generator is inputed to, the first zero-crossing pulse generator changes in voltage signal from negative value
To on the occasion of when produce a pulse signal, the zero-crossing pulse signal of electric voltage frequency counter using adjacent voltage signal is used as one
The starting point and ending point in counting cycle, one counts the respective value that cycle count value is electric voltage frequency.
Specifically, started counting up when a voltage zero-cross pulse signal carrys out interim electric voltage frequency counter, to next electricity
Press through pair that zero pulse signal carrys out the interim count value, as electric voltage frequency for stopping counting and exporting now electric voltage frequency counter
Should be worth, then start counting up again by counter O reset and again, wait voltage zero-cross pulse signal next time, with this it is reciprocal come
The respective value of electric voltage frequency is continuously calculated, can be counted according to the count frequency of the count value of electric voltage frequency and electric voltage frequency counter
Calculate the frequency of voltage on power line.
Correspondingly, live wire current signal, neutral line current signal are filtered through the second low pass filter, the 3rd low pass filter respectively
After harmonic component signal, then by the second zero-crossing pulse generator, the 3rd zero-crossing pulse generator, believe respectively in live wire electric current
Number, neutral line current signal from negative value be changed on the occasion of when produce a pulse signal, the first phase angle counter made with voltage signal
To count the starting point in cycle, the terminating point in the cycle of counting, meter are used as using the zero-crossing pulse signal of adjacent live wire current signal
Number can draw the respective value of voltage and live wire current phase angle, starting of the second phase angle counter using voltage signal as the cycle of counting
Point, using the zero-crossing pulse signal of adjacent neutral line current signal as the terminating point in the cycle of counting, counting can draw voltage and zero
The correspondence of line current phase angle.
Specifically, started counting up when a voltage zero-cross pulse signal carrys out interim first phase angle counter, until adjacent
Live wire current over-zero pulse signal comes the interim count value for stopping counting and exporting the first phase angle counter, as voltage and live wire
The respective value of current phase angle, then again by the first phase angle counter O reset, voltage zero-cross pulse signal arrives it next time for wait
After start counting up, continue this process, with this reciprocal respective value continuously to calculate voltage and live wire current phase angle.According to voltage
The phase angle of voltage and live wire electric current can be calculated with the respective value of live wire current phase angle and the respective value of electric voltage frequency.
Correspondingly, started counting up when a voltage zero-cross pulse signal carrys out interim second phase angle counter, until next
Neutral line current zero-crossing pulse signal comes the interim count value for stopping counting and exporting the second phase angle counter, as voltage and zero line
The respective value of current phase angle, then again by the second phase angle counter O reset, voltage zero-cross pulse signal arrives it next time for wait
After start counting up, continue this process, with this reciprocal phase angle respective value continuously to calculate voltage and neutral line current.According to voltage
The phase angle of voltage and neutral line current can be calculated with the respective value of neutral line current phase angle and the respective value of electric voltage frequency.
Fig. 5 show the signal principle figure of the first electric parameter metering circuit shown in Fig. 4.As shown in figure 5, a is input
Voltage signal figure, b is the live wire current signal figure of input, and c is the neutral line current signal graph of input, and d is the production of the first zero-crossing pulse
The voltage zero-cross pulse signal that raw device is produced, e is the live wire current over-zero pulse signal that the second zero-crossing pulse generator is produced, f
The neutral line current zero-crossing pulse signal produced for the 3rd zero-crossing pulse generator, g is the counting figure of electric voltage frequency counter, and h is
The counting figure of first phase angle counter, j is the counting figure of the second phase angle counter.
Count value of the electric voltage frequency counter within a counting cycle is D as shown in Figure 51, i.e. the correspondence of electric voltage frequency
It is worth for D1, count value of the first phase angle counter within a counting cycle is D2,, i.e. voltage is corresponding with live wire current phase angle
It is worth for D2, count value of the second phase angle counter within a counting cycle is D3,, i.e. voltage is corresponding with neutral line current phase angle
It is worth for D3If the count frequency of electric voltage frequency counter is f, and electric voltage frequency actual value is（f/D1）Hz, voltage and live wire electric current
Phase angle actual value is（D2/D1）× 360 °, voltage is with neutral line current phase angle actual value（D3/D1）×360°.
The computation chip that the present embodiment is provided, is realized to the respective value of electric voltage frequency, voltage and live wire using hardware circuit
The survey calculation of the respective value of the respective value of current phase angle, voltage and neutral line current phase angle, software is used compared to prior art
The method of calculating, simplifies the circuit structure of computation chip, reduces the manufacturing cost of computation chip.
The structural representation of computation chip embodiment two that Fig. 6 provides for the present invention.As shown in fig. 6, in the metering shown in Fig. 3
On the basis of chip embodiment one, the computation chip embodiment two that provides of the present invention also include respectively with three analog-to-digital conversions
Second electric parameter metering circuit 34 of sample circuit connection.
Fig. 7 be Fig. 6 shown in computation chip embodiment two in the second electric parameter metering circuit structural representation.Such as Fig. 7
Shown, the second electric parameter metering circuit includes：First counter 700,90-degree phase shifter 701, the first data selector 702,
Two data selectors 703, the 3rd data selector 704, the 4th data selector 705, the first multiplier 706, the 4th low pass filtered
Ripple device 707, first adder 708, the second multiplier 709, the first decoder 710；
First input end, the 3rd input of first data selector are all connected with the live wire current output terminal, institute
State the second input of the first data selector, the 4th input and be all connected with the neutral line current output end, first data
The output end of selector is connected to the first input end of first multiplier；
First input end, the second input of second data selector are all connected with the voltage output end, described
The 3rd input, the 4th input of two data selectors are all connected with the output end of the 90-degree phase shifter, 90 degree of phase shifts
The input of device connects the voltage output end, and the output end of second data selector is connected to first multiplier
Second input；
The output end of first multiplier connects the input of the 4th low pass filter, the 4th LPF
The output end of device connects the first input end of the first adder；
The first input end connection live wire active power compensation control end of 3rd data selector, the 3rd data
The second input section connection zero line active power compensation control end of selector, the 3rd input of the 3rd data selector connects
Start to exchange fire line reactive power compensation control end, the 4th input connection zero line reactive power compensation control of the 3rd data selector
End processed, the output end of the 3rd data selector is connected to the second input of the first adder；
The output end of the first adder connects the first input end of second multiplier；
The first input end connection live wire active power gain control end of 4th data selector, the 4th data
The second input section connection zero line active power gain control end of selector, the 3rd input of the 4th data selector connects
Start to exchange fire line reactive power gain control end, the 4th input connection zero line reactive power gain control of the 4th data selector
End processed, the output end of the 4th data selector is connected to the second input of second multiplier；
The input of first decoder connects the output end of second multiplier；
First data selector, the second data selector, the 3rd data selector, the 4th data selector, first
Output end of the selection signal end of decoder with first counter is connected, the first output end of first decoder,
Second output end, the 3rd output end, the 4th output end are used for respective value, the zero line active power for exporting live wire active power successively
Respective value, the respective value of live wire reactive power, the respective value of zero line reactive power.
In the present embodiment, each data selector and the first decoder can be built realization, the first meter by simple gate circuit
Number device can realize that the present embodiment is not limited this with up counter or subtraction count device.
The digit of first counter is determined according to each data selector input quantity and the first decoder output quantity.
For example, in the present embodiment, each data selector has four inputs, the first decoder to have four output ends, can select 2
The up counters of 2 systems of position controls the data that each data selector and the first decoder are selected.The input of first counter
For the clock signal of fixed frequency, different count status number that the frequency of the clock signal is exported by the first counter and defeated
The signal frequency for entering the second electric parameter metering circuit determines that generally, the clock signal frequency of the first counter of input is input the
The product of the signal frequencies of the two electric parameter metering circuits count status number different from the first counter.In the present embodiment, the
The different count status of the up counter output for 22 systems that one counter is used have 00,01,10,11,4 counting shape
State, then 4 times of the signal frequency for inputting the clock signal frequency of the first counter to input the second electric parameter metering circuit,
The voltage that even inputs, live wire electric current, neutral line current signal frequency are 8kHz, and the first counter is then cut with 32kHz frequency
Change each data selector of control and the first decoder.The work of each multiplier and first adder in second electric parameter metering circuit
Working frequency determines according to the frequency for the signal for inputting each multiplier and first adder, usual each multiplier and first adder
Working frequency is more than the clock signal frequency of the first counter of input.For example, when the first rolling counters forward is 00, each data
Selector selects the data of first input end, and the first decoder of correspondence selects the first output end output data, circuit counting live wire
The respective value of active power；During first clock signal input, the first rolling counters forward is 01, each data selector selection second
The data of input, the first decoder of correspondence selects the second output end output data, the correspondence of circuit counting zero line active power
Value；During second clock signal input, the first rolling counters forward is 10, and each data selector selects the data of the 3rd input,
The first decoder of correspondence selects the 3rd output end output data, the respective value of circuit counting live wire reactive power；3rd clock
When signal is inputted, the first rolling counters forward is 11, and each data selector selects the data of the 4th input, the first decoder of correspondence
Select the 4th output end output data, the respective value of circuit counting zero line reactive power；During the 4th clock signal input, first
Rolling counters forward is 00, the respective value of circuit counting live wire active power；Reciprocal realized with this to each data selector, first
The switching control of decoder and computing circuit.
In the present embodiment, live wire active power compensation control end, zero line active power compensation control end, live wire reactive power
Compensate control end, live wire reactive power compensation control end, live wire active power gain control end, zero line active power gain control
End, live wire reactive power gain control end and zero line reactive power gain control end control posting in circuit with computation chip respectively
Storage is corresponding with the corresponding output end of communication module, respective value, zero line for the live wire active power that measures computation chip
The respective value of the respective value of active power, the respective value of live wire reactive power and zero line reactive power is compensated and gain school
Just, to eliminate the error in circuit.
Specifically, when the first rolling counters forward is 00, the second electric parameter metering circuit counting is active on live wire
Power respective value.Correspondingly, the first data selector selection live wire current signal, the second data selector selection voltage signal,
3rd data selector selects live wire active power thermal compensation signal, the 4th data selector selection live wire active power gain letter
Number, the first decoder selects the first output end output live wire active power respective value, and accordingly, the first multiplier is by live wire electric current
Multiplying is carried out with voltage, the product drawn inputs to first adder, the first addition after being filtered through the 4th low pass filter
The live wire active power thermal compensation signal phase that device inputs the product of filtered live wire electric current and voltage with the 3rd data selector
Plus the product of the live wire electric current and voltage is compensated, the second multiplier is by the live wire electric current and the product of voltage after compensation
Calculated with live wire active power multiplied by gains and obtain the respective value of live wire active power and by the first output end of the first decoder
Output.
Correspondingly, when the first rolling counters forward is 01, the second electric parameter metering circuit counting is active on zero line
Power respective value.
Further, when the first rolling counters forward is 10, the second electric parameter metering circuit counting is nothing on live wire
Work(power respective value.Especially, the first multiplier will be entered by the voltage signal after 90 ° of phase shifter phase shifts and live wire current signal
Row multiplying, is exported after the 4th low pass filter, first adder and the second multiplier is passed through by the first decoder the 3rd
End output；Similarly, when the first rolling counters forward is 11, the second electric parameter metering circuit counting is idle work(on zero line
Rate respective value.
Further, by the live wire active power respective value in the present embodiment, zero line active power respective value, live wire
Reactive power respective value, zero line reactive power respective value, which carry out simple arithmetic, can draw actual live wire active power
Value, zero line active power value, live wire reactive power value, zero line reactive power value.
The present embodiment provide the second electric parameter metering circuit, measurement live wire active power respective value, live wire is idle
In the respective value of power, the respective value of zero line active power, the circuit of the respective value of zero line reactive power, to using identical algorithms
Computing circuit by the way of time-sharing multiplex, with prior art to the measurement of every parameter all using independent circuit compared to simple
Change circuit structure, improved the utilization rate of computing circuit, reduce area, power consumption and the manufacturing cost of circuit.
The structural representation of computation chip embodiment three that Fig. 8 provides for the present invention.As shown in figure 8, in the metering shown in Fig. 6
On the basis of chip embodiment two, the computation chip embodiment three that the present invention is provided, in addition to：Turn respectively with three moduluses
Change the 3rd electric parameter metering circuit 35 of sample circuit connection.
Fig. 9 be Fig. 8 shown in computation chip embodiment three in the 3rd electric parameter metering circuit structural representation.Such as Fig. 9
Shown, the 3rd electric parameter metering circuit includes：Second counter 900, the 5th data selector 901, the selection of the 6th data
Device 902, the 7th data selector 903, the 3rd multiplier 904, the 5th low pass filter 905, square root calculation device 906, second
Adder 907, the 4th multiplier 908, the second decoder 909；
The first input end connection live wire current output terminal of 5th data selector, the 5th data selector
Second input connects neutral line current output end, the 3rd input connection voltage output end of the 5th data selector, institute
The output end for stating the 5th data selector connects two inputs of the 3rd multiplier；
The output end of 3rd multiplier connects the input of the 5th low pass filter；
The output end of the 5th low pass bandpass filter connects the square root calculation device input；
The square root calculation device output end connects the first input end of the second adder；
The first input end connection live wire current effective value compensation control end of 6th data selector, the 6th number
According to the second input connection neutral line current virtual value compensation control end of selector, the 3rd input of the 6th data selector
End connection voltage effective value compensation control end, the output end of the 6th data selector connects the second of the second adder
Input；
The output end of the second adder connects the first input end of the 4th multiplier；
The first input end connection live wire current effective value gain control end of 7th data selector, the 7th number
Neutral line current rms gain control end, the 3rd input of the 7th data selector are connected according to the second input of selector
End connection voltage effective value gain control end, the output end of the 7th data selector connects the second of the 4th multiplier
Input；
The output end of 4th multiplier connects the input of second decoder；
5th data selector, the 6th data selector, the 7th data selector, the second decoder control end it is equal
It is connected with the output end of second counter, the first output end, the second output end, the 3rd output end of second decoder
It is used for the respective value, the respective value of neutral line current virtual value, the respective value of voltage effective value for exporting live wire current effective value successively.
In the present embodiment, each data selector and the second decoder can be built realization, the second meter by simple gate circuit
Number device can realize that the present embodiment is not limited this with up counter or subtraction count device.
The digit of second counter is according to each data selector input quantity and second in the 3rd electric parameter metering circuit
Decoder output quantity is determined, it is considered to which circuit design selects the minimum principle of part category, and the second counter herein can be with the
The first counter in two electric parameter metering circuits controls each data selector equally from the up counter of 22 systems
The data selected with the second decoder.The input of second counter is the clock signal of fixed frequency, the frequency of the clock signal
The signal frequency of the 3rd electric parameter metering circuit of different count status numbers that rate is exported by the second counter and input determines,
Generally, the clock signal frequency of the second counter of input counts for the signal frequency of the 3rd electric parameter metering circuit of input with second
The product of the different count status numbers of device.In the present embodiment, the different count status of the second counter output are 00,01,
10,11, totally 4 different count status, then input the clock signal frequency of the second counter electric for the 3rd electric parameter metering of input
4 times of the signal frequency on road.If specifically, the voltage of input, live wire electric current, neutral line current signal frequency are 8kHz, the
Two counters then come each data selector of switching control and the second decoder with 32kHz frequency.3rd electric parameter metering circuit
In each multiplier working frequency it is true according to the frequency for the signal for inputting each multiplier, square root calculation device and second adder
Fixed, generally, the working frequency of each multiplier, square root calculation device and second adder is more than the clock letter of the second counter of input
Number frequency.For example, when the second rolling counters forward is 00, each data selector selects the data of first input end, correspondence the
Two decoders select the first output end output data, the respective value of circuit counting live wire current effective value；First clock signal
During input, the second rolling counters forward is 01, and each data selector selects the data of the second input, correspondence the second decoder selection
Second output end output data, the respective value of circuit counting neutral line current virtual value；During second clock signal input, the second meter
Rolling counters forward is 10, and each data selector selects the data of the 3rd input, and the second decoder of correspondence selects the 3rd output end defeated
Go out data, the respective value of circuit counting voltage effective value；During the 3rd clock signal input, the second rolling counters forward is 11, electricity
Any action is not done on road, during the 4th clock signal input, and the second rolling counters forward is 00, circuit counting live wire current effective value
Respective value, the switching control to each data selector, the second decoder and computing circuit is back and forth realized with this.
In the present embodiment, live wire current effective value compensation control end, neutral line current virtual value compensation control end, voltage are effective
Value complement repays control end, live wire current effective value gain control end, neutral line current rms gain control end, voltage effective value gain
Control end is corresponding with the register and the corresponding output end of communication module in computation chip control circuit respectively, for metering core
The respective value of the respective value of live wire current effective value of piece measurement, the respective value of neutral line current virtual value and voltage effective value is carried out
Compensation and gain calibration, to eliminate the error in circuit.
Specifically, when the second rolling counters forward is 00, the 3rd electric parameter metering circuit counting is that live wire electric current is effective
The respective value of value.Correspondingly, the 5th data selector selection live wire current signal, the 6th data selector selection live wire electric current has
Valid value compensating control signal, the 7th data selector selection live wire current effective value gain signal, the second decoder selection first
Output end exports the respective value of live wire current effective value, accordingly, and live wire electric current is carried out square operation by the 3rd multiplier, is drawn
Product filtered through the 5th low pass filter after input to square root calculation device and carry out extracting operation, square root calculation device is by evolution
The square root of live wire current effective value afterwards inputs to second adder, and second adder is by the square root of live wire electric current and the
The live wire current effective value thermal compensation signal of six data selectors input is added to be compensated to the live wire current effective value, and the 4th
Live wire current effective value after compensation and live wire current effective value multiplied by gains are calculated and obtain live wire current effective value by multiplier
Respective value and by the second decoder the first output end export.
Further, when the second rolling counters forward is 10, the 3rd electric parameter metering circuit counting is that neutral line current has
The respective value of valid value, when the second rolling counters forward be 10 when, the 3rd electric parameter metering circuit counting be voltage effective value pair
It should be worth.
Further, by the respective value of the live wire current effective value in the present embodiment, pair of neutral line current virtual value
It should be worth, the simple arithmetic of respective value progress of voltage effective value can draw actual live wire current effective value, zero line electricity
Flow virtual value, voltage effective value.
Preferably, the second counter in the present embodiment can be with the first counter in the second electric parameter metering circuit
Same counter.
The 3rd electric parameter metering circuit that the present embodiment is provided, respective value, live wire electric current in measurement voltage effective value have
In the circuit of the respective value of valid value and the respective value of neutral line current virtual value, to using timesharing using the computing circuit of identical algorithms
The mode of multiplexing, simplifies circuit structure compared with prior art all uses independent circuit to the measurement of every parameter, improves
The utilization rate of computing circuit, reduces area, power consumption and the manufacturing cost of circuit.
A kind of structural representation for computation chip example IV that Figure 10 provides for the present invention.As shown in Figure 10, the metering
Chip includes：Analog signal sampling module 100, digital signal processing module 101, control and communication module 102；Wherein, simulate
Signal sampling module 100 includes：Three analog-to-digital conversion sample circuits 30,31,32, digital signal processing module 101 includes：First
Electric parameter metering circuit 33, the second electric parameter metering circuit 34, the 3rd electric parameter metering circuit 35；Control and communication module 102
Including：Pulse output control module 36, register and communication module 37, interruption/Super-zero control module 38.
In the present embodiment, analog signal sampling module is used to the voltage of input, live wire electric current, neutral line current being converted into number
Word signal, and the phase correcting value that the data signal obtained to sampling is inputted according to control and communication module enters horizontal phasing control.
Further, digital signal processing module is used to believe the voltage signal, live wire current signal, neutral line current of input
Number carry out in real time calculate and correlation electric energy detection, such as calculate voltage effective value respective value, the correspondence of live wire active power
Value, the respective value of zero line reactive power, detection Voltage Drop, interruption, zero passage, anti-electricity-theft, startup shunt running etc..Control and communication mould
Block, for the micro control unit MCU in metering device（Micro Control Unit, abbreviation MCU）Carry out data exchange communications,
And control the output of electrical energy pulse, interrupt zero cross signal output etc..
Specifically, register and communication module are used for correction, the compensating parameter for preserving MCU write-ins, are when in use modulus
Conversion sample circuit and each electric parameter metering circuit provide correction, compensation control, make the variable of computation chip closer actual
Value, in addition, register and communication module are additionally operable to preserve the respective value of each measured value of each electric parameter metering circuit output, and it is defeated
Go out to MCU, it is that can obtain actual live wire wattful power that the respective value of each electric parameter of input is carried out simple arithmetic by MCU
Rate value, zero line active power value, live wire reactive power value, zero line reactive power value, voltage effective value, live wire current effective value and
Neutral line current virtual value；Pulse output control module is used for the control signal according to register and communication module, and output zero line has
Respective value, the respective value of zero line reactive power, the respective value of live wire active power, the respective value of live wire reactive power of work(power
Corresponding pulse signal, so that MCU calculates power consumption according to number of pulses；Interruption/Super-zero control module is used for according to register
Control signal with communication module makes MCU please according to the interruption of input to MCU output interrupt requests and voltage zero-cross pulse signal
Ask whether the interrupt event for judging to enable occurs, the disposal of some events is carried out according to the voltage zero-cross pulse signal of input.
The side of implementing of analog-to-digital conversion sample circuit and first, second, third electric parameter metering circuit in the present embodiment
Formula illustrates that here is omitted referring to the embodiment of above-mentioned each circuit.
One of ordinary skill in the art will appreciate that：Although the present invention is completed by hardware circuit, realize above-mentioned each
The all or part of step of embodiment of the method can also control related hardware to complete by programmed instruction.Foregoing program can
To be stored in a computer read/write memory medium.Upon execution, execution includes the step of above-mentioned each method embodiment to the program
Suddenly；And foregoing storage medium includes：ROM, RAM, magnetic disc or CD etc. are various can be with the medium of store program codes.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；With
The description of upper each electric parameter metering circuit is only the explanation and improvement carried out to measuring circuit representative in computation chip,
It will be appreciated by those skilled in the art that be that the method for the present invention can be used for all having similar structure to above-mentioned measuring circuit
Circuit in solve identical the problem of, although the present invention is described in detail with reference to foregoing embodiments, this area
Those of ordinary skill should be understood：It can still modify to the technical scheme described in foregoing embodiments, or
Equivalent substitution is carried out to which part or all technical characteristic；And these modifications or replacement, do not make appropriate technical solution
Essence depart from various embodiments of the present invention technical scheme scope.
Claims (6)
1. a kind of analog-to-digital conversion sample circuit, it is characterised in that including：Modulator, digital filtering and extracting unit, phasing
Circuit；The phase-correcting circuit include the first delay unit and the second delay unit, first delay unit respectively with institute
State the input connection of output end, the digital filtering and the extracting unit of modulator, second delay unit and the number
Word is filtered and the output end of extracting unit is connected；
Wherein, first delay unit includes M time-delay trigger, and second delay unit includes K time-delay trigger,
M=(X-1) * L, X are the down-sampled multiple of the digital filtering and extracting unit, and L is the data signal that the modulator is exported
Digit, K=Y*N, N is the digit for the data signal that the digital filtering and extracting unit are exported, during Y is N position digital signals
Bits per inch word signal distinguish corresponding time-delay trigger number, M, K, X, N, L, Y is positive integer.
2. analog-to-digital conversion sample circuit according to claim 1, it is characterised in that L=1.
3. a kind of computation chip, it is characterised in that including：Three analog-to-digital conversion sample circuits, turn with three moduluses respectively
Change the first electric parameter metering circuit of sample circuit connection；
Three analog-to-digital conversion sample circuits, for voltage signal respectively to input, live wire current signal, neutral line current letter
Number sampled, and will sample obtained voltage signal, live wire current signal, neutral line current signal are respectively outputted to voltage output
End, live wire current output terminal, neutral line current output end；
The first electric parameter metering circuit, for according to the obtained voltage signal of sampling, live wire current signal, zero line electricity
Stream signal is calculated, and obtains respective value, voltage and the zero line electricity of the phase angle of respective value, voltage and the live wire electric current of electric voltage frequency
The respective value of the phase angle of stream；
Wherein, three analog-to-digital conversion sample circuits are the analog-to-digital conversion sampling electricity as described in any in claim 1~2
Road.
4. computation chip according to claim 3, it is characterised in that the first electric parameter metering circuit includes：First
Low pass filter, the second low pass filter, the 3rd low pass filter, the first zero-crossing pulse generator, the second zero-crossing pulse are produced
Device, the 3rd zero-crossing pulse generator, electric voltage frequency counter, the first phase angle counter, the second phase angle counter；
The input of first low pass filter connects the voltage output end, and the output end of first low pass filter connects
The input of the first zero-crossing pulse generator is connect, the output end of the first zero-crossing pulse generator connects the voltage frequency
The input of rate counter, the first input end of the first phase angle counter, the first input end of the second phase angle counter, the electricity
Pressing the output end of frequency counter is used for the respective value of output voltage frequency；
The input of second low pass filter connects the live wire current output terminal, the output of second low pass filter
The input of end connection the second zero-crossing pulse generator, the output end connection of the second zero-crossing pulse generator described the
Second input of one phase angle counter, the output end of the first phase angle counter is used for output voltage and live wire current phase angle
Respective value；
The input of 3rd low pass filter connects the neutral line current output end, the output of the 3rd low pass filter
The input of end connection the 3rd zero-crossing pulse generator, the output end connection of the 3rd zero-crossing pulse generator described the
Second input of two-phase angle counter, the output end of the second phase angle counter is used for output voltage and neutral line current phase angle
Respective value.
5. computation chip according to claim 3, it is characterised in that also include：Adopted respectively with three analog-to-digital conversions
Second electric parameter metering circuit of sample circuit connection；
The second electric parameter metering circuit includes：First counter, 90-degree phase shifter, the first data selector, the second data
Selector, the 3rd data selector, the 4th data selector, the first multiplier, the 4th low pass filter, first adder,
Paired multiplier, the first decoder；
First input end, the 3rd input of first data selector are all connected with the live wire current output terminal, described
The second input, the 4th input of one data selector are all connected with the neutral line current output end, the first data selection
The output end of device is connected to the first input end of first multiplier；
First input end, the second input of second data selector are all connected with the voltage output end, second number
The output end of the 90-degree phase shifter is all connected with according to the 3rd input, the 4th input of selector, the 90-degree phase shifter
Input connects the voltage output end, and the output end of second data selector is connected to the second of first multiplier
Input；
The output end of first multiplier connects the input of the 4th low pass filter, the 4th low pass filter
Output end connects the first input end of the first adder；
The first input end connection live wire active power compensation control end of 3rd data selector, the 3rd data selection
The second input connection zero line active power compensation control end of device, the 3rd input connection fire of the 3rd data selector
Line reactive power compensation control end, the 4th input connection zero line reactive power compensation control of the 3rd data selector
End, the output end of the 3rd data selector is connected to the second input of the first adder；
The output end of the first adder connects the first input end of second multiplier；
The first input end connection live wire active power gain control end of 4th data selector, the 4th data choosing
Select the second input section connection zero line active power gain control end of device, the 3rd input connection of the 4th data selector
Live wire reactive power gain control end, the 4th input connection zero line reactive power gain control of the 4th data selector
End, the output end of the 4th data selector is connected to the second input of second multiplier；
The input of first decoder connects the output end of second multiplier；
First data selector, the second data selector, the 3rd data selector, the 4th data selector, the first decoding
Output end of the control end of device with first counter is connected, the first output end of first decoder, the second output
End, the 3rd output end, the 4th output end are used for respective value, the correspondence of zero line active power for exporting live wire active power successively
Value, the respective value of live wire reactive power, the respective value of zero line reactive power.
6. computation chip according to claim 5, it is characterised in that also include：Adopted respectively with three analog-to-digital conversions
3rd electric parameter metering circuit of sample circuit connection；
The 3rd electric parameter metering circuit includes：Second counter, the 5th data selector, the 6th data selector, the 7th
Data selector, the 3rd multiplier, the 5th low pass filter, square root calculation device, second adder, the 4th multiplier, second
Decoder；
The first input end connection live wire current output terminal of 5th data selector, the second of the 5th data selector
Input connects neutral line current output end, the 3rd input connection voltage output end of the 5th data selector, described the
The output end of five data selectors connects two inputs of first multiplier；
The output end of 3rd multiplier connects the input of the 5th low pass filter；5th low pass filter
Output end connects the square root calculation device input；
The square root calculation device output end connects the first input end of the second adder；
The first input end connection live wire current effective value compensation control end of 6th data selector, the 6th data choosing
The second input connection neutral line current virtual value compensation control end of device is selected, the 3rd input of the 6th data selector connects
Voltage effective value compensation control end is connect, the output end of the 6th data selector connects the second input of the adder；
The output end of the second adder connects the first input end of the 4th multiplier；
The first input end connection live wire current effective value gain control end of 7th data selector, the 7th data choosing
The second input connection neutral line current rms gain control end of device is selected, the 3rd input of the 7th data selector connects
Voltage effective value gain control end is connect, the output end of the 7th data selector connects the second input of four multiplier
End；
The output end of 4th multiplier connects the input of second decoder；
5th data selector, the 6th data selector, the 7th data selector, the second decoder control end and institute
The output end connection of the second counter is stated, the first output end of second decoder, the second output end, the 3rd output end are successively
Respective value, the respective value of neutral line current virtual value, the respective value of voltage effective value for exporting live wire current effective value.
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| CN108566204A (en) * | 2018-04-19 | 2018-09-21 | 南通大学 | A kind of adaptive power frequency type double integration A/D converter of integration period for accurate fields of measurement |
| CN109406873B (en) * | 2018-12-11 | 2024-11-08 | 上海贝岭股份有限公司 | Energy metering chips and smart meters |
| CN112286846B (en) * | 2019-07-25 | 2023-05-12 | 珠海格力电器股份有限公司 | Method and equipment for processing interrupt event |
| CN114744603B (en) * | 2021-10-22 | 2025-04-04 | 固赢科技(深圳)有限公司 | Power supply protection method and electronic equipment based on high-speed signal processing |
| CN114325085B (en) * | 2021-12-30 | 2024-07-05 | 江苏林洋能源股份有限公司 | Electric energy meter and method supporting dynamic energy consumption management |
| CN114415099B (en) * | 2022-01-15 | 2024-12-31 | 孟耕 | Phase correction circuit and electric energy meter based on analog-to-digital conversion delay |
| CN119087031B (en) * | 2024-11-06 | 2025-01-28 | 传申弘安智能(深圳)有限公司 | A conversion circuit applied to a gateway electric energy meter and a gateway electric energy meter |
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