CN104425273A - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device, comprising the following steps: firstly, a gate structure is formed on a substrate; then, substrate regions on both sides of the gate structure are etched to form recessed regions, and Perform ion implantation on the surface of the recessed area to make the surface of the recessed area amorphous; redeposit the stress layer; then perform annealing to recrystallize the surface of the amorphized recessed area to generate stress, which is the same as the stress The stresses of the layers are superimposed and transferred to the channel region and retained therein; finally the stress layer is removed, and a source and a drain are respectively formed in the recessed regions on both sides of the gate structure. In the present invention, an amorphous region is obtained by performing ion implantation in the channel region and its surrounding substrate, and a stress layer is deposited, so that the stress generated by the recrystallization of the amorphous region during the annealing process and the stress of the stress layer itself are used to form Compressive strain or tensile strain channels greatly enhance the mobility in the channel region.

Description

Manufacturing method of semiconductor device

technical field

The field of semiconductor manufacturing of the present invention relates to a manufacturing method of a semiconductor device.

Background technique

In semiconductor devices, especially MOS transistors, one of the main ways to increase the switching frequency of field effect transistors is to increase the driving current, and the main way to increase the driving current is to increase the carrier mobility. An existing technology for improving the carrier mobility of field effect transistors is stress memory technology (StressMemorization Technique, referred to as SMT), which increases the carrier mobility in the channel by forming stable stress in the channel region of the field effect transistor. Generally, tensile stress can make the molecular arrangement in the channel region more loose, thereby improving the mobility of electrons, which is suitable for NMOS transistors; while compressive stress can make the molecular arrangement in the channel region more compact, which helps to improve the migration of holes. rate, suitable for PMOS transistors.

From the perspective of the optimal introduction direction of the strain induced by the uniaxial process, for NMOS devices, the introduction of tensile strain along the direction of the channel and the introduction of compressive strain in the direction perpendicular to the channel are the most effective for improving the mobility of electrons in the channel. ; On the other hand, for PMOS devices, it is most effective to introduce compressive strain along the channel direction to improve the mobility of holes in the channel. According to this theory, many methods have been developed, one of which is to generate "global strain", that is, to apply stress from the substrate to the overall transistor device area. The global strain is generated by using structures such as ordinary silicon SiGe, SiC and other materials with different lattice constants are epitaxially grown on the substrate through a buffer layer, and a low-defect single-crystal silicon layer is grown on it to realize the formation of a globally strained silicon layer; or the method of making silicon-on-insulator is used to realize an insulator silicon germanium, strained silicon structure. Another method is to generate "local strain", that is, use the local structure or process method adjacent to the device channel to generate corresponding stress to act on the channel region to generate strain. Local strain is usually generated by, for example, the following structure: Stressed shallow trench isolation structures, (double) stressed liners, SiGe (e-SiGe) structures embedded in source/drain (S/D) regions of PMOS, in source/drain (S/D) regions of PMOS Embedded Σ-shaped SiGe structures, embedded SiC (e-SiC) structures in source/drain (S/D) regions of NMOS, etc. Among them, embedded silicon germanium (SiGe) technology (eSiGe technology) has become one of the main technologies of PMOS stress engineering because it can apply appropriate compressive stress to the channel region to improve the mobility of holes. At present, there are two silicon-germanium stress introduction technologies, one is to form a silicon-germanium stress layer in the source/drain region of the PMOS transistor, and the other is to form a silicon-germanium stress layer in the channel region directly under the gate structure .

However, some of the above-mentioned methods of generating channel local strain and changing the type of channel stress require complex processes, some are easy to introduce defects into the channel, and some have narrow application range; on the other hand, with the increase of device feature size As the size continues to shrink, the induced strain effect brought by the above methods is also constantly weakening.

Therefore, it is necessary to provide a manufacturing method of a semiconductor device to further improve channel mobility.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for manufacturing a semiconductor device, which is used to solve the problem of low channel mobility of the MOS device in the prior art.

To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device at least includes the following steps:

S1: providing a substrate on which a gate structure is formed; a channel region is provided in the substrate directly below the gate structure;

S2: Etching the substrate regions on both sides of the gate structure to form a recessed region, and performing ion implantation on the surface of the recessed region to make the surface of the recessed region amorphous;

S3: Deposit a stress layer, the stress layer covers the surface of the recessed region and the surface of the gate structure; then annealing is performed to recrystallize the surface of the amorphized recessed region to generate a first stress, the first The stress is superimposed on the second stress generated by the stress layer and transmitted to the channel region and retained in the channel region;

S4: removing the stress layer, and respectively forming a source and a drain in the recessed regions on both sides of the gate structure.

Optionally, in the step S2, at least one of Ge element, Sn element or C element is used for ion implantation.

Optionally, in the step S2, the energy range of ion implantation is 0.5-50 KeV, the ion implantation dose range is 5E13-5E15 atoms/cm ² , and the ion implantation angle range is 15-45°.

Optionally, in the step S3, the stress layer is a tensile stress layer or a compressive stress layer.

Optionally, the material of the stress layer includes TaC or SiN.

Optionally, the step S1 also includes a step of lightly doping the substrate in the regions on both sides of the gate structure, and the lightly doping uses one of arsenic, phosphorus, boron or indium elements or more.

Optionally, the substrate is an SOI substrate, which includes a buried oxide layer, and the bottom of the recessed region is higher than the bottom of the buried oxide layer.

Optionally, the substrate is an SOI substrate, which includes a buried oxide layer, and the bottom of the recessed region is lower than or flush with the bottom of the buried oxide layer.

Optionally, the source and drain materials include at least one of Si, Si _{1-x Gex} , Si _1-y C _y or Si _1-ab Ge _a C _b , wherein x ranges from is 0.1~0.5, the value range of y is 0.01~0.1, the value range of a is 0.1~0.35, and the value range of b is 0.01~0.05.

Optionally, the source and drain are formed by epitaxy or ultra-high vacuum chemical vapor deposition.

Optionally, the depth of the recessed region is 30-100 nm.

Optionally, in the step S3, the range of the annealing temperature is 950-1200° C., and the time range is 40 ms-30 s.

As mentioned above, the manufacturing method of the semiconductor device of the present invention has the following beneficial effects: an amorphous region is obtained by performing ion implantation in the channel region and its surrounding substrate, and then a stress layer is deposited and annealed. During the annealing process, The recrystallization of the amorphous region will generate stress in the channel region. In addition, the stress of the stress layer itself is further transmitted to the channel region and retained. The superposition of the two makes the stress of the channel region greatly enhanced. By changing the type of ion implantation and the dose and energy of implantation, the stress generated can be made to be compressive stress or tensile stress, which is suitable for PMOS and NMOS respectively, thereby improving channel mobility, and the manufacturing method of the semiconductor device of the present invention is suitable for 22nm and below node technology.

Description of drawings

FIG. 1 shows a process flow diagram of the manufacturing method of the semiconductor device of the present invention.

2 is a schematic cross-sectional view of the semiconductor device manufacturing method of the present invention after the gate structure is formed on the Si substrate in Embodiment 1. FIG.

FIG. 3 is a schematic cross-sectional view of the semiconductor device manufacturing method of the present invention after lightly doping the substrate in the regions on both sides of the gate structure in Embodiment 1. FIG.

FIG. 4 is a schematic diagram of a cross-sectional structure after forming a recessed region in the first embodiment of the manufacturing method of the semiconductor device of the present invention.

FIG. 5 is a schematic diagram of a cross-sectional structure of the semiconductor device manufacturing method of the present invention when performing ion implantation in Embodiment 1. FIG.

FIG. 6 is a schematic diagram of a cross-sectional structure after depositing a stress layer in Embodiment 1 of the manufacturing method of the semiconductor device of the present invention.

FIG. 7 is a schematic diagram of a cross-sectional structure of the semiconductor device manufacturing method of the present invention after the stress layer is removed in the first embodiment.

FIG. 8 is a schematic diagram of the cross-sectional structure of the manufacturing method of the semiconductor device of the present invention after forming the source and the drain in the first embodiment.

FIG. 9 is a schematic cross-sectional structure diagram after forming a gate structure on an SOI substrate in Embodiment 3 of the method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a schematic cross-sectional structure diagram of the semiconductor device manufacturing method of the present invention when ion implantation is performed in the third embodiment.

FIG. 11 is a schematic diagram of a cross-sectional structure after depositing a stress layer in Embodiment 3 of the method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a schematic cross-sectional view of the semiconductor device manufacturing method of the present invention after the stress layer is removed and the source and drain are formed in the third embodiment.

FIG. 13 is a schematic cross-sectional view of the semiconductor device manufacturing method of the present invention after the recessed region is formed in the fourth embodiment.

FIG. 14 is a schematic cross-sectional structure diagram of the semiconductor device manufacturing method of the present invention when performing ion implantation in Embodiment 4. FIG.

FIG. 15 is a schematic diagram of a cross-sectional structure after depositing a stress layer in Embodiment 4 of the method for manufacturing a semiconductor device of the present invention.

FIG. 16 is a schematic cross-sectional structure diagram of the semiconductor device manufacturing method of the present invention after the source and drain are formed in the fourth embodiment.

Component designation description

S1～S4 steps

1 Si substrate

2 gate dielectric layer

3 grid

4 side walls

5 protective layers

6 lightly doped region

7 Etched area

8 stress layer

9 strain channel

10 source

11 drain

12 Backing substrate

13 buried oxide layer

14 top silicon

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 16. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

Please refer to Fig. 1, it is shown as the process flow diagram of the manufacturing method of the semiconductor device of the present invention, the manufacturing method of the semiconductor device at least includes the following steps:

Step S1 , please refer to FIG. 1 , providing a substrate on which a gate structure is formed; a channel region is provided in the substrate directly below the gate structure.

Specifically, the substrate may be any known semiconductor substrate, including but not limited to Si, Ge, SiGe and the like. In this embodiment, a Si substrate is taken as an example for description. Please refer to FIG. 2, as shown in the figure, a gate structure is formed on a Si substrate 1, the gate structure includes a gate dielectric layer 2 and a gate 3 formed thereon, the gate dielectric layer 2 and the gate Side walls 4 are formed on both sides of the gate 3, and a protective layer 5 is formed on the gate 3. The function of the protection layer 5 is to prevent the edge of the gate 3 from being damaged during the subsequent ion implantation process. A channel region is provided in the substrate right below the gate structure. In this embodiment, a PMOS structure will be finally formed, so before forming the gate structure, an N-well implantation can be performed on the Si substrate 1, and the gate 3 is N-type.

Specifically, after forming the gate structure, light doping can also be carried out in the substrate in the regions on both sides of the gate structure, the light doping adopts one or more of boron or indium elements, lightly doped The elements will diffuse into the substrate below the spacer 4, reducing the contact resistance between the subsequently formed source and drain and the channel. Please refer to FIG. 3 , which is a schematic diagram of a cross-sectional structure after light doping, in which a lightly doped region 6 is shown.

Step S2, etching the substrate regions on both sides of the gate structure to form a recessed region, and performing ion implantation on the surface of the recessed region to make the surface of the recessed region amorphized.

Please refer to FIG. 4 , which is a schematic diagram of a cross-sectional structure after forming the etched region 7 . Wherein, the substrate between the two sidewalls inside the left and right recessed regions is defined as a channel region, which is located directly below the gate region. Specifically, the depth range of the recessed area is 30-100 nm. After the recessed region 7 is formed, ion implantation is performed on the surface of the recessed region, please refer to FIG. 5 , which is a schematic diagram of ion implantation. Specifically, at least one of Ge element, Sn element or C element is used for ion implantation. The energy range of ion implantation is 0.5-50KeV, the ion implantation dose range is 5E13-5E15 atoms/cm ² , and the ion implantation angle range is 15-50KeV. 45°, where the angle here refers to the angle between the ion implantation direction and the vertical direction. Preferably, the energy range of ion implantation of Ge element and Sn element is 10-50 KeV, and the ion implantation dose range is 5E14-5E15 atoms/cm ² ; the energy range of C element ion implantation is 0.5-5 KeV, and the implantation dose range is 5E13- 1E15 atoms/cm ² .

The purpose of ion implantation is to amorphize the surface of the recessed region, that is, to amorphize the surface of the channel region and the surrounding substrate surface. It should be pointed out that by adjusting the ion implantation dose and ion implantation energy, the implanted ions can be distributed at different depths in the channel region, and the degree of amorphization will also be different, that is, the implanted elements can be distributed at both ends of the channel region or distributed throughout the channel region. In addition, the length of the channel region will also have an impact. For a shorter channel, the implanted elements are more likely to be distributed in the entire channel region, while for a longer channel, the implanted elements are more likely to be distributed in the channel. The ends of the region and none in the middle. For the same implanted elements, the two distribution structures (distributed at both ends of the channel region or distributed in the entire channel region) have different effects in the subsequent annealing and recrystallization process. Since the PMOS structure is to be formed in this embodiment, it is necessary to introduce compressive stress in the channel region, preferably using heavier elements such as Ge or Sn, and make the implanted elements distributed at both ends of the channel region, so that the channel region Both ends will form compressive stress on the non-implanted region in the middle of the channel region.

Step S3, depositing a stress layer, the stress layer covering the surface of the recessed region and the surface of the gate structure; then performing annealing to recrystallize the surface of the amorphized recessed region to generate a first stress, the second A stress is superimposed on the second stress generated by the stress layer and transmitted to the channel region and remains in the channel region.

Please refer to FIG. 6 , which is a schematic diagram of a cross-sectional structure after depositing the stress layer 8 . During the annealing process, the surface of the amorphized etched region recrystallizes. As mentioned above, in this embodiment, heavier elements such as Ge or Sn are preferably used for ion implantation, and the implanted elements are distributed at both ends of the channel region. Partial implantation at both ends has a strong lattice mismatch compressive stress on the center of the channel. During the annealing process, the ion-implanted region recrystallizes, and the two ends of the channel region form compressive stress on the middle region of the channel. In this embodiment, the stress layer is preferably a compressive stress layer, which can further enhance the extrusion effect on the channel, that is, the inward compressive stress. The compressive stress of the stress layer itself and the stress formed by the recrystallization of the amorphous region are superimposed and transmitted to the channel region and retained therein, forming a strained channel.

Specifically, the material of the stress layer includes but not limited to TaC or SiN. It should be pointed out that for the same stress layer material, its composition may be a compressive stress layer or a tensile stress layer. For TaC, by adjusting the ratio of C, a compressive stress TaC layer or a tensile stress TaC layer can be obtained. For For SiN, by adjusting the proportion of N, a compressive stress SiN layer or a tensile stress SiN layer can be obtained.

Specifically, the range of the annealing temperature is 950-1200° C., and the time range is 40 ms-30 s.

In step S4, the stress layer is removed, and a source and a drain are respectively formed in the recessed regions on both sides of the gate structure.

Please refer to FIG. 7 , which is a schematic diagram of a cross-sectional structure after removing the stress layer. It can be seen from the figure that the channel region directly below the gate region has become a strained channel 9 . In this embodiment, the strained channel 9 has compressive stress in the channel direction, which can greatly improve the mobility of hole carriers.

After the stress-reducing layer 8 is removed, a source 10 and a drain 11 are respectively formed in the recessed regions on both sides of the gate structure. Please refer to FIG. 8 , which is a schematic diagram of the cross-sectional structure after forming the source and drain. Specifically, the material of the source electrode 10 and the drain electrode 11 includes at least one of Si, Si _{1-x Gex} , Si _1-y C _y or Si _1-ab Ge _a C _b , wherein the value of x is The range is 0.1-0.5, the value range of y is 0.01-0.1, the value range of a is 0.1-0.35, and the value range of b is 0.01-0.05. The source 10 and the drain 11 are formed by epitaxy or ultra-high vacuum chemical vapor deposition. The source 10 and the drain 11 are P-type.

In another embodiment, light elements such as C can also be used for ion implantation, and the implanted C elements can be distributed at both ends of the channel region or the entire channel region. The contribution is much smaller, and the implantation of C element makes the channel region loose, so the source and drain materials can be selected as Si or Si _{1-x Gex} , which can also form compressive stress in the channel region.

So far, a PMOS structure with a compressively strained channel has been formed by the method for manufacturing a semiconductor device of the present invention.

As mentioned above, the manufacturing method of the semiconductor device of the present invention has the following beneficial effects: an amorphous region is obtained by performing ion implantation in the channel region and its surrounding substrate, and then a stress layer is deposited and annealed. During the annealing process, The recrystallization of the amorphous region will generate compressive stress in the channel region. In addition, the compressive stress of the stress layer itself is further transmitted to the channel region and retained. The superposition of the two makes the compressive stress of the channel region greatly enhanced. , thereby improving the channel mobility of the PMOS structure.

Embodiment two

This embodiment adopts basically the same scheme as that of the first embodiment, except that the PMOS structure is prepared in the first embodiment, while the NMOS structure is prepared in this embodiment.

The manufacturing method of the semiconductor device of the present invention at least includes the following steps:

First, a substrate is provided, and a gate structure is formed on the substrate; the gate structure includes a gate dielectric layer, a gate formed on the gate dielectric layer, a gate formed on the gate dielectric layer and the gate dielectric layer. Sidewalls on both sides of the gate and a protection layer formed on the gate; a channel region is provided in the substrate directly below the gate structure. In this embodiment, an NMOS structure will be finally formed, so before forming the gate structure, a P-well implantation can be performed on the substrate, and the gate is P-type.

Specifically, after the gate structure is formed, light doping can be performed on the substrate in the regions on both sides of the gate structure, and the light doping uses one or more of arsenic or phosphorus elements. Lightly doped elements will diffuse into the substrate below the sidewalls, reducing the contact resistance between the subsequently formed source and drain and the channel.

Second, etching the substrate regions on both sides of the gate structure to form a recessed region, and performing ion implantation on the surface of the recessed region to make the surface of the recessed region amorphous.

Specifically, at least one of Ge element, Sn element or C element is used for ion implantation. The energy range of ion implantation is 0.5-50KeV, the ion implantation dose range is 5E13-5E15 atoms/cm ² , and the ion implantation angle range is 15-50KeV. 45°, where the angle here refers to the angle between the ion implantation direction and the vertical direction. Preferably, the energy range of ion implantation of Ge element and Sn element is 10-50 KeV, and the ion implantation dose range is 5E14-5E15 atoms/cm ² ; the energy range of C element ion implantation is 0.5-5 KeV, and the implantation dose range is 5E13- 1E15 atoms/cm ² . The purpose of ion implantation is to amorphize the surface of the recessed region, that is, to amorphize the surface of the channel region and the surrounding substrate surface. It should be pointed out that by adjusting the ion implantation dose and ion implantation energy, the implanted ions can be distributed at different depths in the channel region, and the degree of amorphization will also be different, that is, the implanted elements can be distributed at both ends of the channel region or distributed throughout the channel region. In addition, the length of the channel region will also have an impact. For a shorter channel, the implanted elements are more likely to be distributed in the entire channel region, while for a longer channel, the implanted elements are more likely to be distributed in the channel. The ends of the region and none in the middle. For the same implanted element, the two distribution structures (distributed at both ends of the channel region or distributed in the entire channel region) have different effects in the subsequent annealing and recrystallization process. Since an NMOS structure is to be formed in this embodiment, tensile stress needs to be introduced into the channel region, preferably using heavier elements such as Ge or Sn, and the implanted elements are distributed throughout the channel region, so that the channel region will There is a tendency to expand outward.

Again, a stress layer is deposited, and the stress layer covers the surface of the recessed region and the surface of the gate structure; then annealing is performed to recrystallize the surface of the amorphized recessed region to generate a first stress, the first stress The second stress generated by the stress layer is superimposed and transferred to the channel region and retained in the channel region.

During the annealing process, the surface of the amorphized etched region recrystallizes. As mentioned above, in this embodiment, it is preferable to use heavier elements such as Ge or Sn, and to distribute the implanted elements in the entire channel region, so that the entire channel region is amorphized. During the annealing process, the entire channel region is regenerated. Crystallization, because for the entire distribution of high-energy and high-angle Ge and Sn implantation, it will occur in the implantation overlap area in the center of the channel, which has a strong external expansion tendency and forms tensile stress in the channel region. In this embodiment, the stress layer is preferably a tensile stress layer, which can strengthen the above-mentioned tensile stress. The tensile stress of the stress layer itself is superimposed on the tensile stress formed by the recrystallization of the amorphous region and is transmitted to the channel region and retained. In it, a tensile strained channel is formed. In this embodiment, the strained channel has tensile stress in the channel direction, which can greatly improve the mobility of electron carriers.

Specifically, the material of the stress layer includes but not limited to TaC or SiN. It should be pointed out that for the same stress layer material, its composition may be a compressive stress layer or a tensile stress layer. For TaC, by adjusting the ratio of C, a compressive stress TaC layer or a tensile stress TaC layer can be obtained. For For SiN, by adjusting the proportion of N, a compressive stress SiN layer or a tensile stress SiN layer can be obtained.

Finally, the stress layer is removed, and a source and a drain are respectively formed in the recessed regions on both sides of the gate structure.

Specifically, the material of the source and drain includes at least one of Si, Si _{1-x Gex} , Si _1-y C _y or Si _1-ab Ge _a C _b , wherein the value range of x is 0.1~0.5, the value range of y is 0.01~0.1, the value range of a is 0.1~0.35, and the value range of b is 0.01~0.05. The source and drain are formed by epitaxy or ultra-high vacuum chemical vapor deposition. The source and drain are N-type.

In another embodiment, light elements such as C can also be used for ion implantation, and the implanted C element is preferably distributed at both ends of the channel region, so that the non-implanted region in the middle of the channel region will form an outward gap between the implanted regions at both ends. The pushing force, that is, the formation of tensile stress in the channel region, and the subsequently deposited stress layer is preferably a tensile stress layer, which can strengthen the tensile stress. The material of the source and drain electrodes is preferably Si _1-y Cy _y , so as to form tensile stress in the channel region.

So far, an NMOS structure with a tensile strain channel has been formed through the manufacturing method of the semiconductor device of the present invention.

As mentioned above, the manufacturing method of the semiconductor device of the present invention has the following beneficial effects: an amorphous region is obtained by performing ion implantation in the channel region and its surrounding substrate, and then a stress layer is deposited and annealed. During the annealing process, The recrystallization of the amorphous region will generate tensile stress in the channel region during this process. In addition, the tensile stress of the stress layer itself is further transmitted to the channel region and retained. The superposition of the two makes the tensile stress of the channel region greatly enhanced. , thereby improving the channel mobility of the NMOS structure.

Embodiment Three

This embodiment adopts basically the same solution as that of Embodiment 1 or Embodiment 2, except that in this embodiment, the substrate is an SOI substrate.

Referring to FIGS. 9 to 12, the manufacturing method of the semiconductor device of the present invention at least includes the following steps:

First, referring to FIG. 9 , an SOI substrate including a back substrate 12, a buried oxide layer 13 and a top layer of silicon 14 is provided from bottom to top, and a gate structure is formed on the SOI substrate; the gate structure Including a gate dielectric layer 2, a gate 3 formed on the gate dielectric layer, sidewalls 4 formed on both sides of the gate dielectric layer and the gate, and a protective layer 5 formed on the gate; A channel region is provided in the substrate right below the gate structure.

Specifically, after forming the gate structure, light doping can also be performed on the substrate in the regions on both sides of the gate structure. For NMOS, the light doping uses one or more of arsenic and phosphorus elements, For PMOS, one or more of boron and indium elements are used for the light doping, and the lightly doped elements will diffuse into the top layer of silicon below the sidewall 4, reducing the subsequent formation of source and drain electrodes and Contact resistance between channels.

Secondly, the substrate regions on both sides of the gate structure are etched to form recessed regions. Specifically, the bottom of the etched region is higher than the bottom of the buried oxide layer. In this embodiment, the bottom of the recessed region reaches the top of the buried oxide layer 13 . Wherein, the top layer of silicon between the two sidewalls inside the left and right recessed regions is defined as a channel region, which is located directly below the gate region.

After the recessed region 7 is formed, ion implantation is performed on the surface of the recessed region to make the surface of the recessed region amorphous. Please refer to FIG. 10 , which is a schematic diagram of a cross-sectional structure during ion implantation, and the lightly doped region 6 is shown in the figure. Specifically, at least one of Ge element, Sn element or C element is used for ion implantation. The energy range of ion implantation is 0.5-50KeV, the ion implantation dose range is 5E13-5E15 atoms/cm ² , and the ion implantation angle range is 15-50KeV. 45°. Preferably, the energy range of ion implantation of Ge element and Sn element is 10-50 KeV, and the ion implantation dose range is 5E14-5E15 atoms/cm ² ; the energy range of C element ion implantation is 0.5-5 KeV, and the implantation dose range is 5E13- 1E15 atoms/cm ² .

The purpose of the ion implantation is to make the surface of the recessed region amorphized. In this embodiment, the ion implantation makes the surface of the channel region amorphized. It should be pointed out that by adjusting the ion implantation dose and ion implantation energy, the implanted ions can be distributed at different depths in the channel region, and the degree of amorphization will also be different, that is, the implanted elements can be distributed at both ends of the channel region or distributed throughout the channel region. In addition, the length of the channel region will also have an impact. For a shorter channel, the implanted elements are more likely to be distributed in the entire channel region, while for a longer channel, the implanted elements are more likely to be distributed in the channel. The ends of the region and none in the middle. For the same implanted elements, the two distribution structures (distributed at both ends of the channel region or distributed in the entire channel region) have different effects in the subsequent annealing and recrystallization process.

Again, referring to FIG. 11, a stress layer 8 is deposited, and the stress layer covers the surface of the recessed region and the surface of the gate structure; then annealing is performed to recrystallize the surface of the amorphized recessed region to produce the first Stress, the first stress is superimposed on the second stress generated by the stress layer and transmitted to the channel region and retained in the channel region.

Specifically, the type of ion implantation, implantation dose and energy can be changed according to the type of device to be manufactured, such as PMOS or NMOS, so that the stress generated by recrystallization of the channel region during the annealing process is compressive stress or tensile stress. For the principle, please refer to the relevant descriptions in Embodiment 1 and Embodiment 2, and details will not be repeated here.

Specifically, the material of the stress layer includes but not limited to TaC or SiN. It should be pointed out that for the same stress layer material, its composition may be a compressive stress layer or a tensile stress layer. For TaC, by adjusting the ratio of C, a compressive stress TaC layer or a tensile stress TaC layer can be obtained. For For SiN, by adjusting the proportion of N, a compressive stress SiN layer or a tensile stress SiN layer can be obtained.

Finally, the stress layer is removed, and a source and a drain are respectively formed in the recessed regions on both sides of the gate structure.

Specifically, the source electrode 10 and the drain electrode 11 are formed by epitaxial method or ultra-high vacuum chemical vapor deposition method. For the epitaxial method, since the bottom of the recessed region reaches the buried oxide layer, the source and drain can only be formed by the lateral epitaxial method.

Please refer to FIG. 12 , which is a schematic diagram of a cross-sectional structure after removing the stress layer 8 and forming the source and drain. It can be seen from the figure that the channel region directly below the gate region has become a strained channel 9 . For the PMOS structure, the strained channel 9 has a compressive stress in the channel direction, which can greatly improve the mobility of hole carriers; for the NMOS structure, the strained channel 9 has a tensile stress in the channel direction, The mobility of electron carriers can be greatly improved.

As mentioned above, the manufacturing method of the semiconductor device of the present invention has the following beneficial effects: an amorphous region is obtained by performing ion implantation in the channel region and its surrounding substrate, and then a stress layer is deposited and annealed. During the annealing process, The recrystallization of the amorphous region will generate compressive stress or tensile stress in the channel region and remain in the channel region during this process. In addition, the compressive stress or tensile stress of the stress layer itself will be further transmitted to the channel region and retained. The superposition of the former makes the stress of the channel region greatly enhanced, thereby improving the channel mobility of the PMOS or NMOS structure.

Embodiment Four

This embodiment adopts basically the same scheme as Embodiment 3, the difference is that in Embodiment 2, the bottom of the etched region is higher than the bottom of the buried oxide layer in this embodiment, while in this embodiment, the etched region The bottom is lower than or flush with the bottom of the buried oxide layer.

Referring to FIGS. 13 to 16, the manufacturing method of the semiconductor device of the present invention at least includes the following steps:

First, referring to FIG. 13 , an SOI substrate including a back substrate 12, a buried oxide layer 13, and a top layer of silicon 14 is provided from bottom to top, and a gate structure is formed on the SOI substrate; the gate structure Including a gate dielectric layer 2, a gate 3 formed on the gate dielectric layer, sidewalls 4 formed on both sides of the gate dielectric layer and the gate, and a protective layer 5 formed on the gate; A channel region is provided in the substrate right below the gate structure; and then the substrate regions on both sides of the gate structure are etched to form a recessed etching region.

Specifically, the bottom of the etched region is higher than or flush with the bottom of the buried oxide layer. In this embodiment, the bottom of the recessed region reaches the back substrate 12 below the bottom of the buried oxide layer 13 . Wherein, the top layer of silicon between the two sidewalls inside the left and right recessed regions is defined as a channel region, which is located directly below the gate region.

Specifically, after forming the gate structure and before forming the recessed region, light doping can also be performed on the substrate in the regions on both sides of the gate structure. For NMOS, the light doping uses one of arsenic and phosphorus elements. For PMOS, one or more of boron and indium elements are used for the light doping, and the lightly doped elements will diffuse into the top-layer silicon below the sidewall 4, reducing the source of subsequent formation. The contact resistance between the electrode and the drain and the channel.

Secondly, after forming the etched area 7 , ion implantation is performed on the surface of the etched area to make the surface of the etched area amorphized. Please refer to FIG. 14 , which is a schematic diagram of a cross-sectional structure during ion implantation, in which a lightly doped region 6 is shown. Specifically, at least one of Ge element, Sn element or C element is used for ion implantation. The energy range of ion implantation is 0.5-50KeV, the ion implantation dose range is 5E13-5E15 atoms/cm ² , and the ion implantation angle range is 15-50KeV. 45°. Preferably, the energy range of ion implantation of Ge element and Sn element is 10-50 KeV, and the ion implantation dose range is 5E14-5E15 atoms/cm ² ; the energy range of C element ion implantation is 0.5-5 KeV, and the implantation dose range is 5E13- 1E15 atoms/cm ² .

The purpose of the ion implantation is to amorphize the surface of the recessed region. In this embodiment, the ion implantation amorphizes the surface of the channel region and the surface of the back substrate. It should be pointed out that by adjusting the ion implantation dose and ion implantation energy, the implanted ions can be distributed at different depths in the channel region, and the degree of amorphization will also be different, that is, the implanted elements can be distributed at both ends of the channel region or distributed throughout the channel region. In addition, the length of the channel region will also have an impact. For a shorter channel, the implanted elements are more likely to be distributed in the entire channel region, while for a longer channel, the implanted elements are more likely to be distributed in the channel. The ends of the region and none in the middle. For the same implanted elements, the two distribution structures (distributed at both ends of the channel region or distributed in the entire channel region) have different effects in the subsequent annealing and recrystallization process.

Again, referring to FIG. 15, a stress layer 8 is deposited, and the stress layer covers the surface of the recessed region and the surface of the gate structure; then annealing is performed to recrystallize the surface of the amorphized recessed region to produce the first Stress, the first stress is superimposed on the second stress generated by the stress layer and transmitted to the channel region and retained in the channel region.

Specifically, the type of ion implantation, implantation dose and energy can be changed according to the type of device to be manufactured, such as PMOS or NMOS, so that the stress generated by recrystallization of the channel region during the annealing process is compressive stress or tensile stress. For the principle, please refer to the relevant descriptions in Embodiment 1 and Embodiment 2, and details will not be repeated here.

Specifically, the material of the stress layer includes but not limited to TaC or SiN. It should be pointed out that for the same stress layer material, its composition may be a compressive stress layer or a tensile stress layer. For TaC, by adjusting the ratio of C, a compressive stress TaC layer or a tensile stress TaC layer can be obtained. For For SiN, by adjusting the proportion of N, a compressive stress SiN layer or a tensile stress SiN layer can be obtained.

Finally, the stress layer is removed, and a source and a drain are respectively formed in the recessed regions on both sides of the gate structure.

Please refer to FIG. 16 , which is a schematic diagram of a cross-sectional structure after removing the stress layer 8 . It can be seen from the figure that the channel region directly below the gate region has become a strained channel 9 . For the PMOS structure, the strained channel 9 has a compressive stress in the channel direction, which can greatly improve the mobility of hole carriers; for the NMOS structure, the strained channel 9 has a tensile stress in the channel direction, The mobility of electron carriers can be greatly improved.

In this embodiment, since the back substrate 12 is exposed, an amorphous region is also formed on its surface during the ion implantation process, and the recrystallization of this region during the annealing process will also generate stress and transmit it to the channel region. Compared with the embodiment Third, the stress in the channel region is stronger in this embodiment. In addition, the source 10 and the drain 11 are formed by epitaxy or ultra-high vacuum chemical vapor deposition. For the epitaxial method, since the bottom of the recessed region reaches the back substrate, the source and drain can be formed by both the lateral epitaxy and the vertical epitaxy, and there are fewer process restrictions.

As mentioned above, the manufacturing method of the semiconductor device of the present invention has the following beneficial effects: an amorphous region is obtained by performing ion implantation in the channel region and its surrounding substrate, and then a stress layer is deposited and annealed. During the annealing process, The recrystallization of the amorphous region will generate compressive stress or tensile stress in the channel region and remain in the channel region during this process. In addition, the compressive stress or tensile stress of the stress layer itself will be further transmitted to the channel region and retained. The superposition of the former makes the stress of the channel region greatly enhanced, thereby improving the channel mobility of the PMOS or NMOS structure.

To sum up, the method for manufacturing a semiconductor device of the present invention obtains an amorphous region by performing ion implantation in the channel region and its surrounding substrate, and deposits a stress layer, thereby taking advantage of the recrystallization of the amorphous region during the annealing process The generated stress and the stress of the stress layer itself form a compressive strain or tensile strain channel, which greatly improves the carrier mobility in the channel region, and the method of the present invention is applicable to 22nm and below node technologies. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (12)

1. a manufacture method for semiconductor device, is characterized in that, the manufacture method of described semiconductor device at least comprises the following steps:

S1 a: substrate is provided, forms grid structure over the substrate; Channel region is provided with in substrate immediately below described grid structure;

S2: the substrate region etching described grid structure both sides, forms etchback region, and carries out ion implantation in described etchback region surface, to make described etchback region surface decrystallized;

S3: deposition stressor layers, described stressor layers covers described etchback region surface and described grid structure surface; Then anneal, make decrystallized etchback region surface recrystallization to produce the first stress, described first stress and described stressor layers produce the second stress be stacked adduction and be passed to described channel region and be retained in described channel region;

S4: remove described stressor layers, and source electrode and drain electrode is formed respectively in the etchback region of described grid structure both sides.

2. the manufacture method of semiconductor device according to claim 1, is characterized in that: in described step S2, adopts at least one in Ge element, Sn element or C element to carry out ion implantation.

3. the manufacture method of semiconductor device according to claim 1, is characterized in that: in described step S2, and the energy range of ion implantation is 0.5 ~ 50KeV, and ion implantation dosage scope is 5E13 ~ 5E15atoms/cm ², ion implantation angle scope is 15 ~ 45 °.

4. the manufacture method of semiconductor device according to claim 1, is characterized in that: in described step S3, and described stressor layers is tension stress layer or compressive stress layer.

5. the manufacture method of semiconductor device according to claim 1, is characterized in that: the material of described stressor layers comprises TaC or SiN.

6. the manufacture method of semiconductor device according to claim 1, it is characterized in that: be also included in after described step S1 in the substrate of described grid structure two side areas and carry out lightly doped step, described light dope adopt in arsenic, phosphorus, boron or phosphide element one or more.

7. the manufacture method of semiconductor device according to claim 1, is characterized in that: described substrate is SOI substrate, and it comprises oxygen buried layer, and described etchback sections bottom is higher than bottom described oxygen buried layer.

8. the manufacture method of semiconductor device according to claim 1, is characterized in that: described substrate is SOI substrate, and it comprises oxygen buried layer, described etchback sections bottom lower than or flush bottom described oxygen buried layer.

9. the manufacture method of semiconductor device according to claim 1, is characterized in that: the material of described source electrode and drain electrode comprises Si, Si _1-xge _x, Si _1-yc _yor Si _1-a-bge _ac _bin at least one, wherein the span of the span of x to be the span of 0.1 ~ 0.5, y be 0.01 ~ 0.1, a is the span of 0.1 ~ 0.35, b is 0.01 ~ 0.05.

10. the manufacture method of semiconductor device according to claim 1, is characterized in that: described source electrode and drain electrode adopt epitaxy or ultra-high vacuum CVD method to be formed.

The manufacture method of 11. semiconductor device according to claim 1, is characterized in that: the depth bounds in described etchback region is 30 ~ 100nm.

The manufacture method of 12. semiconductor device according to claim 1, is characterized in that: in described step S3, and the scope of described annealing temperature is 950 ~ 1200 DEG C, and time range is 40ms ~ 30s.