CN104410411A - Intelligent phase locking device for long-distance synchronous communication clock - Google Patents
Intelligent phase locking device for long-distance synchronous communication clock Download PDFInfo
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- CN104410411A CN104410411A CN201410784174.1A CN201410784174A CN104410411A CN 104410411 A CN104410411 A CN 104410411A CN 201410784174 A CN201410784174 A CN 201410784174A CN 104410411 A CN104410411 A CN 104410411A
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- 230000005540 biological transmission Effects 0.000 abstract description 9
- 230000002452 interceptive effect Effects 0.000 abstract 1
- 230000033764 rhythmic process Effects 0.000 abstract 1
- 230000008054 signal transmission Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 2
- 230000008632 circadian clock Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Abstract
The invention discloses an intelligent phase locking device for a long-distance synchronous communication clock. The phase locking device comprises a signal receiving circuit, a communication clock and a frequency dividing circuit, wherein the signal receiving circuit is connected with a signal transmission line; the signal receiving circuit is connected with a master control CPU (Central Processing Unit) through a communication chip and further connected with a synchronizing signal analyzing and phase-locked control CPU; the communication clock and the frequency dividing circuit are respectively connected with the communication chip and the synchronizing signal analyzing and phase-locked control CPU; the synchronizing signal analyzing and phase-locked control CPU is connected with a differentiating circuit; the differentiating circuit is connected with the communication clock and the frequency dividing circuit. With the adoption of the structure, reasonable structural arrangement is achieved, information transmission is reliable, the transmission efficiency is high and the capacity of resisting disturbance is strong and is far more higher than a conventional pulse synchronization manner, and besides, an interfering signal can be easily judged and removed when encountering strong interference, even being subjected to a blanket interference for a long time, the micro-chip computer can also calculate the position of a next synchronous field FE according to own clock rhythm memory.
Description
Technical field
The present invention relates to a kind of underground mine use communicator, specifically a kind of remote synchronization communication clock intelligence phase-locking device.
Background technology
Conventional asynchronous serial communication mode, its structure is simple, equipment requirement is not strictly adopted in a large number, its shortcoming is poor anti jamming capability, superpose in signal and be easily mistakened as the starting impulse making information code after disturbing pulse, trigger the displacement of serial code receiver and cause error code, because each byte units must insert start bit, position of rest, parity check bit, space character etc., efficiency of transmission is declined greatly.Synchronous communication is with the transmission of whole field data bag, CRC redundancy check, efficiency of transmission high anti-jamming capacity is strong, but require that the communication clock of communication host and terminal must with frequency homophase, this is a difficult problem to telecommunication, is especially difficult to realize in the bus of general twisted-pair power cable, if adopt data pulse change along triggering synchronous, interference in signal can disturb synchronous stability, and phase place is once the whole field signal of step-out will whole error codes.
Summary of the invention
The technical problem to be solved in the present invention is to provide one can intellectual analysis synchronous point, makes phase-locked precisely reliable thus realize the remote synchronization communication clock intelligence phase-locking device of whole network intelligent synchronizationization transmission.
In order to solve the problems of the technologies described above, remote synchronization communication clock intelligence phase-locking device of the present invention, comprise the signal receiving circuit be connected with signal transmssion line, signal receiving circuit is connected with master cpu by communication chip, signal receiving circuit is also connected with phase-locked control CPU with a synchronizing signal analysis, synchronizing signal analysis and phase-locked control CPU can directly receive the data-signal carried from signal receiving circuit, also comprise a communication clock and frequency dividing circuit, described communication clock and frequency dividing circuit connect communication chip and synchronizing signal analysis and phase-locked control CPU respectively, described synchronizing signal analysis is connected differential circuit with phase-locked control CPU, and described differential circuit connects communication clock and frequency dividing circuit.
After adopting above-mentioned structure, owing to being equipped with phase-locked single-chip microcomputer in each station terminal, flutter the FE synchronization field of catching in downlink call code in real time, synchronous head elaborate position is isolated through Logic judgment, then the synchronous frequency divider of triggering terminal realizes the same frequency homophase of whole network communication clock, its vibrational power flow is reasonable, information transmission is reliable, efficiency of transmission high anti-jamming capacity is strong, its antijamming capability is far away higher than the impulsive synchronization mode of routine, can interference signal be judged easily and reject when meeting with strong jamming, even if suffer long period suppression jamming, single-chip microcomputer also can calculate the position of next synchronization field FE according to the memory of self circadian clock.
Accompanying drawing explanation
Fig. 1 is the theory diagram of remote synchronization communication clock of the present invention intelligence phase-locking device.
Embodiment
Below in conjunction with the drawings and specific embodiments, remote synchronization communication clock intelligence phase-locking device of the present invention is described in further detail.
As shown in the figure, remote synchronization communication clock intelligence phase-locking device of the present invention, comprise the signal receiving circuit be connected with signal transmssion line, described signal receiving circuit is connected with master cpu by communication chip, signal receiving circuit is also connected with phase-locked control CPU with a synchronizing signal analysis, synchronizing signal analysis and phase-locked control CPU can directly receive the data-signal carried from signal receiving circuit, also comprise a communication clock and frequency dividing circuit, described communication clock and frequency dividing circuit connect communication chip and synchronizing signal analysis and phase-locked control CPU respectively, communication clock and frequency dividing circuit can be analyzed signal to synchronizing signal analysis and phase-locked control CPU tranmitting data register signal by synchronizing signal analysis and phase-locked control CPU, synchronizing signal analysis is connected differential circuit with phase-locked control CPU, differential circuit connects communication clock and frequency dividing circuit, synchronizing signal analyzes the phase-locked command that exports with phase-locked control CPU to differential circuit, differential circuit by phase-locked burst transmissions to communication clock and frequency dividing circuit.
From said structure, embedded scm is introduced as phase-locked control in communication unit of the present invention, symbolic states in monitoring communication flows, intelligent decision, synchronizing signal in information flow is 32 bit synchronization codes of regular feature, can effectively judge to identify compared with random Millisecond disturbing pulse, after single-chip microcomputer often detects a frame synchronization code element, just a lock-out pulse can accurately be generated, this lock-out pulse is produced by software simulation, start forward position and can reach high accuracy, " clearing " the end triggering phase-locked frequency demultiplication device is removed in this pulse, force communication clock subsequently to aim at and trigger edge, the accurate clock with frequency homophase can be obtained thus in each terminal, even if also can not suffer that under strong interference environment step-out is destroyed, thus make remote synchronization communication obtain high interference free performance.
Claims (1)
1. a remote synchronization communication clock intelligence phase-locking device, it is characterized in that: comprise the signal receiving circuit be connected with signal transmssion line, described signal receiving circuit is connected with master cpu by communication chip, described signal receiving circuit is also connected with phase-locked control CPU with a synchronizing signal analysis, synchronizing signal analysis and phase-locked control CPU can directly receive the data-signal carried from signal receiving circuit, also comprise a communication clock and frequency dividing circuit, described communication clock and frequency dividing circuit connect communication chip and synchronizing signal analysis and phase-locked control CPU respectively; Described synchronizing signal analysis is connected differential circuit with phase-locked control CPU, and described differential circuit connects communication clock and frequency dividing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410784174.1A CN104410411A (en) | 2014-12-16 | 2014-12-16 | Intelligent phase locking device for long-distance synchronous communication clock |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410784174.1A CN104410411A (en) | 2014-12-16 | 2014-12-16 | Intelligent phase locking device for long-distance synchronous communication clock |
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| CN104410411A true CN104410411A (en) | 2015-03-11 |
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| CN201410784174.1A Pending CN104410411A (en) | 2014-12-16 | 2014-12-16 | Intelligent phase locking device for long-distance synchronous communication clock |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117007911A (en) * | 2023-09-27 | 2023-11-07 | 陕西陶网新智软件科技有限公司 | Fault detection device, system and use method of Direct Current (DC) bus line |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5526379A (en) * | 1992-11-04 | 1996-06-11 | Nec Corporation | Method of selecting the most desirable code search mode in a pager in the case of frame async |
| CN101009544A (en) * | 2006-01-27 | 2007-08-01 | 大唐移动通信设备有限公司 | System and method of automatic phase-locking tracking clock synchronization |
| CN101871968A (en) * | 2009-04-24 | 2010-10-27 | 郑州威科姆科技股份有限公司 | Reliable time scale pulse measurement method and measurement device thereof |
| CN102801174A (en) * | 2012-08-31 | 2012-11-28 | 长沙威胜能源产业技术有限公司 | Main control module for low-voltage dynamic reactive harmonic comprehensive compensation device |
| CN103067112A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Clock synchronization method and device and network equipment |
| CN203180892U (en) * | 2013-03-27 | 2013-09-04 | 北京中水科水电科技开发有限公司 | DCF77 code generating device based on synchronous clock signal of satellite |
| CN204272082U (en) * | 2014-12-16 | 2015-04-15 | 镇江中煤电子有限公司 | Remote Synchronous Communication Clock Intelligent Phase Locking Device |
-
2014
- 2014-12-16 CN CN201410784174.1A patent/CN104410411A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5526379A (en) * | 1992-11-04 | 1996-06-11 | Nec Corporation | Method of selecting the most desirable code search mode in a pager in the case of frame async |
| CN101009544A (en) * | 2006-01-27 | 2007-08-01 | 大唐移动通信设备有限公司 | System and method of automatic phase-locking tracking clock synchronization |
| CN101871968A (en) * | 2009-04-24 | 2010-10-27 | 郑州威科姆科技股份有限公司 | Reliable time scale pulse measurement method and measurement device thereof |
| CN102801174A (en) * | 2012-08-31 | 2012-11-28 | 长沙威胜能源产业技术有限公司 | Main control module for low-voltage dynamic reactive harmonic comprehensive compensation device |
| CN103067112A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Clock synchronization method and device and network equipment |
| CN203180892U (en) * | 2013-03-27 | 2013-09-04 | 北京中水科水电科技开发有限公司 | DCF77 code generating device based on synchronous clock signal of satellite |
| CN204272082U (en) * | 2014-12-16 | 2015-04-15 | 镇江中煤电子有限公司 | Remote Synchronous Communication Clock Intelligent Phase Locking Device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117007911A (en) * | 2023-09-27 | 2023-11-07 | 陕西陶网新智软件科技有限公司 | Fault detection device, system and use method of Direct Current (DC) bus line |
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Application publication date: 20150311 |