CN104392959A - Method for manufacturing dual damascene structure - Google Patents
Method for manufacturing dual damascene structure Download PDFInfo
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- CN104392959A CN104392959A CN201410710830.3A CN201410710830A CN104392959A CN 104392959 A CN104392959 A CN 104392959A CN 201410710830 A CN201410710830 A CN 201410710830A CN 104392959 A CN104392959 A CN 104392959A
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- layer
- hard mask
- manufacture method
- double damask
- damask structure
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000009977 dual effect Effects 0.000 title claims abstract description 15
- 239000010949 copper Substances 0.000 claims abstract description 22
- 239000003989 dielectric material Substances 0.000 claims abstract description 20
- 229910052802 copper Inorganic materials 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 4
- 239000011737 fluorine Substances 0.000 claims abstract description 4
- 235000015847 Hesperis matronalis Nutrition 0.000 claims description 28
- 240000004533 Hesperis matronalis Species 0.000 claims description 28
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 8
- BLIQUJLAJXRXSG-UHFFFAOYSA-N 1-benzyl-3-(trifluoromethyl)pyrrolidin-1-ium-3-carboxylate Chemical compound C1C(C(=O)O)(C(F)(F)F)CCN1CC1=CC=CC=C1 BLIQUJLAJXRXSG-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 229910052743 krypton Inorganic materials 0.000 claims description 3
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- RPSSQXXJRBEGEE-UHFFFAOYSA-N xenon tetrafluoride Chemical compound F[Xe](F)(F)F RPSSQXXJRBEGEE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 11
- 238000007747 plating Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000003814 drug Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002484 inorganic compounds Chemical class 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for manufacturing dual damascene structure. The method comprises the following steps: after forming a dual damascene pattern with a trench in a dielectric layer and a hard mask layer, firstly using fluorine-containing gas dry etching to remove the hard mask layer, then depositing a barrier layer, a seed layer and metallic copper, thereby finally forming the dual damascene structure. The method can reduce the overall film layer thickness and aspect ratio of the characteristic structure before the coppering technology after the hard mask layer is removed, and enlarge the window of coppering technology; the method can further prevent the dielectric layer such as an ultralow dielectric material from damage during the process of removing the hard mask layer via wet etching of the prior art, and avoid the probability of metal entering the dielectric layer under the effect of the wet method liquid, thereby solving the problems of electric leakage and reliability of dielectric layer.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor device, particularly relate to a kind of manufacture method of double damask structure.
Background technology
In the technological development of very lagre scale integrated circuit (VLSIC), along with due to the lifting of chip speed, the reduction etc. of power consumption, the delay of the delay of metal interconnecting wires far super device.In order to reduce interconnect delay, ultra-low dielectric materials replaces silicon dioxide thus can reduce dielectric constant, and reduces interconnection capacitance; Copper instead of aluminium thus can reduce interconnection resistance and improve electric migration performance.Traditional aluminium technique adopts first depositing metal aluminium, then photoetching, etching are carried out to metallic aluminium, and metallic copper forces down due to saturated steam, cannot remove from the accessory substance of etching, namely the Damascus technics adopted carries out photoetching, etching to medium, is then barrier layer, the deposit of inculating crystal layer and copper plating and cmp (CMP).But along with the reduction of characteristic size and the use of ultra-low dielectric materials, in order to prevent the damage to dielectric materials in process of removing photoresist after the etch, improve lithographic process window, metal hard mask obtains more and more general application.Metal hard mask dual damascene process is after ultra-low dielectric materials deposit, and deposit titanium nitride (TiN) etc. are as hard mask material.First be the photoetching to titanium nitride, etching thus definition groove characteristic size, be then the photoetching of through hole, follow-up etching comprises, the etching of through hole, etch chamber internal in-situ removes photoresist subsequently, be afterwards groove and throughhole portions while etching, thus formed double damask structure.
Due to characteristic size continue reduce, in order to ensure the covering of bottom and side wall barrier layer and inculating crystal layer, thus the copper preventing the diffusion of copper in ultra-low dielectric materials follow-up plating, need the certain thickness barrier layer of deposit and inculating crystal layer, the aperture efficiency characteristic size that plating can be made like this to face is less, thus increases the difficulty of copper-plating technique.In order to increase copper-plating technique window, need to reduce total thicknesses of layers as far as possible, the titanium nitride in existing dual damascene process is graphical for dual damascene process, is remove in copper CMP technique in follow-up metallization process.By removing the hard mask of titanium nitride after dual damascene process etching, will help and reduce total thicknesses of layers, thus effectively increase copper-plating technique window.
At present, removing the methods that mask adopts usually firmly such as titanium nitride is, after dual damascene process etching, introduces organic or inorganic compound and carry out wet etching to remove in follow-up wet method degumming process.The shortcoming of the method is, because the ultra-low dielectric materials of double damask structure sidewall after etching exposes completely, has Titanium to enter into the possibility of ultra-low dielectric materials under the effect of wet liquid medicine, thus causes the problem of electric leakage and medium reliability.Chinese patent application CN103094184 A proposes and adopts the hydrofluoric acid of dilution to remove hard mask, but the hydrofluoric acid of dilution can cause damage to ultra-low dielectric materials, affects device performance.
Summary of the invention
The object of the invention is to make up above-mentioned the deficiencies in the prior art, a kind of manufacture method of double damask structure is provided, before removing the hard mask such as titanium nitride and reducing copper facing while total thicknesses of layers of feature structure and depth-width ratio, avoid the damage to dielectric layers such as ultra-low dielectric materials in removal process.
For achieving the above object, the invention provides a kind of manufacture method of double damask structure, it comprises the following steps:
Step S01, provides a silicon chip substrate, and forms dielectric layer and hard mask layer successively over the substrate;
Step S02, utilizes chemical wet etching, in described dielectric layer and hard mask layer, form groove, and forms dual damascene figure;
Step S03, utilizes fluoro-gas dry etching to remove described hard mask layer;
Step S04, forms barrier layer and/or inculating crystal layer in described trench bottom surfaces and sidewall, and in described groove, forms metallic copper, to form double damask structure.
Further, described fluoro-gas is the compound containing fluorine element and inert gas elements.
Further, described fluoro-gas is xenon difluoride, xenon tetrafluoride or tetrafluoride krypton.
Further, in step S03, the flow of fluoro-gas is 3-20sccm.
Further, the reaction temperature of step S03 is 50-300 DEG C, and reaction pressure is 0.3-2Torr.
Further, step S03 and step S02 completes in same cavity.
Further, described hard mask layer is titanium nitride or tantalum nitride.
Further, described hard mask layer thickness is
Further, described barrier layer and/or inculating crystal layer are Ti/TiN/Cu or Ta/TaN/Cu.
Further, described dielectric layer is ultra-low dielectric materials.
The manufacture method of double damask structure provided by the invention, by after dielectric layer and hard mask layer form the fluted dual damascene figure of tool, first utilize fluoro-gas dry etching, remove hard mask layer, carry out the deposit of barrier layer, inculating crystal layer and metallic copper subsequently, finally form double damask structure.Method of the present invention can reduce total thicknesses of layers and the depth-width ratio of copper-plating technique (metallic copper deposit) front feature structure after removing hard mask layer, increase the window of copper-plating technique, the present invention also can avoid prior art wet etching to remove damage to dielectric layers such as ultra-low dielectric materials in hard mask process, and under the effect of wet liquid medicine can be avoided, have metal to enter into the possibility of dielectric layer, solve the problem of electric leakage and dielectric layer reliability.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention be described in detail, wherein:
Fig. 1 to Fig. 5 is each step structural representation of the double damask structure manufacture method of first embodiment of the invention.
Embodiment
The manufacture method of double damask structure of the present invention, it comprises the following steps:
Step S01, provides a silicon chip substrate, and forms dielectric layer and hard mask layer successively over the substrate;
Step S02, utilizes chemical wet etching, in described dielectric layer and hard mask layer, form groove, and forms dual damascene figure;
Step S03, utilizes fluoro-gas dry etching to remove described hard mask layer;
Step S04, forms barrier layer and/or inculating crystal layer in described trench bottom surfaces and sidewall, and in described groove, forms metallic copper, to form double damask structure.
The manufacture method of double damask structure provided by the invention, by after dielectric layer and hard mask layer form the fluted dual damascene figure of tool, first utilize fluoro-gas dry etching, remove hard mask layer, carry out the deposit of barrier layer, inculating crystal layer and metallic copper subsequently, finally form double damask structure.Method of the present invention can reduce total thicknesses of layers and the depth-width ratio of copper-plating technique (metallic copper deposit) front feature structure after removing hard mask layer, increase the window of copper-plating technique, the present invention also can avoid prior art wet etching to remove damage to dielectric layers such as ultra-low dielectric materials in hard mask process, and under the effect of wet liquid medicine can be avoided, have metal to enter into the possibility of dielectric layer, solve the problem of electric leakage and dielectric layer reliability.
Particularly, as shown in Figure 1, step S01 comprises provides a silicon chip substrate 11, and forms ultra-low dielectric materials layer 12 and the titanium nitride layer 13 as hard mask successively on the substrate 11.Wherein, ultra-low dielectric materials layer can be carbon doped silicon dioxide or porous carbon doping silicon dioxide; Titanium nitride layer is formed by physical vapor deposition, and its thickness is preferably
the present embodiment is
As shown in Figure 2, step S02 comprises and utilizes lithographic etch process, and graphical ultra-low dielectric materials layer 12 and titanium nitride layer 13 to form groove 14, thus form the dual damascene figure with groove 14.This step realizes by conventional means, therefore repeats no more.
As shown in Figure 3, step S03 comprise utilize fluoro-gas dry etching remove titanium nitride layer 13, the damage that this step avoids the ultra-low dielectric materials of existing wet-etching technology to trench bottom surfaces and sidewall to cause by dry etching, also wet etching liquid used can be avoided to make Titanium enter into ultra-low dielectric materials, thus avoid electric leakage, improve the reliability of ultra-low dielectric materials.
Wherein, in this step, fluoro-gas is preferably xenon difluoride, and it has higher etch rate to titanium nitride.In this step, xenon difluoride flow is preferably 3-20sccm, and the present embodiment is 10sccm; Reaction temperature in reaction cavity is preferably 50-300 DEG C, and the present embodiment is 90 DEG C; Reaction pressure is preferably 0.3-2Torr, the non-1.0Torr of the present embodiment.This step can adopt in-situ process, and namely same cavity, with Simplified flowsheet, also can adopt independent cavity with step S02, and the present embodiment adopts the xenon difluoride cavity of Sheng Mei semiconductor company.
As shown in Figure 4, after removal titanium nitride layer 13, just can carry out the subsequent technique of double damask structure, form barrier layer and/or inculating crystal layer in groove 14 bottom surface and sidewall, and in groove 14 depositing metal copper (copper-plating technique), to form double damask structure.Wherein, barrier layer and/or inculating crystal layer can be Ti/TiN/Cu, TaN/Ta/Cu etc.
As shown in Figure 5, cmp (CMP) is carried out to silicon chip, completes the making of double damask structure.
In other embodiments, hard mask layer can also be tantalum nitride; In dry etch process, etching gas that is corresponding with hardmask layer, that this material is had to higher etch rate such as xenon tetrafluoride, tetrafluoride krypton etc. can be selected to contain the compound of fluorine element and inert gas elements, to remove this hard mask layer.
Claims (10)
1. a manufacture method for double damask structure, is characterized in that, it comprises the following steps:
Step S01, provides a silicon chip substrate, and forms dielectric layer and hard mask layer successively over the substrate;
Step S02, utilizes chemical wet etching, in described dielectric layer and hard mask layer, form groove, and forms dual damascene figure;
Step S03, utilizes fluoro-gas dry etching to remove described hard mask layer;
Step S04, forms barrier layer and/or inculating crystal layer in described trench bottom surfaces and sidewall, and in described groove, forms metallic copper, to form double damask structure.
2. the manufacture method of double damask structure according to claim 1, is characterized in that: described fluoro-gas is the compound containing fluorine element and inert gas elements.
3. the manufacture method of double damask structure according to claim 2, is characterized in that: described fluoro-gas is xenon difluoride, xenon tetrafluoride or tetrafluoride krypton.
4. the manufacture method of the double damask structure according to any one of claims 1 to 3, is characterized in that: in step S03, the flow of fluoro-gas is 3-20sccm.
5. the manufacture method of double damask structure according to claim 4, is characterized in that: the reaction temperature of step S03 is 50-300 DEG C, and reaction pressure is 0.3-2Torr.
6. the manufacture method of double damask structure according to claim 4, is characterized in that: step S03 and step S02 completes in same cavity.
7. the manufacture method of the double damask structure according to any one of claims 1 to 3, is characterized in that: described hard mask layer is titanium nitride or tantalum nitride.
8. the manufacture method of double damask structure according to claim 7, is characterized in that: described hard mask layer thickness is
9. the manufacture method of double damask structure according to claim 1, is characterized in that: described barrier layer and/or inculating crystal layer are Ti/TiN/Cu or Ta/TaN/Cu.
10. the manufacture method of double damask structure according to claim 1, is characterized in that: described dielectric layer is ultra-low dielectric materials.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410710830.3A CN104392959A (en) | 2014-11-28 | 2014-11-28 | Method for manufacturing dual damascene structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410710830.3A CN104392959A (en) | 2014-11-28 | 2014-11-28 | Method for manufacturing dual damascene structure |
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| Publication Number | Publication Date |
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| CN104392959A true CN104392959A (en) | 2015-03-04 |
Family
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410710830.3A Pending CN104392959A (en) | 2014-11-28 | 2014-11-28 | Method for manufacturing dual damascene structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN104392959A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346420A (en) * | 2018-09-11 | 2019-02-15 | 武汉新芯集成电路制造有限公司 | A method of detection damascene structure electric conductivity |
| CN112349650A (en) * | 2019-08-06 | 2021-02-09 | 芯恩（青岛）集成电路有限公司 | Damascus structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1444275A (en) * | 2002-03-07 | 2003-09-24 | 中芯国际集成电路制造(上海)有限公司 | Double mosaic process |
| US20050266681A1 (en) * | 2003-09-19 | 2005-12-01 | International Business Machines Corp. | Formation of low resistance via contacts in interconnect structures |
| CN103839876A (en) * | 2012-11-27 | 2014-06-04 | 盛美半导体设备（上海）有限公司 | Method and device for manufacturing semiconductor device |
-
2014
- 2014-11-28 CN CN201410710830.3A patent/CN104392959A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1444275A (en) * | 2002-03-07 | 2003-09-24 | 中芯国际集成电路制造(上海)有限公司 | Double mosaic process |
| US20050266681A1 (en) * | 2003-09-19 | 2005-12-01 | International Business Machines Corp. | Formation of low resistance via contacts in interconnect structures |
| CN103839876A (en) * | 2012-11-27 | 2014-06-04 | 盛美半导体设备（上海）有限公司 | Method and device for manufacturing semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346420A (en) * | 2018-09-11 | 2019-02-15 | 武汉新芯集成电路制造有限公司 | A method of detection damascene structure electric conductivity |
| CN109346420B (en) * | 2018-09-11 | 2021-04-06 | 武汉新芯集成电路制造有限公司 | Method for detecting conductivity of damascene structure |
| CN112349650A (en) * | 2019-08-06 | 2021-02-09 | 芯恩（青岛）集成电路有限公司 | Damascus structure and preparation method thereof |
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