CN104376814B - Driving circuit, driving method, display panel and display device - Google Patents
Driving circuit, driving method, display panel and display device Download PDFInfo
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- CN104376814B CN104376814B CN201410692009.3A CN201410692009A CN104376814B CN 104376814 B CN104376814 B CN 104376814B CN 201410692009 A CN201410692009 A CN 201410692009A CN 104376814 B CN104376814 B CN 104376814B
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Abstract
The invention provides a driving circuit and a driving method thereof, a display panel and a display device, wherein the driving circuit comprises a first transistor, a second transistor, a third transistor and a coupling capacitor; the display panel comprises a plurality of shift register circuits and a plurality of light-emitting driving circuit units which are connected in series, wherein each light-emitting driving circuit unit comprises a driving circuit of 3T1C, and an input end of each light-emitting driving circuit unit is coupled to an output end of the corresponding shift register circuit. The driving circuit provided by the invention has a simple structure and is easy to realize the narrow frame of the display panel; after being coupled with the corresponding shift register circuit, the scanning signal of the line is accessed, and then an Emit control signal can be generated, so that the positive and negative scanning functions can be realized.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of drive circuit and its driving method, display panel, display
Device.
Background technology
In order to compensate influence of the difference such as threshold value and mobility to display characteristic between OLED pixel efferent duct, OLED pixel
Need to design various compensation circuits.And compensation circuit needs peripheral driving circuit to provide input signal according to certain sequential.
When OLED pixel circuit is PMOS circuits, Emit control signals are generally low level signal, mainly there is two at present
Kind Emit signal generation modes：1. cascade negative pulse shift circuit directly generates；2. cascade positive pulse shift circuit connects phase inverter
Generation.And in general cascade negative pulse shift circuit directly generates circuit structure complexity needed for reverse impulse, if being used for bottom gate
NMOS Oxide semiconductor device circuits can more take up space, cause narrow frame to be difficult to.Connect using positive pulse shift circuit
The design of phase inverter is, it is necessary to which the concatenation of two functional circuits, takes up space also very big.And if being not added with preceding crystal drive circuit, with sweeping for VSR
Retouch input of the signal as phase inverter, it is necessary to take scanning signal from next line, thus can not realize and positive and negative sweep function.
The content of the invention
The embodiment of the present invention provides a kind of drive circuit, including the first transistor, second transistor, third transistor and coupling
Electric capacity is closed, wherein, the grid of the first end of the first transistor, the first pole plate of coupled capacitor and second transistor is connected to the
One node；
The first end of second transistor and the first end of third transistor are connected to section point；
The grid of the first transistor is coupled to the first clock signal terminal, and the second end is coupled to input；
Second end of second transistor is coupled to second clock signal end；
The grid of third transistor is coupled to the 3rd clock signal terminal, and the second end is coupled to high level signal end；
Second pole plate of coupled capacitor is coupled to the 4th clock signal terminal；
Output end of the section point as the drive circuit.
On the other hand, the embodiment of the present invention also provides the driving method of above-mentioned drive circuit, including：
To the first clock signal terminal, the 3rd clock signal terminal input high level, control the first transistor, third transistor are beaten
Open, the first transistor transmits input signal to first node, and the third transistor transmits high level signal to the second section
Point；
To the 4th clock signal terminal input low level；
Saltus step occurs for the first clock signal terminal and the signal of the 3rd clock signal terminal input, is low electricity by high level saltus step
Flat, control the first transistor, third transistor are closed；
To second clock signal end input low level；
Saltus step occurs for the 4th clock signal, by low transition to high level, is drawn high by the boot strap of coupled capacitor
The current potential of first node, opens second transistor, transmission second clock signal to section point.
On the other hand, the embodiment of the present invention also provides a kind of display panel, includes the multi-stage shift register circuit of series connection
With multiple light emission drive circuit units, light emission drive circuit unit includes above-mentioned drive circuit, wherein, the drive circuit it is defeated
Enter the output end that end is coupled to corresponding shift-register circuit.
On the other hand, the embodiment of the present invention also provides a kind of display device, including above-mentioned display panel.
Drive circuit provided in an embodiment of the present invention, only 3T1C, it is simple in construction, it is easy to accomplish narrow frame；With it is corresponding
After shift-register circuit coupling, the scanning signal of one's own profession is accessed, you can generation Emit control signals, therefore positive and negative sweep can be realized
Function.
Brief description of the drawings
Fig. 1 is the driving circuit structure schematic diagram that the embodiment of the present invention one provides；
Fig. 2 is the drive signal timing diagram for the drive circuit that the embodiment of the present invention one provides；
Fig. 3 is another drive signal timing diagram for the drive circuit that the embodiment of the present invention one provides；
Fig. 4 is the another embodiment for the drive circuit that the embodiment of the present invention one provides；
Fig. 5 is another driving circuit structure schematic diagram that the embodiment of the present invention two provides；
Fig. 6 is the driving method schematic flow sheet for the drive circuit that the embodiment of the present invention three provides；
Fig. 7 is the display panel schematic diagram that the embodiment of the present invention four provides；
Fig. 8 is the enlarged schematic partial view of the embodiment of the present invention four.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention is illustrate only in description, accompanying drawing and not all.
Embodiment one
Fig. 1 show the preferred embodiment of the present invention one offer drive circuit, as shown in figure 1, including the first transistor M1,
Second transistor M2, third transistor M3 and coupled capacitor C1, specifically, the first transistor M1 first end, coupled capacitor
C1 the first pole plate and second transistor M2 grid are connected to first node Q；Second transistor M2 first end and the 3rd
Transistor M3 first end is connected to section point N；The first transistor M1 grid is coupled to the first clock signal terminal CK1, the
Two ends are coupled to input IN；Second transistor M2 the second end is coupled to second clock signal end CK2；Third transistor M3's
Grid is coupled to the 3rd clock signal terminal CK3, and the second end is coupled to high level signal end VGH；Coupled capacitor C1 the second pole plate
It is coupled to the 4th clock signal terminal CK4；Output end OUTs of the section point N as the drive circuit.Wherein, the first transistor
M1, second transistor M2, third transistor M3 are N-type TFT, and first end refers to NTFT source electrode, and the second end refers to
NTFT drain electrode.
Fig. 2 show a kind of driver' s timing figure of above-mentioned drive circuit, as shown in Fig. 2 the first clock signal terminal CK1,
Two clock signal terminal CK2, the 3rd clock signal terminal CK3 can input identical clock signal.Therefore, the company of above-mentioned drive circuit
Relation is connect, further can be the first transistor M1 grid, second transistor M2 the second end, third transistor M3 grid
Pole is coupled to same point, as shown in figure 4, the another embodiment of the drive circuit provided for the embodiment of the present invention one.With reference to
Drive signal sequential shown in Fig. 2, the operation principle for the drive circuit that embodiment one provides are as follows：
At the T1 moment shown in Fig. 2, the first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal
CK3 input high level signals are held, wherein, the first clock signal CK1 control the first transistors M1 is opened, the 3rd clock signal CK3
Control third transistor M3 to open, signal input part IN input high level signals, transmitted by the first transistor M1 to first segment
Point Q, third transistor M3 transmission high level signal VGH to section point N so that output end OUT exports high level, and completes high
Level IN signals are transmitted to Q points.Now, the 4th clock signal terminal CK4 input low level signals.
At the T2 moment, the first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal terminal CK3 inputs
Signal saltus step occurs, low level is changed into from high level, the first clock signal CK1 control the first transistors M1 is closed, when the 3rd
Clock signal CK3 control third transistor M3 is closed.Due to the presence of the first transistor M1 or second transistor M2 parasitic capacitance,
So that the current potential of Q points arrives with CK1, CK2 trailing edge and slightly dragged down, it is not enough to open M2 completely.Afterwards, the 4th clock is believed
Saltus step occurs for the signal of number end CK4 inputs, is changed into high level from low level, due to coupled capacitor C1 boot strap so that the
One node Q current potential is driven high with the arrival of CK4 rising edge.
At the T3 moment, because first node Q current potential is driven high, it is sufficient to so that second transistor M2 is opened, now the
Two clock signal terminal CK2 still input low levels.The low level signal that second transistor M2 inputs second clock signal end CK2
Transmit to section point N, also output end OUT output low level.
At the T4 moment, the first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal terminal CK3 are inputted
Saltus step occurs for signal, is changed into high level from low level, the first clock signal CK1 control the first transistors M1 is opened, the 3rd clock
Signal CK3 control third transistor M3 is opened.Third transistor M3 transmits high level VGH to section point N so that output end
OUT exports high level.Afterwards, saltus step occurs for the signal of the 4th clock signal terminal CK4 inputs, by high level saltus step to low level.
From the operation principle of above-mentioned drive circuit, when the output signal OUT of this drive circuit trailing edge is by the 4th
Clock signal CK4 rising edge is controlled, and output signal OUT rising edge is determined by the 3rd clock signal CK3 rising edge.Drive
Coupled capacitor C1 in dynamic circuit is used to compensating the first clock signal CK1 or second clock signal CK2 when pulling down, and Q points are because the
One transistor M1 or second transistor M2 parasitic capacitance and the factor being pulled down, if electric capacity is too small, it may cause second brilliant
Body pipe M2 can not be opened fully；If electric capacity, which crosses conference, causes the shake of output signal.
Fig. 3 show another driver' s timing figure of embodiment one drive circuit.Wherein, the first clock letter of drive circuit
Number end CK1 and the 3rd clock signal terminal CK3 input identical clock signals, second clock signal end CK2 input constant low electricity
It is flat.
Under the driver' s timing shown in Fig. 3, its operation principle driving principle substantially as shown in Figure 2 is similar, distinctive points
It is, when the first clock signal terminal CK1 is at the T2 moment, when by high level saltus step being low level, only posting by the first transistor M1
Raw electric capacity, drag down first node Q current potential so that Q point current potentials are not enough to open second transistor M2.In the 4th clock signal terminal
When CK4 input signals are by low transition to high level, by coupled capacitor C1 boot straps, first node Q current potential, institute are drawn high
The coupled capacitor C1 needed capacitance can be with more smaller.Other exist with the driving principle process of driver' s timing identical shown in Fig. 2
This is repeated no more.
Embodiment two
Fig. 5 is another driving circuit structure that the embodiment of the present invention two provides, as shown in figure 5, including the first transistor
M1, second transistor M2, third transistor M3 and coupled capacitor C1, specifically, the first transistor M1 first end, coupling electricity
Hold C1 the first pole plate and second transistor M2 grid is connected to first node Q；Second transistor M2 first end and the
Three transistor M3 first end is connected to section point N；The first transistor M1 grid is coupled to the first clock signal terminal CK1,
Second end is coupled to input IN；Second transistor M2 the second end is coupled to second clock signal end CK2；Third transistor M3
Grid be coupled to the 3rd clock signal terminal CK3, the second end is coupled to high level signal end VGH；Coupled capacitor C1 the second pole
Plate is coupled to the 4th clock signal terminal CK4；Output end OUTs of the section point N as the drive circuit.Wherein, first crystal
Pipe M1, third transistor M3 are p-type TFT, and second transistor M2 is N-type TFT.Second transistor M2DE first ends refer to source
Pole, the second end refer to NTFT drain electrode.The first transistor M1 and third transistor M3 first end refer to draining, the second end
Refer to source electrode.
Because the first transistor M1 and third transistor M3 are p-type TFT, therefore the first clock for controlling it to open and close
Signal CK1 and the 3rd clock signal CK3, it is opposite with the signal of drive circuit shown in embodiment one.
Equally, the drive circuit shown in embodiment two, its first clock signal terminal CK1 and the 3rd clock signal terminal CK3 can
To be coupled to same point.Therefore it can also have another embodiment.
Further, the driver' s timing of the drive circuit shown in embodiment two, wherein second clock signal CK2, as implemented
Example one, can be impulse wave or constant low level value.The driving principle of drive circuit and implementation shown in embodiment two
The driving principle of drive circuit is roughly the same shown in example one, only difference is that：The first transistor M1's and third transistor M3
Type is PTFT, therefore controls the signal value of its opening and closing opposite.Therefore, the driver' s timing figure of embodiment two is no longer detailed
Description.
Embodiment three
As shown in fig. 6, the driving method of the drive circuit provided for the preferred embodiment of the present invention, wherein, drive circuit knot
Structure is as shown in figure 1, including including the first transistor M1, second transistor M2, third transistor M3 and coupled capacitor C1, and described the
One~third transistor is N-type TFT, and the first transistor M1 first end, coupled capacitor C1 the first pole plate and second are brilliant
Body pipe M2 grid is connected to first node Q；Second transistor M2 first end and third transistor M3 first end are connected to
Section point N；The first transistor M1 grid is coupled to the first clock signal terminal CK1, and the second end is coupled to input signal end IN；
Second transistor M2 the second end is coupled to second clock signal end CK2；Third transistor M3 grid is coupled to the 3rd clock
Signal end CK3, the second end are coupled to high level signal VGH；The second pole plate of the coupled capacitor C1 is coupled to the 4th clock letter
Number end CK4；Output signal end OUTs of the section point N as drive circuit.Driving method includes：
(1) to the first clock signal terminal CK1, the 3rd clock signal terminal CK3 input high levels, control the first transistor M1,
Third transistor M3 is opened, and the first transistor M1 transmits input signal IN to first node Q, and the third transistor M3 is passed
Defeated high level signal VGH to section point N；To the 4th clock signal input low level；
Saltus step occurs for the signal of (2) first clock signal terminal CK1 and the 3rd clock signal terminal CK3 inputs, is jumped by high level
It is changed into low level, control the first transistor M1, third transistor M3 are closed；To second clock signal end CK2 input low levels；
Saltus step occurs for the signal of (3) the 4th clock signal terminal CK4 inputs, by low transition to high level, passes through coupling
First node Q current potential is drawn high in electric capacity C1 boot strap, opens second transistor M2, and transmission second clock signal CK2 is extremely
Section point N；
Saltus step occurs for the signal of (4) first clock signal terminal CK1 and the 3rd clock signal terminal CK3 inputs, is jumped by low level
It is changed into high level, control the first transistor M1, third transistor M3 are opened.The signal of 4th clock signal terminal CK4 inputs is by height
Level saltus step is low level.
Wherein, in (2) and (3) stage, the first clock signal CK1 is occurred by high level saltus step to low level
Before 4th clock signal CK4 is by low transition to high level.And in (4) stage, the first clock signal CK1 is by low level
Saltus step occurs before the 4th clock signal CK4 is by high level saltus step to low level to high level.Output signal OUT decline
Edge is controlled by the 4th clock signal CK4 rising edge, and output signal OUT rising edge is by the upper of the 3rd clock signal CK3
Rise along decision.
Example IV
Fig. 7 show the display panel of preferred embodiment of the present invention offer, in display panel AA areas periphery, is provided with panel
Drive circuit, panel drive circuit include multi-stage shift register circuit VSR1, VSR2, VSR3 ... of series connection, in addition to multiple
Light emission drive circuit unit Emit1, Emit2, Emit3 ..., each light emission drive circuit unit include what previous embodiment provided
Drive circuit.Wherein, every grade of shift-register circuit VSR is mutually cascaded, and each light emission drive circuit unit is posted with every grade of displacement
Latch circuit is corresponding, namely the input of each light emission drive circuit unit is coupled to the defeated of every grade of shift-register circuit
Go out end.
In display panel shift-register circuit VSR and light emission drive circuit unit Emit annexation as shown in figure 8,
Wherein, the corresponding shift-register circuit VSR of a light emission drive circuit unit Emit, i.e. shift-register circuit VSR's
Output end is coupled to light emission drive circuit unit Emit input, and light emission drive circuit unit Emit is in the first clock signal terminal
CK1, second clock signal end CK2, the 3rd clock signal CK3, the 4th clock signal CK4 and high level signal VGH driving
Under, output end OUT exports corresponding low level Emit signals.
Because each light emission drive circuit unit is coupled to the shift-register circuit of one's own profession, therefore, as long as shift LD
The cascade connection of device circuit in itself can realize it is positive and negative sweep function, then this integral panels drive circuit can still realize positive and negative sweep
Function.Furthermore the driving circuit structure that light emission drive circuit unit includes only includes as shown in embodiment one or embodiment two
3T1C, it is simple in construction, it is easy to accomplish narrow frame design.
Embodiment five
The embodiment of the present invention five provides a kind of display device, and it includes the display panel described in example IV.
It is significant to note that " coupling " that is hereinbefore previously mentioned, includes direct or indirect electrical connection.
Obviously, above-described embodiment is only used for the statement present invention in detail, does not form limiting the scope of the invention.
Under the design of the present invention, any various changes and modification for not having creative work and carrying out of one of ordinary skill in the art,
Belong to the protection domain of the claims in the present invention.
Claims (11)
- A kind of 1. drive circuit, it is characterised in that including the first transistor, second transistor, third transistor and coupled capacitor, Wherein,The grid of the first end of the first transistor, the first pole plate of coupled capacitor and second transistor is connected to first segment Point；The first end of the second transistor and the first end of third transistor are connected to section point；The grid of the first transistor is coupled to the first clock signal terminal, and the second end is coupled to input；Second end of the second transistor is coupled to second clock signal end；The grid of the third transistor is coupled to the 3rd clock signal terminal, and the second end is coupled to high level signal end；Second pole plate of the coupled capacitor is coupled to the 4th clock signal terminal；Output end of the section point as the drive circuit；Wherein, the 4th clock signal transitions of the 4th clock signal terminal occur to believe in the first clock of the first clock signal terminal Number saltus step after；The trailing edge of the output signal of the drive circuit is controlled by the rising edge of the 4th clock signal, the output signal Rising edge determined by the rising edge of the 3rd clock signal of the 3rd clock signal terminal.
- 2. drive circuit as claimed in claim 1, it is characterised in that described the first transistor, second transistor and the 3rd Transistor is N-type TFT.
- 3. drive circuit as claimed in claim 2, it is characterised in that described the first clock signal terminal, second clock signal End, the 3rd clock signal terminal input identical clock signal；Or first clock signal terminal, the 3rd clock signal terminal are defeated Enter identical clock signal, the second clock signal inputs constant low level.
- 4. drive circuit as claimed in claim 1, it is characterised in that the second transistor is N-type TFT, and described first is brilliant Body pipe, third transistor are p-type TFT.
- 5. drive circuit as claimed in claim 4, it is characterised in that first clock signal terminal, the 3rd clock signal terminal Input identical clock signal.
- 6. a kind of driving method of drive circuit, it is characterised in that the drive circuit includes the first transistor, the second crystal Pipe, third transistor and coupled capacitor, the first~third transistor are N-type TFT, wherein,The grid of the first end of the first transistor, the first pole plate of coupled capacitor and second transistor is connected to first segment Point；The first end of the second transistor and the first end of third transistor are connected to section point；The grid of the first transistor is coupled to the first clock signal terminal, and the second end is coupled to input signal end；Second end of the second transistor is coupled to second clock signal end；The grid of the third transistor is coupled to the 3rd clock signal terminal, and the second end is coupled to high level signal；Second pole plate of the coupled capacitor is coupled to the 4th clock signal terminal；Output signal end of the section point as the drive circuit；The driving method includes：To the first clock signal terminal, the 3rd clock signal terminal input high level, control the first transistor, third transistor are opened, The first transistor transmits input signal to first node, and the third transistor transmits high level signal to section point；To the 4th clock signal terminal input low level；Saltus step occurs for the first clock signal terminal and the signal of the 3rd clock signal terminal input, is low level by high level saltus step, control The first transistor processed, third transistor are closed；To second clock signal end input low level；Saltus step occurs for the 4th clock signal, and by low transition to high level, first is drawn high by the boot strap of coupled capacitor The current potential of node, opens second transistor, transmission second clock signal to section point.
- 7. driving method as claimed in claim 6, it is characterised in that the saltus step of the 4th clock signal occurs at first After the saltus step of clock signal.
- 8. driving method as claimed in claim 6, it is characterised in that first clock signal terminal, second clock signal end, 3rd clock signal terminal inputs identical clock signal；Or first clock signal terminal, the 3rd clock signal terminal input phase Same clock signal, the second clock signal end input constant low level.
- 9. a kind of display panel, it is characterised in that multi-stage shift register circuit and multiple light emission drive circuits including series connection Unit, the light emission drive circuit unit include the drive circuit as described in claim any one of 1~claim 5, wherein, The input of the drive circuit is coupled to the output end of corresponding shift-register circuit.
- 10. display panel as claimed in claim 9, it is characterised in that the multi-stage shift register circuit can be realized positive and negative Sweep function.
- 11. a kind of display device, it is characterised in that including display panel as claimed in claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410692009.3A CN104376814B (en) | 2014-11-25 | 2014-11-25 | Driving circuit, driving method, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410692009.3A CN104376814B (en) | 2014-11-25 | 2014-11-25 | Driving circuit, driving method, display panel and display device |
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| Publication Number | Publication Date |
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| CN104376814A CN104376814A (en) | 2015-02-25 |
| CN104376814B true CN104376814B (en) | 2017-12-26 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104952420A (en) * | 2015-07-29 | 2015-09-30 | 武汉华星光电技术有限公司 | Multiplexer, as well as data driving circuit and liquid crystal display panel applying multiplexer |
| CN104977768B (en) * | 2015-07-30 | 2018-11-06 | 武汉华星光电技术有限公司 | Liquid crystal display panel and its pixel charging circuit |
| US10297781B2 (en) * | 2016-06-30 | 2019-05-21 | Lg Display Co., Ltd. | Organic light emitting display device and driving method of the same |
| KR20180067948A (en) * | 2016-12-13 | 2018-06-21 | 엘지디스플레이 주식회사 | Shift register and gate driving circuit including the same |
| WO2020113516A1 (en) * | 2018-12-06 | 2020-06-11 | 深圳市柔宇科技有限公司 | Eoa circuit, display panel, and terminal |
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| RU2458460C2 (en) * | 2007-12-28 | 2012-08-10 | Шарп Кабусики Кайся | Semiconductor device and display device |
| TWI480882B (en) * | 2012-09-04 | 2015-04-11 | Au Optronics Corp | Shift register and driving method thereof |
| TWI520117B (en) * | 2014-02-07 | 2016-02-01 | 友達光電股份有限公司 | Shift control cell |
| TWI525596B (en) * | 2014-02-14 | 2016-03-11 | 友達光電股份有限公司 | Light emitting control circuit, driving circuit using the same and active matrix oled display panel using the same |
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