CN104360527A - Array substrate and manufacturing method thereof and display device - Google Patents

Abstract

The invention provides an array substrate, a manufacturing method thereof, and a display device, belonging to the field of display technology. Wherein, the array substrate includes a base substrate and a conductive metal pattern formed on the base substrate, and the array substrate further includes: a color filter layer; a black matrix capable of shielding the conductive metal pattern. The technical solution of the present invention can reduce the influence of the alignment deviation between the array substrate and the color filter substrate on the transmittance of the display panel.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

Liquid crystal displays have been widely used in various display fields, such as homes, public places, office places and personal electronic related products. At present, the manufacturing process of liquid crystal display panels is to make array substrates and color film substrates separately. After the substrates are manufactured separately, they are aligned and boxed.

FIG. 1 is a schematic structural view of an existing color filter substrate. The color filter substrate mainly includes a base substrate 1 , a color filter unit 2 , a black matrix 3 , an alignment layer 4 and a spacer 5 . In addition, there is also COA technology that implements the color filter unit on the array substrate. Figure 2 is a schematic structural diagram of an array substrate in the TN (Twisted Nematic, twisted nematic) mode using COA technology. The array substrate mainly includes a substrate A base substrate 6 , a gate electrode 7 , a gate insulating layer 8 , an active layer 9 , a source electrode 10 , a drain electrode 11 , a color filter unit 12 , a passivation layer 13 and a pixel electrode 14 .

When the array substrate and the color filter substrate are aligned to form a box, due to the limitation of alignment accuracy, defects such as light leakage caused by alignment deviation are prone to occur. In order to avoid light leakage, the black matrix (BlackMatrix, BM) on the color filter substrate must be wide enough, but this will lose the transmittance of the display panel, increase the cost of the backlight, and cause the color filter substrate to have a large step difference.

Contents of the invention

The technical problem to be solved by the present invention is to provide an array substrate, its manufacturing method, and a display device, which can reduce the influence of the alignment deviation between the array substrate and the color filter substrate on the transmittance of the display panel.

In order to solve the above technical problems, embodiments of the present invention provide technical solutions as follows:

In one aspect, an array substrate is provided, including a base substrate and a conductive metal pattern formed on the base substrate, and the array substrate further includes:

color filter layer;

A black matrix capable of shielding the conductive metal pattern.

Further, the conductive pattern includes a gate electrode and a gate line, and the color filter layer is a gate insulating layer covering the gate electrode and the gate line.

Further, the conductive pattern includes source electrodes, drain electrodes and data lines, and the color filter layer is a passivation layer covering the source electrodes, drain electrodes and data lines.

Further, the black matrix is located on the color filter layer.

Further, the conductive pattern includes source electrodes, drain electrodes and data lines, and the color filter layer and the black matrix form a passivation layer covering the source electrodes, drain electrodes and data lines.

Further, the array substrate further includes: spacers formed on the black matrix.

An embodiment of the present invention also provides a display device, including the above-mentioned array substrate.

An embodiment of the present invention also provides a method for manufacturing an array substrate, including forming a conductive metal pattern on the base substrate, and the method further includes:

Form a color filter layer;

A black matrix capable of shielding the conductive metal pattern is formed.

Further, forming the conductive metal pattern includes:

forming gate electrodes and gate lines;

Forming the color filter layer is specifically as follows:

A gate insulating layer covering the gate electrodes and gate lines is formed, and a color filter material is used for the gate insulating layer.

Further, forming the conductive metal pattern includes:

Forming source electrodes, drain electrodes and data lines;

Forming the color filter layer is specifically as follows:

A passivation layer covering the source electrode, the drain electrode and the data line is formed, and the passivation layer adopts a color filter material.

Further, forming the black matrix is specifically:

The black matrix is formed on the color filter layer.

Further, forming the conductive metal pattern includes:

Forming source electrodes, drain electrodes and data lines;

Forming the color filter layer and the black matrix includes:

A passivation layer covering the source electrode, the drain electrode and the data line is formed, the part of the passivation layer is the black matrix, and the other part of the passivation layer is made of color filter material.

Further, the method also includes:

Spacers are formed on the black matrix.

Embodiments of the present invention have the following beneficial effects:

In the above solution, both the black matrix and the color filter layer are formed on the array substrate, so that when the array substrate and the color filter substrate are aligned to form a box, the black matrix on the array substrate can block the In light leakage, the black matrix on the array substrate does not need to be set too wide, which can reduce the influence of the alignment deviation between the array substrate and the color filter substrate on the transmittance of the display panel; in addition, compared with the existing display devices using COA technology , there is no need to form a black matrix on the color filter substrate, which reduces the step difference on the color filter substrate; in addition, the color filter layer can also serve as an insulating layer on the array substrate, which can reduce the number of patterning processes required for making the array substrate and shorten The manufacturing time of the array substrate is shortened, and the manufacturing cost of the array substrate is reduced.

Description of drawings

FIG. 1 is a schematic structural view of an existing color filter substrate;

FIG. 2 is a schematic diagram of conventionally forming a color filter unit on an array substrate;

3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present invention.

reference sign

1.6 Substrate 2.12 Color filter unit 3.15 Black matrix 4 Alignment layer

5 spacer 7 gate electrode 8 gate insulating layer 9 active layer 10 source electrode

11 Drain electrode 13 Passivation layer 14 Pixel electrode

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can reduce the influence of alignment deviation between the array substrate and the color filter substrate on the transmittance of the display panel.

An embodiment of the present invention provides an array substrate including a base substrate and a conductive metal pattern formed on the base substrate, and the array substrate further includes:

color filter layer;

A black matrix capable of shielding the conductive metal pattern.

In this embodiment, both the black matrix and the color filter layer are formed on the array substrate, so that when the array substrate and the color filter substrate are aligned to form a box, the black matrix on the array substrate can block light leakage regardless of whether there is an alignment deviation. , the black matrix on the array substrate does not need to be set too wide, which can reduce the influence of the alignment deviation between the array substrate and the color filter substrate on the transmittance of the display panel; in addition, compared with the existing display devices using COA technology, There is no need to form a black matrix on the color filter substrate, which reduces the step difference on the color filter substrate; in addition, the color filter layer can also serve as an insulating layer on the array substrate, which can reduce the number of patterning processes required to make the array substrate and shorten the length of the array. The manufacturing time of the substrate is shortened, and the manufacturing cost of the array substrate is reduced.

Further, in another embodiment of the present invention, on the basis of the above structure, the conductive pattern includes a gate electrode and a gate line, and the color filter layer is a gate insulating layer covering the gate electrode and the gate line.

Further, in another embodiment of the present invention, on the basis of the above structure, the conductive pattern includes source electrodes, drain electrodes and data lines, and the color filter layer covers the source electrodes, drain electrodes and data lines. Passivation layer of the line.

Furthermore, in another embodiment of the present invention, on the basis of the above structure, the black matrix is located on the color filter layer.

Further, in another embodiment of the present invention, on the basis of the above structure, the conductive pattern includes a source electrode, a drain electrode and a data line, and the color filter layer and the black matrix cover the source electrode , the passivation layer of the drain electrode and the data line.

Furthermore, in another embodiment of the present invention, on the basis of the above structure, the array substrate further includes: spacers formed on the black matrix.

The array substrate in this embodiment may be an array substrate in TN mode. In one embodiment, the array substrate in TN mode specifically includes:

Substrate substrate;

a gate electrode and a gate line located on the base substrate;

a gate insulating layer on the base substrate on which the gate electrodes and gate lines are formed, and the gate insulating layer is made of color filter material;

an active layer located on the gate insulating layer;

A source electrode, a drain electrode, and a data line located on the substrate on which the active layer is formed;

Passivation layer including vias;

A pixel electrode and a black matrix located on the passivation layer, the black matrix can shield gate electrodes, gate lines, source electrodes, drain electrodes and data lines;

A spacer located on the black matrix.

Further, in another embodiment, the array substrate in TN mode specifically includes:

Substrate substrate;

a gate electrode and a gate line located on the base substrate;

a gate insulating layer on the base substrate on which the gate electrodes and gate lines are formed;

an active layer located on the gate insulating layer;

A source electrode, a drain electrode, and a data line located on the substrate on which the active layer is formed;

A passivation layer including via holes on the base substrate on which the source electrode, drain electrode and data line are formed, and the passivation layer adopts a color filter material;

A pixel electrode and a black matrix located on the passivation layer, the pixel electrode is connected to the drain electrode through the via hole, and the black matrix can block the gate electrode, gate line, source electrode, drain electrode and data line ;

A spacer located on the black matrix.

Further, in another embodiment, the array substrate in TN mode specifically includes:

Substrate substrate;

a gate electrode and a gate line located on the base substrate;

a gate insulating layer on the base substrate on which the gate electrodes and gate lines are formed;

an active layer located on the gate insulating layer;

A source electrode, a drain electrode, and a data line located on the substrate on which the active layer is formed;

A passivation layer including via holes on the base substrate on which the source electrode, drain electrode and data line are formed, part of the passivation layer is made of color filter material, and other parts are made of opaque material to form black a matrix, the black matrix can shield gate electrodes, gate lines, source electrodes, drain electrodes and data lines;

a pixel electrode located on the passivation layer, the pixel electrode is connected to the drain electrode through the via hole;

A spacer located on the black matrix.

The array substrate of this embodiment can also be an array substrate of ADS (Advanced Super Dimension Switch, Advanced Super Dimension Switch) mode. In one embodiment, the array substrate of ADS mode includes:

Substrate substrate;

a gate electrode and a gate line located on the base substrate;

a gate insulating layer on the base substrate on which the gate electrodes and gate lines are formed, and the gate insulating layer is made of color filter material;

a common electrode located on the base substrate on which the gate insulating layer is formed;

An intermediate insulating layer including a first via hole located on the base substrate on which the common electrode is formed;

an active layer located on the intermediate insulating layer;

A source electrode, a drain electrode, a data line, and a common electrode line located on the base substrate on which the active layer is formed, and the common electrode line is connected to the common electrode through the first via hole;

a passivation layer including a second via hole on the base substrate on which the source electrode, the drain electrode, the data line and the common electrode line are formed;

A pixel electrode and a black matrix located on the passivation layer, the black matrix can shield gate electrodes, gate lines, source electrodes, drain electrodes, common electrode lines and data lines;

A spacer located on the black matrix.

The embodiment of the present invention also provides a display device, including the above-mentioned array substrate, and the display device can be any product with a display function such as a liquid crystal panel, a liquid crystal TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc. or parts.

The embodiment of the present invention also provides a method for manufacturing an array substrate, including forming a conductive metal pattern on the base substrate, and the method further includes: forming a color filter layer; forming a black matrix capable of shielding the conductive metal pattern .

In this embodiment, both the black matrix and the color filter layer are formed on the array substrate, so that when the array substrate and the color filter substrate are aligned to form a box, the black matrix on the array substrate can block light leakage regardless of whether there is an alignment deviation. , the black matrix on the array substrate does not need to be set too wide, which can reduce the influence of the alignment deviation between the array substrate and the color filter substrate on the transmittance of the display panel; in addition, compared with the existing display devices using COA technology, There is no need to form a black matrix on the color filter substrate, which reduces the level difference on the color filter substrate.

Further, the manufacturing method further includes: forming a spacer on the black matrix; in addition, the color filter layer can also serve as an insulating layer on the array substrate, which can reduce the number of patterning processes required for manufacturing the array substrate, shorten The manufacturing time of the array substrate is shortened, and the manufacturing cost of the array substrate is reduced.

Further, forming the conductive metal pattern includes:

forming gate electrodes and gate lines;

Forming the color filter layer is specifically as follows:

A gate insulating layer covering the gate electrodes and gate lines is formed, and a color filter material is used for the gate insulating layer.

Further, forming the conductive metal pattern includes:

Forming source electrodes, drain electrodes and data lines;

Forming the color filter layer is specifically as follows:

A passivation layer covering the source electrode, the drain electrode and the data line is formed, and the passivation layer adopts a color filter material.

Further, forming the black matrix is specifically:

The black matrix is formed on the color filter layer.

Further, forming the conductive metal pattern includes:

Forming source electrodes, drain electrodes and data lines;

Forming the color filter layer and the black matrix includes:

A passivation layer covering the source electrode, the drain electrode and the data line is formed, the part of the passivation layer is the black matrix, and the other part of the passivation layer is made of color filter material.

Further, the method also includes:

Spacers are formed on the black matrix.

In this embodiment, a TN-mode array substrate can be manufactured. In one embodiment, the method for manufacturing a TN-mode array substrate specifically includes:

providing a base substrate;

forming gate electrodes and gate lines on the base substrate;

forming a gate insulating layer, the gate insulating layer is made of color filter material;

forming an active layer;

Forming source electrodes, drain electrodes and data lines;

forming a passivation layer including vias;

Shaped pixel electrodes and black matrix, the black matrix can shield gate electrodes, gate lines, source electrodes, drain electrodes and data lines;

Spacers are formed on the black matrix.

Further, in another embodiment, the manufacturing method of the TN mode array substrate specifically includes:

providing a base substrate;

forming gate electrodes and gate lines on the base substrate;

forming a gate insulating layer;

forming an active layer;

Forming source electrodes, drain electrodes and data lines;

forming a passivation layer including via holes, the passivation layer adopts a color filter material;

forming a pixel electrode and a black matrix, the pixel electrode is connected to the drain electrode through the via hole, and the black matrix can block the gate electrode, the gate line, the source electrode, the drain electrode and the data line;

Spacers are formed on the black matrix.

Further, in another embodiment, the manufacturing method of the TN mode array substrate specifically includes:

providing a base substrate;

forming gate electrodes and gate lines;

forming a gate insulating layer;

forming an active layer;

Forming source electrodes, drain electrodes and data lines;

A passivation layer including via holes is formed, a part of the passivation layer is made of a color filter material, and other parts are made of an opaque material to form a black matrix, and the black matrix can block the gate electrode, gate line, source electrode, leakage Pole and data line;

forming a pixel electrode, the pixel electrode is connected to the drain electrode through the via hole;

Spacers are formed on the black matrix.

In this embodiment, an array substrate in ADS (Advanced Super Dimension Switch) mode can also be manufactured. In one embodiment, the method for manufacturing an array substrate in ADS mode includes:

providing a base substrate;

forming gate electrodes and gate lines;

forming a gate insulating layer, the gate insulating layer is made of color filter material;

forming a common electrode;

forming an intermediate insulating layer including a first via hole;

forming an active layer;

forming a source electrode, a drain electrode, a data line, and a common electrode line, and the common electrode line is connected to the common electrode through the first via hole;

forming a passivation layer including a second via hole;

forming a pixel electrode and a black matrix capable of shielding gate electrodes, gate lines, source electrodes, drain electrodes, common electrode lines and data lines;

Spacers are formed on the black matrix.

The array substrate and its manufacturing method of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments:

Embodiment one

The array substrate in this embodiment is an array substrate in TN mode, and the method for manufacturing the array substrate in this embodiment specifically includes the following steps:

Step 1, providing a base substrate 6, forming patterns of gate electrodes 7 and gate lines on the base substrate 6;

Wherein, the base substrate 6 may be a glass substrate or a quartz substrate. Specifically, sputtering or thermal evaporation can be used to deposit a thickness of about The gate metal layer, the gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the gate metal layer can be single-layer structure or multi-layer Structure, multi-layer structure such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the gate metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the grid line and the gate electrode 7 is located, the unretained area of photoresist corresponds to the area outside the above-mentioned pattern; the development process is carried out, and the photoresist in the unreserved area of photoresist is completely removed, and the area of photoresist reserved area is completely removed. The thickness of the photoresist remains unchanged; the gate metal film in the area not retained by the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form the pattern of the gate line and the gate electrode 7 .

Step 2, forming a gate insulating layer 8 on the base substrate 6 after completing step 1;

Specifically, colored photoresist can be coated on the base substrate 6 that has completed step 1, and the coating method of the colored photoresist can be applied by spin coating to form a gate insulating layer 8. The gate insulating layer 8 includes a plurality of colored photoresists. In the filter unit 12, the color photoresist in the removed area is completely removed.

Step 3, forming an active layer 9 on the base substrate 6 after step 2;

Specifically, a layer of semiconductor material is deposited on the base substrate 6 after step 2 is completed, a layer of photoresist is coated on the semiconductor material, and a mask is used to expose the photoresist to make the photoresist form a photoresist The unreserved area and the photoresist reserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the active layer 9 is located, and the photoresist unreserved area corresponds to the area outside the pattern of the active layer 9; developing process, The photoresist in the area where the photoresist is not retained is completely removed, and the thickness of the photoresist in the area where the photoresist is retained remains unchanged; the semiconductor material in the area where the photoresist is not retained is completely etched away by an etching process to form an active layer 9 pattern, strip the remaining photoresist.

Step 4, forming patterns of data lines, source electrodes 10 and drain electrodes 11 on the base substrate 6 after step 3;

Specifically, a layer with a thickness of about The source and drain metal layers can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The source-drain metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the source-drain metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area Corresponding to the area where the pattern of source electrode 10, drain electrode 11 and data line is located, the unretained area of photoresist corresponds to the area other than the above-mentioned pattern; carry out development treatment, the photoresist in the unreserved area of photoresist is completely removed, and the photoresist is completely removed. The photoresist thickness in the resist reserved area remains unchanged; the source and drain metal layers in the photoresist unreserved area are completely etched away by an etching process, and the remaining photoresist is stripped to form the drain electrode 11, the source electrode 10 and the data Wire.

Step 5, forming a passivation layer 13 including pixel electrode via holes on the base substrate 6 after completing step 4;

Specifically, magnetron sputtering, thermal evaporation, PECVD or other film-forming methods can be used to deposit a thickness of For the passivation layer, the passivation layer can be selected from oxide, nitride or oxynitride compound, specifically, the material of the passivation layer can be SiNx, SiOx or Si(ON)x, and the passivation layer can also use Al ₂ O ₃ . The passivation layer can be a single-layer structure, or a two-layer structure composed of silicon nitride and silicon oxide. Wherein, the reaction gas corresponding to silicon oxide can be SiH ₄ , N ₂ O; the corresponding gas of nitride or oxynitride compound can be SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ . A layer of photoresist is coated on the passivation layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the passivation layer 13 is located, the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; the photoresist in the unreserved area of photoresist is completely removed, and the photoresist in the unreserved area of photoresist is completely removed. The thickness of the glue remains unchanged; the passivation layer in the region where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form the pattern of the passivation layer 13 .

Step 6, forming the pattern of the pixel electrode 14 on the base substrate 6 after completing the step 5;

Specifically, deposit a thickness of about The transparent conductive layer, the transparent conductive layer can be ITO, IZO or other transparent metal oxides, a layer of photoresist is coated on the transparent conductive layer, and a mask is used to expose the photoresist to make the photoresist form The photoresist unreserved area and the photoresist reserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the pixel electrode 14 is located, and the photoresist unreserved area corresponds to the area other than the above-mentioned pattern; The photoresist in the area where the glue is not retained is completely removed, and the thickness of the photoresist in the area where the photoresist is retained remains unchanged; the transparent conductive layer film in the area where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped. The resist forms the pattern of the pixel electrode 14, and the pixel electrode 14 is connected to the drain electrode 11 through the pixel electrode via hole.

Step 7, forming a pattern of a black matrix 15 on the base substrate 6 after step 6 has been completed.

Specifically, taking metal materials as the material of the black matrix as an example, a black matrix film is deposited on the base substrate 6 after step 6, and then a layer of photoresist is coated thereon, and a mask is used to expose the photoresist, Develop to form a photoresist reserved area and a photoresist removed area, wherein the photoresist reserved area corresponds to the area where the pattern of the black matrix 15 is located, and then the exposed black matrix film is etched, and finally the photoresist stripping process is performed The remaining photoresist is stripped to form the pattern of the black matrix 15 . If the material of the black matrix is photosensitive resin, the use of photoresist can be omitted by taking advantage of its photosensitive properties, and the pattern of the black matrix 15 can be obtained by directly exposing and developing.

After the above steps 1-8, the array substrate as shown in FIG. 3 can be fabricated. Further, spacers can also be fabricated on the black matrix 15 of the array substrate.

In this embodiment, since the color filter unit and the black matrix are all made on the array substrate, the problem that the black matrix needs to be made wider and the transmittance decreases due to the alignment deviation between the array substrate and the color filter substrate is avoided, and the The transmittance of the display panel can reduce the power consumption of the display device; and since there is no need to make a black matrix on the color filter substrate, the level difference on the color filter substrate can be reduced; in addition, the color filter unit can also serve as a grid on the array substrate. The insulating layer can reduce the number of patterning processes required for manufacturing the array substrate, shorten the manufacturing time of the array substrate, and reduce the manufacturing cost of the array substrate.

Embodiment two

The array substrate in this embodiment is an array substrate in TN mode, and the method for manufacturing the array substrate in this embodiment specifically includes the following steps:

Step 1, providing a base substrate 6, forming patterns of gate electrodes 7 and gate lines on the base substrate 6;

Wherein, the base substrate 6 may be a glass substrate or a quartz substrate. Specifically, sputtering or thermal evaporation can be used to deposit a thickness of about The gate metal layer, the gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the gate metal layer can be single-layer structure or multi-layer Structure, multi-layer structure such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the gate metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the grid line and the gate electrode 7 is located, the unretained area of photoresist corresponds to the area outside the above-mentioned pattern; the development process is carried out, and the photoresist in the unreserved area of photoresist is completely removed, and the area of photoresist reserved area is completely removed. The thickness of the photoresist remains unchanged; the gate metal film in the area not retained by the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form the pattern of the gate line and the gate electrode 7 .

Step 2, forming a gate insulating layer 8 on the base substrate 6 after completing step 1;

Specifically, a plasma-enhanced chemical vapor deposition (PECVD) method can be used to deposit a thickness of The gate insulating layer 8 can be selected from oxide, nitride or oxynitride compound, and the corresponding reaction gas is SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ .

Step 3, forming an active layer 9 on the base substrate 6 after step 2;

Specifically, a layer of semiconductor material is deposited on the base substrate 6 after step 2 is completed, a layer of photoresist is coated on the semiconductor material, and a mask is used to expose the photoresist to make the photoresist form a photoresist An unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the active layer 9 is located, and the unreserved area of the photoresist corresponds to an area other than the pattern of the active layer 9; developing process, The photoresist in the area where the photoresist is not retained is completely removed, and the thickness of the photoresist in the area where the photoresist is retained remains unchanged; the semiconductor material in the area where the photoresist is not retained is completely etched away by an etching process to form an active layer 9 pattern, strip the remaining photoresist.

Step 4, forming patterns of data lines, source electrodes 10 and drain electrodes 11 on the base substrate 6 after step 3;

Specifically, a layer with a thickness of about The source and drain metal layers can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The source-drain metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the source-drain metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area Corresponding to the area where the pattern of source electrode 10, drain electrode 11 and data line is located, the unretained area of photoresist corresponds to the area other than the above-mentioned pattern; carry out development treatment, the photoresist in the unreserved area of photoresist is completely removed, and the photoresist is completely removed. The photoresist thickness in the resist reserved area remains unchanged; the source and drain metal layers in the photoresist unreserved area are completely etched away by an etching process, and the remaining photoresist is stripped to form the drain electrode 11, the source electrode 10 and the data Wire.

Step 5, forming a passivation layer including pixel electrode via holes on the base substrate 6 after step 4, the passivation layer is composed of a black matrix 15 and a color filter unit 12;

Specifically, black photosensitive resin can be coated on the base substrate 6 after step 4, exposed and developed to obtain the pattern of the black matrix 15 . Then coat the colored photoresist on the base substrate 6, the coating method of the colored photoresist can adopt the mode of spin coating; The reserved area and the removed area, wherein the colored photoresist in the reserved area corresponds to form the color filter unit 12 , and the colored photoresist in the removed area is completely removed.

Step 6, forming the pattern of the pixel electrode 14 on the base substrate 6 after the step 5 is completed.

Specifically, deposit a thickness of about The transparent conductive layer, the transparent conductive layer can be ITO, IZO or other transparent metal oxides, a layer of photoresist is coated on the transparent conductive layer, and a mask is used to expose the photoresist to make the photoresist form The photoresist unreserved area and the photoresist reserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the pixel electrode 14 is located, and the photoresist unreserved area corresponds to the area other than the above-mentioned pattern; The photoresist in the area where the glue is not retained is completely removed, and the thickness of the photoresist in the area where the photoresist is retained remains unchanged; the transparent conductive layer film in the area where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped. The resist forms the pattern of the pixel electrode 14, and the pixel electrode 14 is connected to the drain electrode 11 through the pixel electrode via hole.

After the above steps 1-6, the array substrate as shown in FIG. 4 can be fabricated. Further, spacers can also be fabricated on the black matrix 15 of the array substrate.

In this embodiment, since the color filter unit and the black matrix are all made on the array substrate, the problem that the black matrix needs to be made wider and the transmittance decreases due to the alignment deviation between the array substrate and the color filter substrate is avoided, and the The transmittance of the display panel reduces the power consumption of the display device; and since there is no need to make a black matrix on the color filter substrate, the level difference on the color filter substrate can be reduced; in addition, the color filter unit and the black matrix can also serve as an array substrate The passivation layer on the substrate can reduce the number of patterning processes required for manufacturing the array substrate, shorten the manufacturing time of the array substrate, and reduce the manufacturing cost of the array substrate.

Embodiment Three

The array substrate in this embodiment is an array substrate in ADS (Advanced Super Dimension Switch) mode, and the manufacturing method of the array substrate in this embodiment specifically includes the following steps:

Step 1, providing a base substrate, forming patterns of gate electrodes and gate lines on the base substrate;

Wherein, the base substrate may be a glass substrate or a quartz substrate. Specifically, sputtering or thermal evaporation can be used to deposit a thickness of about The gate metal layer, the gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the gate metal layer can be single-layer structure or multi-layer Structure, multi-layer structure such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the gate metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the grid line and the gate electrode is located, the unreserved area of the photoresist corresponds to the area outside the above-mentioned figure; the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist in the unreserved area of the photoresist is completely removed. The thickness of the resist remains unchanged; the gate metal film in the area where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form the pattern of the gate line and the gate electrode.

Step 2, forming a gate insulating layer on the base substrate after completing step 1;

Specifically, a color photoresist can be coated on the base substrate after step 1, and the color photoresist can be coated by spin coating to form a gate insulating layer, and the gate insulating layer includes a plurality of color filter units .

Step 3, forming the pattern of the common electrode on the base substrate after step 2;

Specifically, on the base substrate that has completed step 2, deposit a thickness of about The transparent conductive layer, the transparent conductive layer can be ITO, IZO or other transparent metal oxides, a layer of photoresist is coated on the transparent conductive layer, and a mask is used to expose the photoresist to make the photoresist form The photoresist unreserved area and the photoresist reserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the common electrode is located, and the photoresist unreserved area corresponds to the area other than the above-mentioned graphics; The photoresist in the unreserved area is completely removed, and the thickness of the photoresist in the photoresist reserved area remains unchanged; the transparent conductive layer film in the unreserved area of the photoresist is completely etched away by an etching process, and the remaining photoresist is peeled off. Glue to form the pattern of the common electrode.

Step 4, forming an intermediate insulating layer including a first via hole on the base substrate after step 3;

Specifically, a plasma-enhanced chemical vapor deposition (PECVD) method can be used to deposit a thickness of The intermediate insulating layer can be oxide, nitride or oxynitride compound, and the corresponding reaction gas is SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ . Coat a layer of photoresist on the intermediate insulating layer, and use a mask to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the interlayer insulating layer is located, the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; after developing treatment, the photoresist in the unreserved area of photoresist is completely removed, and the photoresist in the unreserved area of photoresist is completely removed. The thickness remains unchanged; the gate insulating layer in the region where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of an intermediate insulating layer, which includes a first via hole.

Step 5, forming an active layer on the base substrate after completing step 4;

Specifically, a layer of semiconductor material is deposited on the base substrate of step 4, a layer of photoresist is coated on the semiconductor material, and a mask plate is used to expose the photoresist to make the photoresist form a photoresist layer. Reserved area and photoresist reserved area, wherein, the photoresist reserved area corresponds to the area where the pattern of the active layer is located, and the unreserved area of photoresist corresponds to the area outside the pattern of the active layer; The photoresist in the unreserved area is completely removed, and the thickness of the photoresist in the photoresist reserved area remains unchanged; the semiconductor material in the unreserved area of the photoresist is completely etched away by an etching process to form the pattern of the active layer. Strip remaining photoresist.

Step 6, forming patterns of common electrode lines, data lines, source electrodes and drain electrodes on the base substrate after step 5;

Specifically, a layer with a thickness of about The source and drain metal layers can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The source-drain metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the source-drain metal layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area Corresponding to the area where the pattern of the common electrode line, data line, source electrode and drain electrode is located, the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; the photoresist in the unreserved area of photoresist is completely removed by developing treatment , the thickness of the photoresist in the photoresist reserved area remains unchanged; the source and drain metal layer in the photoresist unreserved area is completely etched away by the etching process, and the remaining photoresist is stripped to form common electrode lines, data lines, The source electrode, the drain electrode, and the common electrode line are connected to the common electrode through the first via hole penetrating through the intermediate insulating layer.

Step 7, forming a passivation layer including a second via hole on the base substrate after step 6;

Specifically, magnetron sputtering, thermal evaporation, PECVD or other film forming methods can be used to deposit a thickness of For the passivation layer, the passivation layer can be selected from oxide, nitride or oxynitride compound, specifically, the material of the passivation layer can be SiNx, SiOx or Si(ON)x, and the passivation layer can also use Al ₂ O ₃ . The passivation layer can be a single-layer structure, or a two-layer structure composed of silicon nitride and silicon oxide. Wherein, the reaction gas corresponding to silicon oxide can be SiH ₄ , N ₂ O; the corresponding gas of nitride or oxynitride compound can be SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ . A layer of photoresist is coated on the passivation layer, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to In the area where the pattern of the passivation layer is located, the unreserved area of photoresist corresponds to the area other than the above-mentioned figure; after developing, the photoresist in the unreserved area of photoresist is completely removed, and the photoresist in the unreserved area of photoresist is completely removed. The thickness remains unchanged; the passivation layer in the region where the photoresist is not retained is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the passivation layer. The passivation layer includes a second via hole.

Step 8, forming the pattern of the pixel electrode on the base substrate after step 7;

Specifically, deposit thickness of about The transparent conductive layer, the transparent conductive layer can be ITO, IZO or other transparent metal oxides, a layer of photoresist is coated on the transparent conductive layer, and a mask is used to expose the photoresist to make the photoresist form The photoresist unreserved area and the photoresist reserved area, wherein the photoresist reserved area corresponds to the region where the pattern of the pixel electrode is located, and the photoresist unreserved area corresponds to the area other than the above-mentioned pattern; The photoresist in the unreserved area is completely removed, and the thickness of the photoresist in the photoresist reserved area remains unchanged; the transparent conductive layer film in the unreserved area of the photoresist is completely etched away by an etching process, and the remaining photoresist is peeled off. glue to form the pattern of the pixel electrode, and the pixel electrode is connected to the drain electrode through the second via hole penetrating the passivation layer.

Step 9, forming a black matrix pattern on the base substrate after step 8 has been completed.

Specifically, taking metal materials as the material of the black matrix as an example, a black matrix film is deposited on the base substrate that has completed step 8, and then a layer of photoresist is coated on it, and a mask is used to expose and develop the photoresist , forming a photoresist reserved area and a photoresist removed area, wherein the photoresist reserved area corresponds to the area where the pattern of the black matrix is located, and then the exposed black matrix film is etched, and finally the remaining photoresist stripping process is carried out The photoresist is stripped to form the pattern of the black matrix. If the material of the black matrix is photosensitive resin, the use of photoresist can be omitted by taking advantage of its photosensitive properties, and the pattern of the black matrix can be obtained by directly exposing and developing.

Further, the spacers can also be made on the black matrix of the array substrate.

In this embodiment, since the color filter unit and the black matrix are all made on the array substrate, the problem that the black matrix needs to be made wider and the transmittance decreases due to the alignment deviation between the array substrate and the color filter substrate is avoided, and the The transmittance of the display panel can reduce the power consumption of the display device; and since there is no need to make a black matrix on the color filter substrate, the level difference on the color filter substrate can be reduced; in addition, the color filter unit can also serve as a grid on the array substrate. The insulating layer can reduce the number of patterning processes required for manufacturing the array substrate, shorten the manufacturing time of the array substrate, and reduce the manufacturing cost of the array substrate.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (13)

1. An array substrate, comprising a base substrate and a conductive metal pattern formed on the base substrate, characterized in that, the array substrate also includes: color filter layer; A black matrix capable of shielding the conductive metal pattern. 2. The array substrate according to claim 1, wherein the conductive pattern includes a gate electrode and a gate line, and the color filter layer is a gate insulating layer covering the gate electrode and the gate line. 3. The array substrate according to claim 1, wherein the conductive pattern includes source electrodes, drain electrodes and data lines, and the color filter layer is a blunt layer covering the source electrodes, drain electrodes and data lines. layers. 4. The array substrate according to claim 3, wherein the black matrix is located on the color filter layer. 5. The array substrate according to claim 1, wherein the conductive pattern includes a source electrode, a drain electrode and a data line, and the color filter layer and the black matrix cover the source electrode and the drain electrode and the passivation layer of the data line. 6. The array substrate according to claim 4 or 5, further comprising: spacers formed on the black matrix. 7. A display device, comprising the array substrate according to any one of claims 1-6. 8. A method for manufacturing an array substrate, comprising forming a conductive metal pattern on a base substrate, characterized in that the method further includes: Form a color filter layer; A black matrix capable of shielding the conductive metal pattern is formed. 9. The method for manufacturing an array substrate according to claim 8, wherein forming the conductive metal pattern comprises: forming gate electrodes and gate lines; Forming the color filter layer is specifically as follows: A gate insulating layer covering the gate electrodes and gate lines is formed, and a color filter material is used for the gate insulating layer. 10. The manufacturing method of the array substrate according to claim 8, wherein forming the conductive metal pattern comprises: Forming source electrodes, drain electrodes and data lines; Forming the color filter layer is specifically as follows: A passivation layer covering the source electrode, the drain electrode and the data line is formed, and the passivation layer adopts a color filter material. 11. The method for manufacturing an array substrate according to claim 10, wherein forming the black matrix is specifically as follows: The black matrix is formed on the color filter layer. 12. The manufacturing method of the array substrate according to claim 8, wherein forming the conductive metal pattern comprises: Forming source electrodes, drain electrodes and data lines; Forming the color filter layer and the black matrix includes: A passivation layer covering the source electrode, the drain electrode and the data line is formed, the part of the passivation layer is the black matrix, and the other part of the passivation layer is made of color filter material. 13. The method for manufacturing an array substrate according to claim 11 or 12, further comprising: Spacers are formed on the black matrix.