CN104348357B - Control circuit for reducing touch current of power converter and operation method thereof - Google Patents

Abstract

The invention discloses a control circuit for reducing touch current of a power converter and an operation method thereof. The control circuit comprises an auxiliary pin, a zero-cross signal generator, a frequency limiting signal generator and a grid signal generator. The auxiliary pin receives a voltage generated by an auxiliary winding of the power converter; the zero-cross signal generator generates a zero-cross signal according to the voltage generated by the auxiliary winding and a first reference voltage; the frequency limiting signal generator generates a frequency limiting signal according to a grid control signal, a burst mode signal and the voltage generated by the auxiliary winding; the grid signal generator generates the grid control signal to a power switch of the power converter according to the frequency limiting signal and the zero-crossing signal. Therefore, the invention can slow down the voltage drop on an input capacitor when the power converter leaves a burst mode so as to reduce the touch current.

Description

Control circuit for reducing touch current of power converter and method of operation thereof

technical field

The present invention relates to a control circuit for reducing the touch current of a power converter and its operation method, especially a control circuit for reducing the voltage on the input capacitor due to the rapid drop of the voltage on the input capacitor when the power converter leaves the burst mode. A control circuit for the generated touch current and a method of operation thereof.

Background technique

In the prior art, when a power factor correction (PFC) power converter operates at a high output voltage and a light load, the power converter enters a burst mode. After the power converter enters the burst mode, the power switch of the power converter is switched according to the gate control signal corresponding to the burst mode. At this time, since the power consumption of the power converter is very small, the voltage on the input capacitor of the power converter will stay at the voltage when the power switch stops switching. When the power converter leaves the burst mode, the power switch starts to switch according to the gate control signal corresponding to the quasi resonant mode. At this time, if the input voltage is less than the voltage on the input capacitor, the diode in the bridge rectifier of the power converter will not conduct, causing the input capacitor to provide power to the inductor of the power converter. Thus, the voltage across the input capacitor will drop. At this time, because the power converter is operating at the highest frequency, the voltage on the input capacitor will drop rapidly, causing the touch current to exceed safety regulations.

In addition, the prior art can only adjust the parameters of the power converter to solve the problem of high touch current, so the prior art can only partially solve the problem of high touch current. Therefore, designers of power converters must find a new solution to replace the existing technology.

Contents of the invention

An embodiment of the invention discloses a control circuit for reducing touch current of a power converter, wherein the power converter is a power factor correction (PFC) power converter. The control circuit includes an auxiliary pin, a zero-crossing signal generator, a frequency-limiting signal generator and a gate signal generator. The auxiliary pin is used to receive a voltage generated by an auxiliary winding of the power converter; the zero-crossing signal generator is used to generate a zero according to the voltage generated by the auxiliary winding and a first reference voltage crossover signal; the frequency limiting signal generator is used to generate a frequency limiting signal according to a grid control signal, a burst mode signal and the voltage generated by the auxiliary winding, wherein the frequency limiting signal is used to limit the grid The gate control signal is at a predetermined frequency; the gate signal generator is used to generate the gate control signal to a power switch of the power converter according to the frequency-limiting signal and the zero-crossing signal.

Another embodiment of the present invention discloses an operation method of a control circuit for reducing touch current of a power converter. The method includes receiving a voltage generated by an auxiliary winding of the power converter; generating a zero-crossing signal according to the voltage generated by the auxiliary winding and a first reference voltage; receiving information about an output voltage of the power converter a feedback voltage; according to a gate control signal, a burst mode reference voltage, the zero-crossing signal, the feedback voltage and the voltage generated by the auxiliary winding, the grid control signal is generated to a side of the power converter power switch.

The invention discloses a control circuit for reducing touch current of a power converter and an operation method thereof. In the control circuit and the operation method, when a power converter leaves a burst mode, a frequency limiting signal generator is used to generate a frequency limiting signal to limit the grid according to a grid control signal and a voltage generated by an auxiliary winding. The pole control signal is at a predetermined frequency until the frequency-limiting signal generator does not generate the frequency-limiting signal. When the frequency-limiting signal generator does not generate the frequency-limiting signal, a gate signal generator can generate the gate control signal corresponding to a quasi-resonant mode to a gate control signal of the power converter according to a zero-crossing signal power switch. In this way, compared with the prior art, the present invention can slow down the voltage drop on an input capacitor when the power converter leaves the burst mode, so as to reduce a touch current. In addition, since the frequency limiting mechanism provided by the present invention starts to function after the power converter leaves the burst mode, the present invention will not reduce the power factor value of the power converter.

Description of drawings

FIG. 1 is a schematic diagram illustrating a control circuit for reducing touch current of a power converter according to an embodiment of the present invention.

2 and 3 are schematic diagrams illustrating that the gate signal generator generates a gate control signal of a predetermined frequency and a gate control signal of a quasi-resonant mode according to the frequency-limiting signal, the zero-crossing signal, and the zero-crossing signal, respectively.

FIG. 4 is a schematic diagram illustrating the relationship between the frequency of the gate control signal and the compensation voltage.

5A and 5B are flowcharts illustrating an operation method of a control circuit for reducing touch current of a power converter according to another embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100 power converter

102 inductance

104 power switch

106 bridge rectifier

108 resistors

200 control circuit

202 Auxiliary pin

203 Zero Crossing Signal Generator

204 frequency limit signal generator

206 gate signal generator

208 Feedback pin

210 compensation voltage generation unit

212 burst mode signal generation module

216 Gate pins

218 current pins

220 Compensation pin

2042 counter

2044 sample and hold unit

2046 Second comparator

2048 frequency limiting unit

2102 Transconductance Amplifier

2104 First Resistor

2106 First Capacitor

2122 First Comparator

2124 signal generation unit

AUX auxiliary winding

BS burst mode signal

CIN input capacitance

CS gate control signal

FCS first comparison signal

IS current

I1 first current

LS limited frequency signal

SCS second comparison signal

V1 first voltage

V2 second voltage

VOUT output voltage

VFB feedback voltage

VCOMP compensation voltage

VA voltage

VAC power

VD detection voltage

VREF1 First reference voltage

VREF2 Second reference voltage

VREF3 Third reference voltage

VREFB Burst mode reference voltage

ZCS Zero Crossing Signal

500-530 steps

detailed description

Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a control circuit 200 applied to a power converter 100 according to an embodiment of the present invention, wherein the power converter 100 is a power factor correction (Power factor Correction, PFC) power converter. device, and is also a boost (boost) power converter. The control circuit 200 includes an auxiliary pin 202, a zero-crossing signal generator 203, a frequency-limiting signal generator 204 and a gate signal generator 206, wherein the auxiliary pin 202 is used to receive a power converter 100 A voltage VA generated by the auxiliary winding AUX; the zero-crossing signal generator 203 is used to generate a zero-crossing signal ZCS according to the voltage VA generated by the auxiliary winding AUX and a first reference voltage VREF1, wherein the first reference voltage VREF1 is approximately 0.2V to 0.3V. As shown in FIG. 1 , the zero-crossing signal generator 203 is a hysteresis comparator. But the present invention is not limited to the zero-crossing signal generator 203 being a hysteresis comparator. As shown in FIG. 1 , the control circuit 200 further includes a feedback pin 208 , a compensation voltage generating unit 210 , a burst mode signal generating module 212 , a gate pin 216 and a current pin 218 . In addition, as shown in FIG. 1 , the induction directions of the auxiliary winding AUX and the inductor 102 coupled to the power converter 100 are opposite.

As shown in FIG. 1 , the feedback pin 208 is used to receive a feedback voltage VFB related to the output voltage VOUT of the power converter 100, wherein the feedback voltage VFB is related to the load of the power converter 100, that is, the feedback The voltage VFB will vary with the load of the power converter 100 . The compensation voltage generating unit 210 is used for generating a compensation voltage VCOMP according to the feedback voltage VFB and a second reference voltage VREF2. The compensation voltage generating unit 210 includes a transconductance amplifier 2102 , a first resistor 2104 and a first capacitor 2106 . The transconductance amplifier 2102 is used to generate a first current I1 according to the feedback voltage VFB and the second reference voltage VREF2 . The first resistor 2104 and the first capacitor 2106 are used to generate the compensation voltage VCOMP according to the first current I1. In addition, the compensation voltage generation unit 210 shown in FIG. 1 is only used to illustrate the control circuit 200 , that is, the present invention is not limited to the compensation voltage generation unit 210 shown in FIG. 1 . In addition, the power converter 100 further includes a compensation pin 220 coupled to the output end of the compensation voltage generating unit 210 .

As shown in FIG. 1 , the burst mode signal generating module 212 includes a first comparator 2122 and a signal generating unit 2124 . The first comparator 2122 is used to generate a first comparison signal FCS according to the compensation voltage VCOMP and a burst mode reference voltage VREFB, that is, when the compensation voltage VCOMP is smaller than the burst mode reference voltage VREFB, the first comparator 2122 generates a first Compare signal FCS. When the signal generation unit 2124 receives the first comparison signal FCS, the signal generation unit 2124 can generate a burst mode signal BS to the gate signal generator 206 according to the first comparison signal FCS (that is, the power converter 100 enters a burst mode). model). When the gate signal generator 206 receives the burst mode signal BS, the gate signal generator 206 can generate a gate control signal CS corresponding to the burst mode according to the burst mode signal BS and the zero-crossing signal ZCS and pass the gate The pole pin 216 is transmitted to a power switch 104 of the power converter 100 . The power switch 104 can be turned on according to the gate control signal CS corresponding to the burst mode.

As shown in FIG. 1 , the frequency-limiting signal generator 204 includes a counter 2042 , a sample-and-hold unit 2044 , a second comparator 2046 and a frequency-limiting unit 2048 . The counter 2042 is used to receive the gate control signal CS, wherein when the signal generating unit 2124 stops generating the burst mode signal BS (that is, the power converter 100 leaves the burst mode), the counter 2042 starts counting the gate control signal CS, and according to the gate The pole control signal CS generates a first number FN and a second number SN, wherein the first number FN is smaller than the second number SN. For example, the first number FN is 1 and the second number SN is 3. But the present invention is not limited to the fact that the first number FN is 1 and the second number SN is 3. The sample and hold unit 2044 is used to store the first voltage V1 generated by the auxiliary winding AUX corresponding to the first number FN, and the second voltage V2 generated by the auxiliary winding AUX corresponding to the second number SN. The second comparator 2046 is used for generating a second comparison signal SCS when the second voltage V2 is greater than the first voltage V1. Because the induction directions of the auxiliary winding AUX and the inductor 102 are opposite, when the second voltage V2 is greater than the first voltage V1, the inductor 102 of the power converter 100 is powered by an input capacitor CIN of the power converter 100, that is, when the second voltage V2 is greater than the first voltage V1 When the second voltage V2 is greater than the first voltage V1 , the diode in the bridge rectifier 106 of the power converter 100 will not conduct, so the power VAC cannot provide power to the inductor 102 at this time. The frequency limiting unit 2048 is used for generating a frequency limiting signal LS to the gate signal generator 206 according to the second comparison signal SCS. The frequency limiting signal LS is used to limit the gate control signal CS generated by the gate signal generator 206 to a predetermined frequency (eg, 25 KHz), wherein the predetermined frequency is adjustable. In this way, after the power converter 100 leaves the burst mode, the frequency-limiting signal generator 204 first makes the gate signal generator 206 generate a gate control signal CS of a predetermined frequency to the power supply according to the frequency-limiting signal LS and the zero-crossing signal ZCS. The power switch 104 of the converter 100 . The power switch 104 can then be turned on according to the gate control signal CS of a predetermined frequency. In addition, after the frequency limiting unit 2048 generates the frequency limiting signal LS to the gate signal generator 206 according to the second comparison signal SCS, the counter 2042, the sample and hold unit 2044, the second comparator 2046 and the frequency limiting unit 2048 will repeat the above actions Until the second voltage V2 sampled by the sample and hold unit 2044 is smaller than the first voltage V1 sampled by the sample and hold unit 2044 .

As shown in FIG. 1, when the power converter 100 leaves the burst mode and the second voltage V2 is lower than the first voltage V1 (that is, the frequency limiting signal generator 204 does not generate the frequency limiting signal LS, and the power converter 100 enters a quasi-resonant mode ), the zero-crossing signal generator 203 is used to generate the zero-crossing signal ZCS to the gate signal generator 206 according to the voltage VA generated by the auxiliary winding AUX and the first reference voltage VREF1 . At this time, the gate signal generator 206 is used to generate the gate control signal CS corresponding to the quasi-resonant mode to the power switch 104 according to the zero-crossing signal ZCS. The power switch 104 can then be turned on according to the gate control signal CS corresponding to the quasi-resonant mode.

In addition, as shown in FIG. 1 , the current pin 218 is used to receive the detection voltage VD determined according to the current IS flowing through the power switch 104 and a resistor 108 . The gate signal generator 206 is also used to disable the gate control signal CS according to the detection voltage VD and a third reference voltage VREF3, that is, when the detection voltage VD is greater than the third reference voltage VREF3, the gate signal generator 206 disables the gate control signal CS to turn off the power switch 104 .

Please refer to FIG. 2, FIG. 3 and FIG. 4. FIG. 2 and FIG. 3 illustrate that the gate signal generator 206 generates a grid with a predetermined frequency according to the frequency-limiting signal LS, the zero-crossing signal ZCS, and the zero-crossing signal ZCS, respectively. 4 is a schematic diagram illustrating the relationship between the frequency of the gate control signal CS and the compensation voltage VCOMP. As shown in FIG. 2, at time T1, the power converter 100 leaves the burst mode, the frequency-limiting signal generator 204 generates a frequency-limiting signal LS to the gate signal generator 206, and the gate signal generator 206 generates a frequency-limiting signal LS according to the frequency-limiting signal LS and the zero-crossing signal ZCS to generate a gate control signal CS of a predetermined frequency. Then, at the third gate control signal CS (time T2), the second voltage V2 sampled by the sample and hold unit 2044 is smaller than the first voltage V1 sampled by the sample and hold unit 2044, so the second comparator 2046 does not generate the first voltage V1 The second comparison signal SCS causes the frequency limiting unit 2048 not to generate the frequency limiting signal LS to the gate signal generator 206 . Therefore, after the fourth gate control signal CS, the gate signal generator 206 generates a quasi-resonant gate control signal CS according to the zero-crossing signal ZCS. As shown in FIG. 3 , at time T1, the power converter 100 leaves the burst mode, the frequency-limiting signal generator 204 generates a frequency-limiting signal LS to the gate signal generator 206, and the gate signal generator 206 generates a frequency-limiting signal LS according to the frequency-limiting signal LS and the zero-crossing signal ZCS to generate a gate control signal CS of a predetermined frequency. Then, at the third gate control signal CS (time T2), the second voltage V2 sampled by the sample and hold unit 2044 is greater than the first voltage V1 sampled by the sample and hold unit 2044, so the second comparator 2046 generates the second The comparison signal SCS causes the frequency limiting unit 2048 to generate a frequency limiting signal LS to the gate signal generator 206 . Therefore, after the fourth gate control signal CS, the gate signal generator 206 generates a gate control signal CS with a predetermined frequency according to the frequency-limiting signal LS and the zero-crossing signal ZCS. After the gate signal generator 206 generates the gate control signal CS of a predetermined frequency according to the frequency-limiting signal LS and the zero-crossing signal ZCS, the counter 2042, the sample-and-hold unit 2044, the second comparator 2046 and the frequency-limiting unit 2048 repeat The above actions are performed until the second voltage V2 sampled by the sample and hold unit 2044 is smaller than the first voltage V1 sampled by the sample and hold unit 2044 (for example, time T3). Because at time T3 (the ninth gate control signal CS), the second voltage V2 sampled by the sample and hold unit 2044 is smaller than the first voltage V1 sampled by the sample and hold unit 2044, so the second comparator 2046 does not generate the second voltage V1. The comparison signal SCS causes the frequency limiting unit 2048 not to generate the frequency limiting signal LS to the gate signal generator 206 . Therefore, after the ninth gate control signal CS, the gate signal generator 206 generates the gate control signal CS in quasi-resonant mode according to the zero-crossing signal ZCS.

As shown in FIG. 4 , when the power converter 100 leaves the burst mode for a period of time, the frequency of the gate control signal CS is a predetermined frequency. Then, the gate signal generator 206 generates the gate control signal CS in the quasi-resonant mode according to the zero-crossing signal ZCS.

Please refer to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5A and Fig. 5B, Fig. 5A and Fig. 5B are another embodiment of the present invention illustrating a control circuit for reducing the touch current of the power converter Flowchart of the method of operation. The operation method of FIG. 5A and FIG. 5B is illustrated by using the power converter 100 and the control circuit 200 of FIG. 1 , and the detailed steps are as follows:

Step 500: start;

Step 501: the auxiliary pin 202 receives a voltage VA generated by the auxiliary winding AUX of the power converter 100;

Step 502: The zero-crossing signal generator 203 generates a zero-crossing signal ZCS according to the voltage VA generated by the auxiliary winding AUX and the first reference voltage VREF1;

Step 504: the feedback pin 208 receives a feedback voltage VFB related to the output voltage VOUT of the power converter 100;

Step 506: The compensation voltage generation unit 210 generates a compensation voltage VCOMP according to the feedback voltage VFB and the second reference voltage VREF2;

Step 508: Whether the compensation voltage VCOMP is greater than the burst mode reference voltage VREFB; if yes, go to step 510; if not, go to step 526;

Step 510: the burst mode signal generating module 212 stops generating a burst mode signal BS;

Step 512: the counter 2042 counts a gate control signal CS, and generates a first digital FN and a second digital SN according to the gate control signal CS;

Step 514: the sample and hold unit 2044 stores a first voltage V1 corresponding to the first digital FN generated by the auxiliary winding AUX, and a second voltage V2 corresponding to the second digital SN generated by the auxiliary winding AUX;

Step 516: Whether the second voltage V2 is greater than the first voltage V1; if yes, go to step 518; if not, go to step 524;

Step 518: the second comparator 2046 generates a second comparison signal SCS;

Step 520: the frequency limiting unit 2048 generates a frequency limiting signal LS to the gate signal generator 206 according to the second comparison signal SCS;

Step 522: the gate signal generator 206 generates a gate control signal CS according to the frequency-limiting signal LS and the zero-crossing signal ZCS;

Step 523: When the current IS flowing through the power switch 104 and the detection voltage VD determined by the resistor 108 is greater than the third reference voltage VREF3, the gate signal generator 206 disables the gate control signal CS, and jumps back to step 516;

Step 524: the gate signal generator 206 generates a gate control signal CS according to the zero-crossing signal ZCS;

Step 525: When the current IS flowing through the power switch 104 and the detection voltage VD determined by the resistor 108 is greater than the third reference voltage VREF3, the gate signal generator 206 disables the gate control signal CS, and jumps back to step 508;

Step 526: the burst mode signal generating module 212 generates the burst mode signal BS;

Step 528: the gate signal generator 206 generates a gate control signal CS according to the burst mode signal BS and the zero-crossing signal ZCS;

Step 530 : When the current IS flowing through the power switch 104 and the detection voltage VD determined by the resistor 108 is greater than the third reference voltage VREF3 , the gate signal generator 206 disables the gate control signal CS, and jumps back to step 508 .

In step 501 , as shown in FIG. 1 , the auxiliary pin 202 receives the voltage VA generated by the auxiliary winding AUX, wherein the induction directions of the auxiliary winding AUX and the inductor 102 coupled to the power converter 100 are opposite. In step 504, as shown in FIG. 1 , the feedback pin 208 is used to receive the feedback voltage VFB related to the output voltage VOUT of the power converter 100 , wherein the feedback voltage VFB is related to the load of the power converter 100 , That is, the feedback voltage VFB will vary with the load of the power converter 100 . In step 506 , as shown in FIG. 1 , the transconductance amplifier 2102 in the compensation voltage generating unit 210 generates a first current I1 according to the feedback voltage VFB and the second reference voltage VREF2 . The first resistor 2104 and the first capacitor 2106 in the compensation voltage generating unit 210 are used to generate the compensation voltage VCOMP according to the first current I1.

In step 526, as shown in FIG. 1, the first comparator 2122 is used to generate a first comparison signal FCS according to the compensation voltage VCOMP and the burst mode reference voltage VREFB, that is, when the compensation voltage VCOMP is smaller than the burst mode reference voltage VREFB , the first comparator 2122 generates a first comparison signal FCS. When the signal generation unit 2124 receives the first comparison signal FCS, the signal generation unit 2124 can generate a burst mode signal BS to the gate signal generator 206 according to the first comparison signal FCS (that is, the power converter 100 enters a burst mode ). In step 528, when the gate signal generator 206 receives the burst mode signal BS, the gate signal generator 206 can generate a gate control signal corresponding to the burst mode according to the burst mode signal BS and the zero-crossing signal ZCS CS is transmitted to the power switch 104 of the power converter 100 through the gate pin 216 . The power switch 104 can be turned on according to the gate control signal CS corresponding to the burst mode.

In step 510, as shown in FIG. 1, when the compensation voltage VCOMP is greater than the burst mode reference voltage VREFB, the first comparator 2122 does not generate the first comparison signal FCS, causing the signal generation unit 2124 to stop generating the burst mode signal BS (that is, power converter 100 leaves burst mode). In step 512, when the signal generating unit 2124 stops generating the burst mode signal BS, the counter 2042 starts counting the gate control signal CS, and generates the first digital FN and the second digital SN according to the gate control signal CS, wherein the first The number FN is smaller than the second number SN. For example, the first number FN is 1 and the second number SN is 3. But the present invention is not limited to the fact that the first number FN is 1 and the second number SN is 3. In step 518, the second comparator 2046 is used to generate a second comparison signal SCS when the second voltage V2 is greater than the first voltage V1. Because the induction directions of the auxiliary winding AUX and the inductor 102 are opposite, when the second voltage V2 is greater than the first voltage V1, the inductor 102 of the power converter 100 is powered by an input capacitor CIN of the power converter 100, that is, when the second voltage V2 is greater than the first voltage V1 When the second voltage V2 is greater than the first voltage V1 , the diode in the bridge rectifier 106 of the power converter 100 will not conduct, so the power supply VAC cannot provide power to the inductor 102 at this time. In step 520 , the frequency limiting signal LS is used to limit the gate control signal CS generated by the gate signal generator 206 to a predetermined frequency (for example, 25 KHz), wherein the predetermined frequency is adjustable. In this way, in step 522, after the power converter 100 leaves the burst mode, the frequency-limiting signal generator 204 will first enable the gate signal generator 206 to generate a gate signal of a predetermined frequency according to the frequency-limiting signal LS and the zero-crossing signal ZCS. The control signal CS is sent to the power switch 104 of the power converter 100 . The power switch 104 can then be turned on according to the gate control signal CS of a predetermined frequency. In addition, after the frequency limiting unit 2048 generates the frequency limiting signal LS to the gate signal generator 206 according to the second comparison signal SCS, the counter 2042, the sample and hold unit 2044, the second comparator 2046 and the frequency limiting unit 2048 will repeat the above actions Until the second voltage V2 sampled by the sample and hold unit 2044 is smaller than the first voltage V1 sampled by the sample and hold unit 2044 (as shown in FIG. 2 and FIG. 3 ).

In step 524, as shown in FIG. 1, when the power converter 100 leaves the burst mode and the second voltage V2 is less than the first voltage V1 (that is, the frequency limiting signal generator 204 does not generate the frequency limiting signal LS, and the power converter 100 When entering the quasi-resonant mode), the gate signal generator 206 is used to generate a gate control signal CS corresponding to the quasi-resonant mode to the power switch 104 according to the zero-crossing signal ZCS. The power switch 104 can then be turned on according to the gate control signal CS corresponding to the quasi-resonant mode.

In addition, in step 523 , step 525 and step 530 , as shown in FIG. 1 , the current pin 218 is used to receive the detection voltage VD determined according to the current IS flowing through the power switch 104 and the resistor 108 . When the detection voltage VD is greater than the third reference voltage VREF3 , the gate signal generator 206 disables the gate control signal CS to turn off the power switch 104 .

Therefore, in steps 510 to 523 , as shown in FIG. 4 , when the power converter 100 leaves the burst mode for a period of time, the frequency of the gate control signal CS is a predetermined frequency. Then, in step 524 , the gate signal generator 206 generates the gate control signal CS in the quasi-resonant mode according to the zero-crossing signal ZCS.

To sum up, the control circuit and its operation method for reducing the touch current of the power converter disclosed in the present invention are to use the frequency limiting signal generator according to the gate control signal and the auxiliary power converter when the power converter leaves the burst mode. The voltage generated by the winding generates a frequency-limiting signal to limit the gate control signal at a predetermined frequency until the frequency-limiting signal generator does not generate the frequency-limiting signal. When the frequency-limiting signal generator does not generate the frequency-limiting signal, the gate signal generator can generate a gate control signal corresponding to the quasi-resonant mode to the power switch of the power converter according to the zero-crossing signal. In this way, compared with the prior art, the present invention can slow down the voltage drop on the input capacitor when the power converter leaves the burst mode, so as to reduce the touch current. In addition, since the frequency limiting mechanism disclosed in the present invention starts to work after the power converter leaves the burst mode, the present invention will not reduce the power factor value of the power converter.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (15)

1. A control circuit for reducing the touch current of a power converter, wherein the power converter is a power factor corrected power converter, the control circuit comprising: an auxiliary pin for receiving a voltage generated by an auxiliary winding of the power converter; The control circuit is characterized by further comprising: a zero-crossing signal generator, used for generating a zero-crossing signal according to the voltage generated by the auxiliary winding and a first reference voltage; A frequency-limiting signal generator is used to generate a frequency-limiting signal according to a gate control signal, a burst mode signal and the voltage generated by the auxiliary winding, wherein the frequency-limiting signal is used to limit the gate control signal to a predetermined frequency; and A gate signal generator is used for generating the gate control signal to a power switch of the power converter according to the frequency limiting signal and the zero crossing signal. 2. The control circuit according to claim 1, further comprising: a feedback pin for receiving a feedback voltage related to the output voltage of the power converter, wherein the feedback voltage is related to a load coupled to the power converter; and A compensation voltage generating unit is used for generating a compensation voltage according to the feedback voltage and a second reference voltage. 3. The control circuit according to claim 2, wherein the compensation voltage generating unit comprises: a transconductance amplifier, used to generate a first current according to the feedback voltage and the second reference voltage; a first resistor; and A first capacitor, wherein the first resistor and the first capacitor are used to generate the compensation voltage according to the first current. 4. The control circuit according to claim 2, further comprising: A burst mode signal generating module, comprising: a first comparator, used for generating a first comparison signal according to the compensation voltage and a burst mode reference voltage; and a signal generating unit, used for generating the burst mode signal to the gate signal generator according to the first comparison signal; Wherein the gate signal generator is further used for generating the gate control signal to the power switch according to the burst mode signal and the zero crossing signal. 5. The control circuit according to claim 4, wherein the frequency-limiting signal generator comprises: a counter for receiving the gate control signal, wherein when the signal generating unit stops generating the burst mode signal, the counter counts the gate control signal, and generates a first number and a a second number, wherein the first number is less than the second number; a sample-and-hold unit for storing a first voltage corresponding to the first number generated by the auxiliary winding, and a second voltage corresponding to the second number generated by the auxiliary winding; a second comparator, used to generate a second comparison signal when the second voltage is greater than the first voltage; and A frequency limiting unit is used for generating the frequency limiting signal to the gate signal generator according to the second comparison signal. 6. The control circuit according to claim 1, wherein the gate signal generator is further used to generate the gate control signal to the power switch according to the zero-crossing signal. 7. The control circuit as claimed in claim 1, wherein the predetermined frequency is adjustable. 8. The control circuit according to claim 1, further comprising: A gate pin, wherein the gate control signal is transmitted to the power switch through the gate pin. 9. The control circuit according to claim 1, 4 or 6, further comprising: a current pin for receiving a detection voltage determined according to a current flowing through the power switch and a resistance; Wherein the gate signal generator is further used for disabling the gate control signal according to the detection voltage and a third reference voltage. 10. A method of operating a control circuit for reducing touch current of a power converter, the method comprising: receiving a voltage generated by an auxiliary winding of the power converter; The operating method is characterized in that it also includes: generating a zero-crossing signal according to the voltage generated by the auxiliary winding and a first reference voltage; receiving a feedback voltage related to the output voltage of the power converter; generating a compensation voltage according to the feedback voltage and a second reference voltage; When the compensation voltage is greater than a burst mode reference voltage and stops generating a burst mode signal, count a gate control signal, and generate a first number and a second number according to the gate control signal, wherein the first number a number is less than the second number; storing a first voltage generated by the auxiliary winding corresponding to the first number, and a second voltage generated by the auxiliary winding corresponding to the second number; generating a comparison signal according to whether the second voltage is greater than the first voltage; generating a frequency-limited signal to a gate signal generator according to the comparison signal; and generating the gate control signal to a power switch of the power converter according to the frequency limiting signal and the zero crossing signal; Wherein the frequency limiting signal is used to limit the gate control signal to a predetermined frequency. 11. The operating method according to claim 10, further comprising: When the second voltage is lower than the first voltage, the gate control signal is generated according to the zero-crossing signal. 12. The operating method according to claim 10, wherein the predetermined frequency is adjustable. 13. The operation method as claimed in claim 10, wherein the feedback voltage is related to a load coupled to the power converter. 14. A method of operating a control circuit to reduce touch current of a power converter, the method comprising: receiving a voltage generated by an auxiliary winding of the power converter; The operating method is characterized in that it also includes: generating a zero-crossing signal according to the voltage generated by the auxiliary winding and a first reference voltage; receiving a feedback voltage related to the output voltage of the power converter; generating a compensation voltage according to the feedback voltage and a second reference voltage; generating a burst mode signal when the compensation voltage is less than a burst mode reference voltage; and According to the burst mode signal and the zero-crossing signal, a gate control signal is generated to a power switch of the power converter. 15. The operating method according to claim 11 or 14, further comprising: receiving a detection voltage determined according to a current flowing through the power switch and a resistance; and The gate control signal is disabled according to the detection voltage and a third reference voltage.