CN104345487A - A display device and a driving method thereof - Google Patents

Abstract

The present invention relates to a display device and a driving method thereof. The display device includes: a display unit including a plurality of pixels, a plurality of scanning lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels; a scanning driving unit sequentially applying a grid to the plurality of scanning lines Pole conduction voltage; the data drive unit, in response to the gate conduction voltage, applies data signals to the plurality of data lines; the signal control unit generates image data signals according to the input image signals and synchronous signals, thereby converting them to forwarding to the above-mentioned data drive unit; and a unit information providing unit that provides unit information for indicating a position on a manufacturing process of a display substrate including the plurality of pixels to the above-mentioned signal control unit, and the above-mentioned signal control unit includes a plurality of units The standard data selects unit standard data corresponding to the unit information from the plurality of unit standard data, and generates the image data signal based on the selected unit standard data.

Description

Display device and driving method thereof

technical field

The present invention relates to a display device and a driving method thereof, and more specifically, to a display device and a driving method thereof capable of improving dispersion of production processes.

Background technique

As one of the representatives of display devices, a liquid crystal display (liquid crystal display, LCD) includes a thin film transistor display panel with pixel electrodes, a common electrode display panel with common electrodes, and a dielectric layer between the two display panels. Anisotropic (dielectric anisotropy) liquid crystal layer. The pixel electrodes are arranged in a matrix form and connected to switching elements such as thin film transistors (thin film transistor, TFT), so that data voltages are applied row by row. The common electrode is formed on the entire surface of the common electrode display panel, and a common voltage is applied thereto. From the circuit point of view, the pixel electrode, the common electrode and the liquid crystal layer in between form a liquid crystal capacitor, and the liquid crystal capacitor and the switching elements connected to it together become the basic unit of the pixel. In such a liquid crystal display device, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

Generally speaking, the manufacturing process of a TFT display panel includes cleaning, deposition, photolithography, etching, PR removal (photo resist strip), inspection and other unit processes. Such unit steps are repeated to form pixel electrodes, thin film transistors, and the like of the thin film transistor display panel. In the manufacturing process of such a thin film transistor display panel, the inherent gamma characteristics of the liquid crystal display device are determined.

In particular, the manufacturing process of the thin film transistor display panel is formed by dividing one large substrate to form a plurality of thin film transistor display panels. At this time, due to limitations of equipment, it is not possible to irradiate the entire large substrate with a fixed amount of exposure. That is, the exposure amount deteriorates between thin film transistor display panels fabricated on one large substrate. The variation in exposure amount leads to variation in image quality characteristics among liquid crystal display devices.

Contents of the invention

The technical problem to be solved by the present invention is to provide a display device and a driving method thereof that can improve the distribution of production processes and thereby improve the variation in image quality characteristics between display devices.

A display device according to an embodiment of the present invention includes: a display unit including a plurality of pixels, a plurality of scanning lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels; A gate-on voltage is sequentially applied to a plurality of scanning lines; a data drive unit applies data signals to the plurality of data lines in response to the gate-on voltage; a signal control unit generates an image data signal, thereby forwarding it to the above-mentioned data driving part; The signal control unit includes a plurality of unit standard data, selects unit standard data corresponding to the unit information from the plurality of unit standard data, and generates the image data signal based on the selected unit standard data.

The plurality of unit standard data may each include image data signal values corresponding to a predetermined number of gradations.

The display substrate including the plurality of pixels may include a thin film transistor display panel included in a liquid crystal display panel assembly, and the liquid crystal display panel assembly includes the above thin film transistor display panel, a common electrode display panel opposite to the above thin film transistor display panel, And a liquid crystal layer filled between the thin film transistor display panel and the common electrode display panel.

The unit information may indicate the area occupied by the thin film transistor display panel among multiple areas divided on a large substrate used to manufacture a plurality of thin film transistor display panels.

The unit information providing unit may include: a first power supply line; a second power supply line; and at least one transistor, and the at least one transistor includes: a gate connected to the first power supply line; One electrode connected to one of the power lines; and the other electrode connected to the output terminal.

The first power line and the output terminal may be connected to the signal control unit, and the signal control unit applies a cell information confirmation voltage to the first power line.

A ground voltage may be applied to the above-mentioned second power supply line.

The at least one transistor may be an n-channel field effect transistor, and the cell information confirmation voltage is a high-level voltage.

The cell information may be represented by a combination of bit information represented by a voltage output from an output terminal of the at least one transistor.

The at least one transistor mentioned above may be an oxide thin film transistor.

The unit information providing unit may include: a first power line, a second power line, and at least one logic circuit, and the at least one logic circuit includes: a first power line connected to one of the first power line and the second power line. An input terminal, a second input terminal connected to one of the first power line and the second power line, and an output terminal connected to the signal control unit.

The first power line may be connected to the signal control unit, and the signal control unit may apply a cell information confirmation voltage to the first power line.

A ground voltage may be applied to the above-mentioned second power supply line.

The above-mentioned unit information may be represented by a combination of bit information represented by a signal output from an output terminal of the above-mentioned at least one logic circuit.

The driving method of a display device according to other embodiments of the present invention includes: a step of outputting a unit information confirmation voltage at an initial stage before the display device displays an image; a step of obtaining unit information in response to the above unit information confirmation voltage; a step of selecting unit standard data corresponding to the unit information from the standard data; and a step of generating an image data signal for the display device to display an image based on the selected unit standard data.

In an initial stage before the display device displays an image, the step of outputting the unit information confirmation voltage may include: a step of applying the unit information confirmation voltage to the first power line; and a step of applying a ground voltage to the second power line.

In the step of obtaining unit information in response to the confirmation voltage of the unit information, it may include: a step of outputting the unit information through at least one transistor, and the transistor includes a gate connected to the first power supply line; An electrode connected to one of the above-mentioned second power lines.

The step of obtaining unit information in response to the confirmation voltage of the unit information may include: a step of outputting the unit information through at least one logic circuit, and the logic circuit includes: a first input terminal connected to the first power line and the second One of the two power lines is connected; and the second input terminal is connected to one of the first power line and the second power line.

The plurality of unit standard data may each include image data signal values corresponding to a predetermined number of gradations.

The above display device may include: a thin film transistor display panel; a common electrode display panel opposite to the above thin film transistor display panel; and a liquid crystal layer filled between the above thin film transistor display panel and the above common electrode display panel, and the above unit information indicates that the above thin film The area occupied by a transistor display panel among the multiple areas divided on a large substrate used to manufacture multiple thin film transistor display panels.

Since the data signal corrected based on the cell information of the thin film transistor display panel is output, it is possible to improve the dispersion of the manufacturing process by the cell position of the thin film transistor display panel. By improving the distribution of production steps, it is possible to improve the variation in image quality characteristics between liquid crystal display devices.

Description of drawings

FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 shows an equivalent circuit for one pixel of FIG. 1 .

Fig. 3 is a circuit diagram showing a cell information providing unit according to an embodiment of the present invention.

Fig. 4 is a circuit diagram showing a cell information providing unit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a signal control unit according to an embodiment of the present invention.

FIG. 6 is a timing chart showing a method of driving a liquid crystal display device according to an embodiment of the present invention.

FIG. 7 shows an example of dividing a large substrate into a plurality of units for a thin film transistor display panel in a manufacturing process of a thin film transistor display panel.

8 is a graph showing the results of measurement of the gamma value distribution with respect to the gray scale of a liquid crystal display device including a thin film transistor display panel formed in a first cell among a plurality of cells divided on a large substrate.

FIG. 9 is a graph showing the results of measurement of gamma value distribution with respect to gradation of a liquid crystal display device including a thin film transistor display panel formed in a second cell among a plurality of cells divided on a large substrate.

FIG. 10 is a graph showing the results of measurement of gamma value distribution with respect to gradation in a liquid crystal display device including a thin film transistor display panel formed in a third unit among a plurality of units divided on a large substrate.

FIG. 11 is a graph showing the results of measurement of gamma value distribution with respect to gradation in a liquid crystal display device including a thin film transistor display panel formed in a fourth unit among a plurality of units divided on a large substrate.

Label description

100: Signal Control Department

101: Standard Data Lookup Form

102: Selection Ministry

150: Unit Information Provider

151: First power cord

152: Second power cord

200: Scan drive unit

300: Data Driven Department

400: Liquid crystal display panel assembly

Detailed ways

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the technical field of the present invention can easily implement them. The present invention can be expressed in various forms, and is not limited to the embodiments described here.

In addition, in a plurality of embodiments, the same reference numerals are used for constituent elements having the same structure, and are representatively described in the first embodiment, and only the structures different from the first embodiment are described in the other embodiments.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar structural elements throughout the specification.

Throughout the specification, when it is described that a certain part is "connected" to other parts, it includes not only the case of "direct connection" but also the case of "electrical connection" via other elements in between. In addition, when it is stated that a certain part "contains" a certain structural element, it means that other structural elements are not excluded but may be further included unless there is a specific contrary statement.

First, the structure and operation of a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5 .

FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1 , the liquid crystal display device includes a signal control unit 100 , a cell information providing unit 150 , a scan driving unit 200 , a data driving unit 300 , and a liquid crystal panel assembly (liquid crystal panel assembly) 400 .

The liquid crystal display panel assembly 400 includes a plurality of pixels PX, a plurality of scan lines S1-Sn, and a plurality of data lines D1-Dm arranged roughly in a matrix. The plurality of pixels PX are connected to the plurality of scanning lines S1 to Sn and the plurality of data lines D1 to Dm. The plurality of scan lines S1 ˜ Sn approximately extend along the row direction and are almost parallel to each other, and the plurality of data lines D1 ˜ Dm approximately extend along the column direction and are almost parallel to each other. At least one polarizer (not shown) for polarizing light is attached on the outer surface of the liquid crystal display panel assembly 400 .

The signal control unit 100 receives image signals R, G, B and synchronization signals input from an external device. The image signals R, G, and B have luminance information of a plurality of pixels. The luminance has a predetermined number such as 1024 (=2 ¹⁰ ), 256 (=2 ⁸ ), or 64 (=2 ⁶ ) grayscales (gray). The synchronization signals include a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync and a main clock signal MCLK.

The signal control unit 100 generates the first drive control signal CONT1, the second drive control signal CONT2, and the image Data signal DAT. The signal control unit 100 divides the image signals R, G, and B into frame units based on the vertical synchronization signal Vsync, and divides the image signals R, G, and B into scanning line units based on the horizontal synchronization signal Hsync, thereby generating an image data signal DAT. The signal control unit 100 forwards the first driving control signal CONT1 to the scan driving unit 200 . The signal control unit 100 forwards the image data signal DAT together with the second driving control signal CONT2 to the data driving unit 300 .

The signal control unit 100 transfers the unit information confirmation voltage Vcc to the unit information providing unit 150 and obtains the unit information CI from the unit information providing unit 150 . The signal control unit 100 includes a plurality of unit standard data, and selects unit standard data corresponding to the unit information CI from among the plurality of unit standard data. The signal control unit 100 generates an image data signal DAT based on the selected cell standard data. The unit standard data includes image data signal values corresponding to each of a predetermined number of gradations.

Upon receiving the cell information confirmation voltage Vcc from the signal control unit 100 , the cell information providing unit 150 supplies the unique cell information CI to the signal control unit 100 . The cell information CI corresponds to the position occupied by the thin film transistor display panel 10 on one large substrate in the manufacturing process of the thin film transistor display panel (see 10 in FIG. 2 ) included in the liquid crystal display panel assembly 400 . That is, the cell information CI indicates the position in the manufacturing process of the thin film transistor display panel 10 included in the liquid crystal display panel assembly 400 which is a display substrate including a plurality of pixels PX.

The scan driving unit 200 is connected to a plurality of scan lines S1 to Sn, and generates a plurality of scan signals based on a first drive control signal CONT1. The scan driving unit 200 can sequentially apply a scan signal having a gate-on voltage to the plurality of scan lines S1 to Sn.

The data driving unit 300 is connected to the plurality of data lines D1-Dm, samples and holds the input image data signal DAT according to the second driving control signal CONT2, and transfers the plurality of data signals to the plurality of data lines D1-Dm. The data driving unit 300 applies a data signal within a predetermined voltage range to a plurality of data lines D1 to Dm in response to a scan signal of a gate-on voltage.

Each of the above-mentioned drive devices 100, 150, 200, 300 can be installed directly on the liquid crystal display panel assembly 400 in the form of at least one integrated circuit chip, or installed on a flexible printed circuit film (flexible printed circuit film), or with The TCP (tape carrier package) is attached to the liquid crystal display panel assembly 400, or installed on other printed circuit boards (printed circuit board). Alternatively, the driving devices 100 , 150 , 200 , and 300 may also be integrated into the liquid crystal display panel assembly 400 together with the plurality of scan lines S1 ˜ Sn and the plurality of data lines D1 ˜ Dm.

FIG. 2 shows an equivalent circuit for one pixel of FIG. 1 .

Referring to FIG. 2 , the liquid crystal display panel assembly 400 includes a thin film transistor display panel 10 , a common electrode display panel 20 and a liquid crystal layer 15 . The TFT display panel 10 and the common electrode display panel 20 face each other. The liquid crystal layer 15 is filled between the TFT display panel 10 and the common electrode display panel 20 . The liquid crystal display panel assembly 400 forms a gap between the TFT display panel 10 and the common electrode display panel 20 , and may include a spacer (spacer, not shown) capable of compressive deformation to a certain extent.

One pixel PX of the liquid crystal display panel assembly 400 will be described. The pixel PX connected to the i-th (i=1˜n) scanning line Si and the j-th (j=1˜m) data line Dj is described as an example. The pixel PX includes a switching element Q and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto.

The switching element Q is a thin film transistor included in the thin film transistor display panel 10 , and includes a gate connected to the scanning line Si, a source connected to the data line Dj, and a drain connected to the pixel electrode PE of the liquid crystal capacitor Clc. Thin film transistors include amorphous silicon (amorphous silicon) or polycrystalline silicon (polycrystalline silicon).

On the other hand, the thin film transistor may be an oxide thin film transistor (Oxide TFT) in which a semiconductor layer is formed of an oxide semiconductor.

The oxide semiconductor may contain zinc oxide based on oxides based on titanium Ti, hafnium Hf, zirconium Zr, aluminum Al, tantalum Ta, germanium Ge, zinc Zn, gallium Ga, tin Sn, or indium In, as their composite oxides ZnO, indium gallium zinc oxide InGaZnO4, indium zinc oxide Zn-In-O, zinc tin oxide Zn-Sn-O, indium gallium oxide In-Ga-O, indium tin oxide In-Sn-O, indium zirconium oxide In-Zr-O, indium zirconium zinc oxide In-Zr-Zn-O, indium zirconium tin oxide In-Zr-Sn-O, indium zirconium gallium oxide In-Zr-Ga-O, indium aluminum oxide In -Al-O, indium zinc aluminum oxide In-Zn-Al-O, indium tin aluminum oxide In-Sn-Al-O, indium aluminum gallium oxide In-Al-Ga-O, indium tantalum oxide In- Ta-O, indium tantalum zinc oxide In-Ta-Zn-O, indium tantalum tin oxide In-Ta-Sn-O, indium tantalum gallium oxide In-Ta-Ga-O, indium germanium oxide In-Ge -O, indium germanium zinc oxide In-Ge-Zn-O, indium germanium tin oxide In-Ge-Sn-O, indium germanium gallium oxide In-Ge-Ga-O, titanium indium zinc oxide Ti-In - one of Zn-O, hafnium indium zinc oxide Hf-In-Zn-O.

The semiconductor layer includes a channel region into which no impurity has penetrated, and a source region and a drain region formed by impregnation into both sides of the channel region. Here, such impurities differ depending on the type of thin film transistor, and may be donor (N-type) impurities or acceptor (P-type) impurities.

When the semiconductor layer is made of an oxide semiconductor, a protective layer may be additionally added in order to protect the oxide semiconductor which is susceptible to external environmental influences such as high temperature.

The liquid crystal capacitor Clc includes the pixel electrode PE of the thin film transistor display panel 10 and the opposite common electrode CE of the display panel 20 . That is, the liquid crystal capacitor Clc uses the pixel electrode PE of the TFT display panel 10 and the common electrode CE of the common electrode display panel 20 as two terminals, and the liquid crystal layer 15 between the pixel electrode PE and the common electrode CP functions as a dielectric.

The pixel electrode PE is connected to the switching element Q. The common electrode CE is formed on the entire surface of the common electrode display panel 20 and is applied with a common voltage Vcom. On the other hand, sometimes the common electrode CE is also included in the TFT display panel 10 , and at this time at least one of the pixel electrode PE and the common electrode CE may be formed in a line shape or a strip shape. The common voltage Vcom is a predetermined voltage of a certain level, and may have a voltage around approximately 0V.

The storage capacitor Cst serving as an auxiliary function of the liquid crystal capacitor Clc is formed to be superimposed on other signal lines (not shown) provided in the thin film transistor display panel 10 and the pixel electrode PE with an insulator interposed therebetween. A predetermined voltage such as a common voltage Vcom is applied to the other signal lines.

A color filter (CF) may be formed on a portion of the common electrode CE of the common electrode display panel 20 . Each pixel PX can be fixed to display one of the primary colors, and the desired color can be identified by the spatial sum of the primary colors. Each pixel PX can alternately display primary colors according to time, and a desired color can be identified by the time sum of the primary colors. Examples of primary colors include three primary colors such as red, green, and blue.

Here, as an example of space division, it is shown that each pixel electrode PX has a color filter CF displaying one of the primary colors in the area of the common electrode display panel 20 corresponding to the pixel electrode PE. Alternatively, the color filter CF may be formed above or below the pixel electrode PE of the TFT display panel 10 .

Fig. 3 is a circuit diagram showing a cell information providing unit according to an embodiment of the present invention.

Referring to FIG. 3 , the unit information providing unit 150 includes at least one transistor ( M1 , M2 , M3 , M4 ), a first power supply line 151 , and a second power supply line 152 . At least one transistor (M1, M2, M3, M4) includes a gate connected to the first power line 151, an electrode connected to one of the first power line 151 and the second power line 152, and an electrode connected to the output terminal OUT connected to another electrode. At least one transistor ( M1 , M2 , M3 , M4 ) is turned on according to the voltage applied to the first power line 151 , so that the voltage applied to the first power line 151 and the voltage applied to the second power line 152 are turned on. One of them is output to the output terminal OUT.

Here, a description will be given assuming that the cell information providing unit 150 includes four transistors M1 , M2 , M3 , and M4 . The number of transistors included in the cell information providing unit 150 is not limited.

The first power line 151 and the output terminal OUT are connected to the signal control unit 100 . The signal control unit 100 applies the cell information confirmation voltage Vcc to the first power supply line 151 . The second power line 152 is applied with a ground voltage GND. The cell information confirmation voltage Vcc is a voltage having a level different from the ground voltage GND. For example, the cell information confirmation voltage Vcc may be 3.3V.

The first transistor M1 includes a gate connected to the first power line 151 , one electrode connected to one of the first power line 151 and the second power line 152 , and the other electrode connected to the output terminal OUT. It is assumed here that one electrode of the first transistor M1 is connected to the first power line 151 . That is, the first transistor M1 is diode-connected.

The second transistor M2 includes a gate connected to the first power line 151 , one electrode connected to one of the first power line 151 and the second power line 152 , and the other electrode connected to the output terminal OUT. Here, it is assumed that one electrode of the second transistor M2 is connected to the first power supply line 151 . That is, the second transistor M2 is diode-connected.

The third transistor M3 includes a gate connected to the first power line 151 , one electrode connected to one of the first power line 151 and the second power line 152 , and the other electrode connected to the output terminal OUT. Here, it is assumed that one electrode of the third transistor M3 is connected to the second power supply line 152 .

The fourth transistor M4 includes a gate connected to the first power line 151 , one electrode connected to one of the first power line 151 and the second power line 152 , and the other electrode connected to the output terminal OUT. Here, it is assumed that one electrode of the fourth transistor M4 is connected to the first power supply line 151 . That is, the fourth transistor M4 is diode-connected.

When the signal control unit 100 applies a cell signal confirmation voltage Vcc of a predetermined level to the first power supply line 151, the cell information confirmation voltage Vcc is transmitted through the diode-connected first transistor M1, second transistor M2, and fourth transistor M4. output to the output terminal OUT. The third transistor M3 is turned on by the cell information confirmation voltage Vcc, and the ground voltage GND is output to the output terminal OUT.

The voltage output to the output terminal OUT through the first transistor M1 represents the first bit information CI-1 of the cell information CI. The voltage output to the output terminal OUT through the second transistor M represents the second bit information CI-2 of the cell information CI. The voltage output to the output terminal OUT through the third transistor M3 represents the third bit information CI-3 of the cell information CI. The voltage output to the output terminal OUT through the fourth transistor M4 represents the fourth bit information CI-4 of the cell information CI. Four-bit cell information CI is represented by a combination of first to fourth bit information CI-1, CI-2, CI-3, and CI4. That is, it is possible to generate cell information CI of the number of bits corresponding to the number of transistors included in the cell information providing unit 150 .

When the ground voltage GND is set to 0 and the cell information confirmation voltage Vcc is set to 1, the four-bit cell information CI becomes "1011". The cell information CI corresponds to the position of the thin film transistor display panel 10 on one large substrate in the manufacturing process of the thin film transistor display panel 10 included in the liquid crystal display panel assembly 400 .

Above, the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 may be n-channel field effect transistors. The gate-on voltage for turning on the n-channel field effect transistor is a high-level voltage, and the gate-off voltage for turning off the transistor is a low-level voltage. At this time, the cell information confirmation voltage Vcc becomes a high-level voltage.

On the other hand, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be p-channel field effect transistors. The gate turn-on voltage for turning on the p-channel field effect transistor is a low-level voltage, and the gate-off voltage for turning off the p-channel field effect transistor is a high-level voltage. At this time, the cell information confirmation voltage Vcc becomes a low-level voltage.

On the other hand, at least one of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 may be an oxide thin film transistor (Oxide TFT) whose semiconductor layer is made of an oxide semiconductor.

Fig. 4 is a circuit diagram showing a cell information providing unit according to another embodiment of the present invention.

Referring to FIG. 4 , the unit information providing unit 150 includes at least one logic circuit ( AND1 , AND2 , AND3 , AND4 ), a first power supply line 151 and a second power supply line 152 . At least one logic circuit (AND1, AND2, AND3, AND4) includes a first input, a second input and an output. The first input end is connected to one of the first power line 151 and the second power line 152 . The second input end is connected to one of the first power line 151 and the second power line 152 . The output terminal OUT is connected to the signal control unit 100 . At least one logic circuit ( AND1 , AND2 , AND3 , AND4 ) outputs 0 or 1 to the output terminal OUT according to the voltages applied to the first power line 151 and the second power line 152 .

Here, it is assumed that the cell information providing unit 150 includes four AND gates AND1, AND2, AND3, and AND4. The number of AND gates included in the cell information providing unit 150 is not limited. In addition, not only AND gates but also OR gates, NAND gates, and NOR gates can be used as logic circuits.

The first power supply line 151 is connected to the signal control unit 100 and is supplied with the cell information confirmation voltage Vcc output from the signal control unit 100 . The second power line 152 is applied with a ground voltage GND. The cell information confirmation voltage Vcc is a voltage having a level different from the ground voltage GND. For example, the cell information confirmation voltage Vcc may be 3.3V.

The first AND gate AND1 includes a first input terminal connected to the first power line 151 , a second input terminal connected to one of the first power line 151 and the second power line 152 , and an output terminal OUT. Here it is assumed that the second input end of the first AND gate AND1 is connected to the first power line 151 .

The second AND gate AND2 includes a first input terminal connected to the first power line 151 , a second input terminal connected to one of the first power line 151 and the second power line 152 , and an output terminal OUT. Here it is assumed that the second input end of the second AND gate AND2 is connected to the first power line 151 .

The third AND gate AND3 includes a first input terminal connected to the first power line 151 , a second input terminal connected to one of the first power line 151 and the second power line 152 , and an output terminal OUT. Here it is assumed that the second input end of the third AND gate AND3 is connected to the second power line 152 .

The fourth AND gate AND4 includes a first input terminal connected to the first power line 151 , a second input terminal connected to one of the first power line 151 and the second power line 152 , and an output terminal OUT. Here it is assumed that the second input end of the fourth AND gate AND4 is connected to the first power line 151 .

When the ground voltage GND is set to 0 and the cell information confirmation voltage Vcc is set to 1, if a cell information confirmation voltage Vcc of a predetermined level is applied from the signal control unit 100 to the first power line 151, the first AND gates AND1, The second AND gate AND2 and the fourth AND gate AND4 output 1. In addition, the third AND gate AND3 outputs 0.

The signal output from the output terminal OUT of the first AND gate AND1 represents the first bit information CI-1 of the cell information CI. The signal output from the output terminal OUT of the second AND gate AND2 represents the second bit information CI-2 of the cell information CI. The signal output from the output terminal OUT of the third AND gate AND3 represents the third bit information CI-3 of the cell information CI. The signal output from the output terminal OUT of the fourth AND gate AND4 represents the fourth bit information CI-4 of the cell information CI. Four-bit cell information CI is represented by a combination of first to fourth bit information CI-1, CI-2, CI-3, and CI-4. The four-bit unit information CI becomes "1011". The cell information CI corresponds to the position of the thin film transistor display panel 10 on one large substrate in the manufacturing process of the thin film transistor display panel 10 included in the liquid crystal display panel assembly 400 .

FIG. 5 is a block diagram showing a signal control unit according to an embodiment of the present invention.

Referring to FIG. 5 , the signal control unit 100 includes a standard data lookup table 101 and a selection unit 102 .

The standard data lookup table 101 contains a plurality of unit standard data. Each of the plurality of unit standard data includes image data signal values respectively corresponding to predetermined numbers of gradations.

For example, the first unit standard data includes image data signal values corresponding to gradations of 0 to 255, respectively. The second unit standard data includes image data signal values respectively corresponding to gradations of 0 to 255. At this time, the first unit standard data reflects the gamma characteristics of the thin film transistor display panel 10 at the first position in a large substrate during the manufacturing process. The second unit standard data reflects the gamma characteristics of the thin film transistor display panel 10 located at the second position in a large substrate during the manufacturing process. In this way, the kth unit standard data reflecting the gamma characteristic of the TFT display panel 10 located at the kth position in one large substrate in the manufacturing process is prepared.

That is, each of the plurality of unit standard data includes image data signal values reflecting gamma characteristics based on the position occupied by the thin film transistor display panel 10 on one large substrate in a manufacturing process for a predetermined number of gradations. Multiple unit standard data can be obtained through experiments respectively.

The selection unit 102 receives the unit information CI from the unit information providing unit 150 , and selects unit standard data corresponding to the unit information CI from the standard data lookup table 101 .

For example, when the cell information CI indicates the first position, the selection unit 102 selects the first cell standard data from the standard data lookup table 101 . Among the image data signal values corresponding to gradations of 0 to 255 included in the first standard data, the image data signal values corresponding to the image signals R, G, and B input to the signal control unit 100 are recorded as the image data signal DAT. is output.

FIG. 6 is a timing chart showing a method of driving a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 6 , in the initial stage before power is applied to the liquid crystal display device and the liquid crystal display device displays an image, the signal control unit 100 outputs the cell information confirmation voltage Vcc ( S110 ). The cell information confirmation voltage Vcc is applied to the first power supply line 151 connected to the cell information providing unit 150 . The cell information providing unit 150 outputs the cell information CI using the cell information checking voltage Vcc applied to the first power line 151 and the ground voltage GND applied to the second power line 152 . The cell information CI may be output as a specific value according to the form in which at least one transistor is connected to the first power supply line 151 and the second power supply line 152 . Alternatively, the cell information CI may be output as a specific value according to the form in which at least one logic circuit is connected to the first power supply line 151 and the second power supply line 152 .

The signal control part 100 acquires the cell information CI output from the cell information providing part 150 in response to the cell information confirmation voltage Vcc ( S120 ). By at least one transistor (M1 to M4) including a gate connected to the first power supply line 151 and an electrode connected to one of the above-mentioned first power supply line 151 and the above-mentioned second power supply line 152, the cell information CI can be output . Or, by including a first input end connected to one of the first power line 151 and the second power line 152, and a second input end connected to one of the first power line 151 and the second power line 152 At least one logic circuit (AND1 to AND4) can output the above-mentioned unit information.

The signal control unit 100 includes a standard data lookup table 101 having a plurality of unit standard data, and selects unit standard data corresponding to the cell information CI from the standard data lookup table 101 ( S130 ). The plurality of unit standard data includes image data signal values reflecting gamma characteristics based on the position occupied by the thin film transistor display panel 10 on a large substrate in a manufacturing process, respectively, in a predetermined number of gradations.

The signal control unit 100 generates an image data signal (DAT) for displaying an image by the display device based on the selected cell standard data ( S140 ). Among the image data signal values corresponding to the predetermined number of gradations included in the selected unit standard data, the image data signal values corresponding to the image signals R, G, and B input to the signal control section 100 are output as Image data signal DAT.

FIG. 7 shows an example of dividing one large substrate into a plurality of units for the thin film transistor display panel in the manufacturing process of the thin film transistor display panel.

Referring to FIG. 7 , the thin film transistor display panel 10 is produced by repeatedly performing unit processes such as cleaning, deposition, photolithography, etching, photo resist strip, and inspection. When manufacturing a plurality of liquid crystal display devices, if such a unit process is repeated every time one thin film transistor display panel 10 is manufactured, the manufacturing time of the liquid crystal display device will become longer.

In order to shorten the manufacturing time of the liquid crystal display device, a plurality of thin film transistor display panels 10 are manufactured simultaneously through a large substrate 500 . A large panel 500 is divided into a plurality of regions (A to H), and one TFT display panel 10 is fabricated in each region (A to H).

Hereinafter, a region of a thin film transistor display panel 10 fabricated on a large substrate 500 is called a cell. The cell information CI indicates the area occupied by the thin film transistor display panel 10 among the divided regions (A to H) in the large substrate 500 for manufacturing the plurality of thin film transistor display panels.

It is shown here that the large substrate 500 is divided into 8 units (A to H) and 8 TFT display panels 10 are fabricated simultaneously. In this case, the cell information providing unit 150 may generate the cell information CI using three or more transistors or three or more logic circuits.

Table 1 shows an example of cell information CI indicating eight cells (A to H) on the large substrate 500 .

【Table 1】

CI-4 CI-3 CI-2 CI-1 unit 0 0 0 0A 0 0 0 1B 0 0 1 0C 0 0 1 1D 0 1 0 0E 0 1 0 1F 0 1 1 0G 0 1 1 1H

That is, the four-bit unit information CI is represented by a combination of the first to fourth bit information CI-1, CI-2, CI-3, and CI-4 output from the unit information providing part 150, and the unit information CI can be expressed in A cell occupying a specific position in a large substrate 500 .

It is assumed here that the large substrate 500 is divided into 8 units (A to H) and 8 thin film transistor display panels 10 are produced at the same time, but the number of thin film transistor display panels 10 that can be produced simultaneously with one large substrate 500 can be determined according to the production environment or The size and the like of the liquid crystal display device are variously specified.

In the manufacturing process of the thin film transistor display panel 10 , due to equipment limitations, it is impossible to irradiate the entire large substrate with a fixed amount of exposure. That is, in one large substrate, variations in the exposure amount between the thin film transistor display panels 10 occur based on the positions of the cells. Variations in exposure amount can cause variations in image quality characteristics among liquid crystal display devices.

In response to this, the large substrate 500 was divided into eight cells (A to H), and the gamma distribution of the liquid crystal display device based on the positions of the cells was measured. 8 to 11 are graphs showing the experimental results for this.

8 shows gamma values (hereinafter referred to as “A Graph of the results for the gamma distribution of the cell"). Gamma distributions of four liquid crystal display devices including thin film transistor display panels formed in unit A were measured.

9 shows gamma values (hereinafter referred to as "D Graph of the results for the gamma distribution of the cell"). The gamma distributions of five liquid crystal display devices including thin film transistor display panels formed in unit D were measured.

10 shows gamma values (hereinafter referred to as "E Graph of the results for the gamma distribution of the cell"). The gamma distributions of four liquid crystal display devices including thin film transistor display panels formed in the E unit were measured.

11 shows gamma values (hereinafter referred to as “H Graph of the results for the gamma distribution of the cell"). Gamma distributions of four liquid crystal display devices including thin film transistor display panels formed in the H cell were measured.

Comparing the gamma distribution of the D unit and the gamma distribution of the E unit, it can be seen that the gamma distribution of the D unit is similar to the gamma distribution of the E unit. Units D and E are units corresponding to the central portion of the large substrate 500 .

It can be seen that the gamma distribution of unit A shows a lower gamma value at high gray levels, which is different from the gamma distribution of unit D and the gamma distribution of unit E.

It can be seen that the gamma distribution of unit H shows a higher gamma value at high gray levels, which is different from the gamma distribution of unit D and the gamma distribution of unit E.

Thus, it can be seen that the gamma distribution differs from each other in the cells located in the central portion of the large substrate 500 and in the cells located in the edge portion.

In order to improve image quality characteristics, it is preferable that the gamma value based on the gradation coincides with the standard gamma value of 2.2. The grayscale-based image data signal value is specified so that the grayscale-based gamma value coincides with the standard gamma value of 2.2. For example, if a gamma value appears to be higher or lower than a standard gamma value in a certain grayscale, the image data signal value in that grayscale is adjusted such that the image data signal value follows a 2.2 gamma curve. In this way, the respective image data signal values of 0 to 255 gray scales are determined.

When the respective image data signal values of 0 to 255 gray scales are specified as one, the image data signal DAT will follow the 2.2 gamma curve well in one liquid crystal display device, but on the contrary it may be possible in another liquid crystal display device. The image data signal DAT in the device cannot follow the 2.2 gamma curve. A liquid crystal display device in which the image data signal DAT cannot follow the 2.2 gamma curve suffers from poor image quality.

For example, it is assumed that image data signal values of gradations of 0 to 255 are specified based on the gamma distribution of cells located in the center of the large substrate 500 . If the liquid crystal display device having the gamma distribution of the cells located at the edge of the large substrate 500 generates an image based on the image data signal value of the gradation specified based on the gamma distribution of the cells located at the central part of the large substrate 500 If the data signal DAT is low, the generated image data signal DAT cannot follow the 2.2 gamma curve well, resulting in poor image quality.

As mentioned above, prepare the standard data lookup table 101 including the cell standard data corresponding to the position of the cell in the manufacturing process of the TFT display panel 10, select the cell standard data corresponding to the cell information CI indicating the position of the cell, The image data signal DAT is generated based on the unit standard data, so that the image data signal DAT can well follow the 2.2 gamma curve, which can improve the image quality characteristics of the liquid crystal display device.

The drawings and the detailed description of the invention referred to so far are merely illustrations of the present invention, and are intended only to illustrate the present invention, and are not intended to limit the meaning or scope of the present invention described in the claims. Therefore, those skilled in the art can understand that various modifications and equivalent other embodiments can be made. Therefore, the true technical protection scope of the present invention is determined by the technical idea of the claims.

Claims (10)

1. a display device, is characterized in that, comprises:

Display part, the multiple data lines comprising multiple pixel, the multiple sweep trace be connected with above-mentioned multiple pixel and be connected with above-mentioned multiple pixel;

Scanning driving part, applies gate-on voltage successively to above-mentioned multiple sweep trace;

Data driver, in response to above-mentioned gate-on voltage, applies data-signal to above-mentioned multiple data line;

Signal control part, according to the picture signal be transfused to and synchronizing signal, image data generating signal, thus be transmitted to above-mentioned data driver; And

Unit information providing unit, is supplied to above-mentioned signal control part by the unit information of the position be used to indicate on the production process of the display base plate comprising above-mentioned multiple pixel,

Above-mentioned signal control part comprises multiple unit normal data, selects the unit normal data corresponding with said units information, generate above-mentioned viewdata signal based on selected unit normal data from above-mentioned multiple unit normal data.

2. display device as claimed in claim 1, is characterized in that,

Above-mentioned multiple unit normal data comprises the viewdata signal value corresponding respectively with the gray scale of specified number or amount respectively.

3. display device as claimed in claim 1, is characterized in that,

The display base plate comprising above-mentioned multiple pixel comprises film transistor display panel, and this film transistor display panel is contained in display panels assembly,

The liquid crystal layer that above-mentioned display panels assembly comprises the above-mentioned film transistor display panel public electrode display panel relative with above-mentioned film transistor display panel and fills between above-mentioned film transistor display panel and above-mentioned public electrode display panel.

4. display device as claimed in claim 3, is characterized in that,

Said units information represents region shared in multiple regions that above-mentioned thin film transistor (TFT) divides on the large substrate for making multiple film transistor display panel.

5. display device as claimed in claim 1, is characterized in that,

Said units information providing unit comprises:

First power lead;

Second source line; And

At least one transistor,

At least one transistor above-mentioned comprises:

The grid be connected with above-mentioned first power lead;

With one of them electrode be connected in above-mentioned first power lead and above-mentioned second source line; And

Another electrode be connected with output terminal.

6. display device as claimed in claim 5, is characterized in that,

Above-mentioned first power lead is connected with above-mentioned signal control part with above-mentioned output terminal,

Above-mentioned signal control part is to above-mentioned first power lead applying unit validation of information voltage.

7. display device as claimed in claim 6, is characterized in that,

Ground voltage is applied to above-mentioned second source line.

8. display device as claimed in claim 7, is characterized in that,

At least one transistor above-mentioned is n slot field-effect transistor, and said units validation of information voltage is high level voltage.

9. display device as claimed in claim 5, is characterized in that,

Said units information is showed by the combination of the bit information represented by the voltage that exports from the output terminal of at least one transistor above-mentioned.

10. display device as claimed in claim 5, is characterized in that,

At least one transistor above-mentioned is oxide thin film transistor.