CN104269457A - n-type IBC silicon solar cell manufacturing method based on ion implantation technology - Google Patents

Abstract

The invention discloses a manufacturing method of n-type IBC silicon solar cells based on an ion implantation process. The doping of n ⁺ and p ⁺ regions is realized by combining boron diffusion and boron ion implantation, and the process does not require n ⁺ /p ⁺ interface is isolated, which can effectively avoid the tunnel junction leakage of the battery.

Description

Manufacturing method of n-type IBC silicon solar cell based on ion implantation process

technical field

The invention belongs to the technical field of solar cells, and in particular relates to a manufacturing method of an n-type IBC silicon solar cell based on an ion implantation process.

Background technique

Solar cells can directly convert solar energy into electrical energy, which is an effective way to utilize solar energy resources. Since no harmful substances are produced during use, solar cells are favored in solving energy and environmental problems and have a good market prospect. Solar energy is also Known as the most ideal energy source, it is an important resource for the survival and development of human society.

At present, the mainstream solar cell material uses p-type silicon as the substrate, and forms a pn junction through high-temperature phosphorus diffusion. For p-type silicon materials, because it is insensitive to metal impurities and many non-metal defects, and has fewer boron-oxygen pairs in the body, its performance stability is higher than that of p-type crystalline silicon cells, while n-type The higher minority carrier life of the battery lays the foundation for the preparation of more efficient solar cells.

Back-junction and back-contact solar cells began to come into people's sight as early as 1977, and until now it is still a research hotspot in the solar cell industry. Compared with conventional silicon cells, back-junction and back-contact solar cells have obvious advantages, mainly in the following aspects Aspects:

1. Back-junction and back-contact solar cells use n-type crystalline silicon as the substrate, which has a high minority carrier life, and is suitable for the preparation of high-efficiency cells, especially for back-junction and back-contact solar cells, which have a pn junction on the back surface of the cell structure. The photo-generated carriers on the front surface must migrate to the pn junction on the back surface of the cell before they can be utilized, and the higher minority carrier lifetime is the guarantee to reduce the recombination of photo-generated carriers on the surface and body of the solar cell;

2. The boron content of the N-type substrate is extremely low, so the light-induced attenuation caused by the boron-oxygen pair is not as obvious as that of the p-type substrate material, and the efficiency improvement of the packaged components is more obvious;

3. There is no electrode on the front of the back-junction and back-contact solar cells, which reduces the shading area and increases the photo-generated current. The positive and negative cells of the battery are distributed on the back of the battery in a finger-like shape;

4. Back-junction and back-contact solar cells are easy to package. Compared with conventional batteries, there is no need to cross the negative electrode of the previous sheet to the positive electrode of the latter sheet, which is easy to operate.

Contents of the invention

Purpose of the invention: For the problems and deficiencies in the above-mentioned prior art, the purpose of the present invention is to provide a method for manufacturing n-type IBC silicon solar cells based on ion implantation technology, which is safe and reliable, compatible with traditional solar cell production lines, suitable for The current solar cell production line is being upgraded.

Technical solution: The invention discloses a method for manufacturing an n-type IBC silicon solar cell based on an ion implantation process, comprising the following steps:

(1) Select an n-type silicon substrate with a resistivity of 3-12Ω·cm, and use chemical etching to remove the damaged layer on the surface of the silicon wafer, and then perform double-sided texturing;

(2) Double-sided phosphorus diffusion;

(3) Remove the phosphosilicate glass in the p ⁺ defined area by printing corrosive paste or laser etching;

(4) Selectively polish the p ⁺ defined area with an organic alkaline solution, and remove the n ⁺ diffusion layer in the p ⁺ defined area;

(5) Remove the phosphosilicate glass on the front surface, and then use an acidic solution to etch the front surface. The square resistance of the etched front surface is controlled at 100Ω/□-200Ω/□;

(6) Remove the phosphosilicate glass on the back surface of the n-type silicon wafer, and perform RCA cleaning;

(7) Boron implantation is selectively performed in the P+ defined area on the back of the n-type silicon wafer, and the amount of boron implantation is 1x10 ¹⁵ cm ^-3 -5x10 ¹⁶ cm ^-3 ;

(8) Annealing: the annealing temperature is controlled at 900°C-1000°C, the annealing time is controlled at 20-90min, and an oxide layer is formed on the front and back surfaces of the N-type silicon wafer at the same time, and the thickness of the oxide layer is 3-15nm;

(9) Deposit passivation layer: SiNx is deposited on both sides of the N-type silicon wafer;

(10) Holes in the dielectric film in the contact area on the back;

(11) Print metal paste on the n ⁺⁺ and p ⁺⁺ contact areas on the back of the n-type silicon wafer and sinter to form ohmic contacts;

Wherein, the organic alkaline solution in step (4) is TMAH or a mixture of TMAH and other alkaline solutions, the etching temperature is 60-80°C, and the etching time is 10min-30min;

The acidic solution in step (5) is a mixed solution of hydrofluoric acid and nitric acid.

In the present invention, the doping of n ⁺ and p ⁺ regions is realized by combining boron diffusion and boron ion implantation, and this process does not need to isolate the n ⁺ /p ⁺ interface on the back, so that the tunnel junction leakage of the battery can be effectively avoided .

As a further optimization of the present invention, the diffusion resistance in step (2) of the present invention is 40Ω/□-100Ω/□.

As a further optimization of the present invention, in step (5) of the present invention, hydrofluoric acid, nitric acid, and water are mixed at a volume ratio of 1:30:300.

As a further optimization of the present invention, the thickness of the SiNx on the front surface in step (9) of the present invention is 65nm-75nm.

As a further optimization of the present invention, the thickness of the back SiNx in step (9) of the present invention is 80nm-150nm.

As a further optimization of the present invention, in step (5) of the present invention, laser or printing corrosive paste is used to complete the opening of the dielectric film. If the back surface uses burn-through metallization paste, this step can be omitted.

As a further optimization of the present invention, the square resistance of the p ⁺ region on the back surface after annealing in step (8) of the present invention is between 50Ω/□-100Ω/□.

Beneficial effects: Compared with the prior art, the present invention adopts n-type crystalline silicon wafer as the base material, which has high minority carrier life and small light-induced attenuation, which has great advantages for preparing batteries and packaging components. The present invention adopts passivation The front and rear surfaces of the film passivation battery can effectively reduce the recombination rate of minority carriers on the surface and improve the lifetime of minority carriers on the surface, and prepare anti-reflection films on the front surface and the back surface, which can reduce the reflection of photons, increase the absorption of photons by the surface, and increase Photogenerated current in turn increases the conversion efficiency of the cell. Both the positive and negative electrodes of the battery of the present invention are made on the back side, so the light-shielding area is reduced, the photogenerated current is increased, the current generated by the silicon chip can be better collected, and a good ohmic contact is formed between the metal and the silicon chip.

The present invention has the characteristics of simple and mature technology, precise ion implantation technology, and selective doping. By controlling the doping concentration of the p ⁺ and n ⁺ regions on the back, there is no need to isolate the n ⁺ /p ⁺ interface on the back, which can effectively avoid The occurrence of tunnel junction leakage of the battery greatly reduces the complexity of the battery manufacturing process.

Description of drawings

Fig. 1 is a structural schematic diagram of the present invention.

Detailed ways

The present invention is further illustrated below in conjunction with the accompanying drawings and examples.

As shown in Figure 1, the solar cell according to the present invention is sequentially stacked with a front surface passivation layer 5, a front surface n+ region 2, an n-type silicon substrate 1, a back surface n++ doped region 3, a back surface p+ doped region 4 , back surface passivation layer 6 , back surface n++ contact electrode 7 and back surface p+ contact electrode 8 .

Example 1:

This embodiment includes the following steps:

1. Select an n-type silicon substrate with a resistivity of 3-5Ω·cm, and its minority carrier lifetime is greater than 500us, use chemical etching to remove the damaged layer on the surface of the silicon wafer , and make texture on both sides.

Double-sided phosphorus diffusion: the diffusion resistance is 60Ω/□.

3. Print corrosive paste on the p ⁺ defined area on the back to remove the phosphosilicate glass in the p ⁺ defined area.

4. Use 20% TMAH solution for selective etching at 60°C, and polish the p ⁺ defined area for 30 minutes.

5. Remove the phosphosilicate glass on the front surface of the n-type silicon wafer, use hydrofluoric acid, nitric acid and water with a volume ratio of 1:30:300 to etch the front surface of the n-type silicon wafer, and the square resistance of the etched front surface is 140Ω/□ .

6. Remove the back phosphosilicate glass and perform RCA cleaning.

7. Using the selective implantation feature of ion implantation, perform boron implantation in the p ⁺ defined region on the back of the n-type silicon wafer, with an implantation amount of 1x10 ¹⁵ cm ^-3 .

8. Anneal at a temperature of 950°C for 30 minutes, and at the same time grow a thin SiO ₂ layer on the front surface and the back surface of the N-type silicon wafer respectively. The thickness of the SiO ₂ layer is 10nm. □.

9. Deposit a 75nm SiNx passivation layer on the front surface of the N-type silicon wafer, and deposit a 120nm SiNx passivation layer on the back of the N-type silicon wafer.

10. Preparation of electrodes:

Print silver paste on the N++ area on the back of the n-type silicon wafer and dry it;

Aluminum paste is printed on the backside p ⁺ area and sintered to form an ohmic contact.

the

Example 2

This embodiment includes the following steps:

1. Select an N-type silicon substrate with a resistivity of 5-12Ω·cm, and its minority carrier lifetime is greater than 500us, remove the damaged layer on the surface of the silicon wafer by chemical etching, and make texture on both sides.

2. Double-sided phosphorus diffusion: the diffusion resistance is 80Ω/□.

3. Use laser to remove the phosphosilicate glass in the P+ defined area. the

4. Use 25% TMAH solution at 70°C for selective etching properties, and polish the p ⁺ defined area for 20 minutes.

5. Remove the phosphosilicate glass on the front surface of the n-type silicon wafer, use 1:30:300 hydrofluoric acid, nitric acid and water to etch the front surface of the n-type silicon wafer at 25°C, and the etching time is 20min. The surface square resistance was 130Ω/□.

6. Remove the back phosphosilicate glass and perform RCA cleaning.

7. Using the selective implantation feature of ion implantation, perform boron implantation in the p ⁺ defined region on the back of the n-type silicon wafer, with an implantation amount of 5x10 ¹⁵ cm ^-3 .

8. Anneal at a temperature of 950°C for 40 minutes, and at the same time grow a thin SiO ₂ layer on the front surface and the back surface of the n-type silicon wafer respectively. The thickness of the SiO ₂ layer is 13nm. □.

9. Deposit a 72nm SiNx passivation layer on the front surface of the N-type silicon wafer, and deposit a 110nm SiNx passivation layer on the back of the N-type silicon wafer.

10. Preparation of electrodes:

Print silver paste on the n ⁺⁺ area on the back of the N-type silicon wafer and dry it;

Aluminum paste is printed on the backside p ⁺ area and sintered to form an ohmic contact.

Claims (7)

1. The n-type IBC silicon solar cell manufacturing method based on ion implantation technology, is characterized in that: comprise the following steps: (1) Select an n-type silicon substrate with a resistivity of 3-12Ω·cm, and use chemical etching to remove the damaged layer on the surface of the silicon wafer, and then perform double-sided texturing; (2) Double-sided phosphorus diffusion; (3) Remove the phosphosilicate glass in the p ⁺ defined area by printing corrosive paste or laser etching; (4) Selectively polish the p ⁺ defined area with an organic alkaline solution, and remove the n ⁺ diffusion layer in the p ⁺ defined area; (5) Remove the phosphosilicate glass on the front surface, and then use an acidic solution to etch the front surface at 25°C, the etching time is 5min-20min, and the square resistance of the etched front surface is controlled at 100Ω/□-200Ω/□; (6) Remove the phosphosilicate glass on the back surface of the n-type silicon wafer, and perform RCA cleaning; (7) Boron implantation is selectively performed in the p ⁺ defined area on the back of the n-type silicon wafer, and the amount of boron implantation is 1x10 ¹⁵ cm ^-3 -5x10 ¹⁶ cm ^-3 ; (8) Annealing: the annealing temperature is controlled at 900°C-1000°C, the annealing time is controlled at 20-90min, and an oxide layer is formed on the front and back surfaces of the n-type silicon wafer at the same time, and the thickness of the oxide layer is 3-15nm; (9) Deposit passivation layer: SiNx is deposited on both sides of the n-type silicon wafer; (10) Definition of the p-type contact area on the back: etching and removing the passivation film in the n-type area on the back by laser or printing corrosive paste; (11) Print metal pastes on the n ⁺⁺ and p ⁺⁺ regions on the back of the n-type silicon wafer and sinter them to form ohmic contacts; The acidic solution in step (5) is a mixed solution of hydrofluoric acid and nitric acid. 2. The manufacturing method of n-type IBC silicon solar cells based on ion implantation process according to claim 1, characterized in that: the diffusion square resistance in the step (2) is controlled at 40Ω/□-100Ω/□. 3. The manufacturing method of n-type IBC silicon solar cells based on ion implantation process according to claim 1, characterized in that: in the step (5), hydrofluoric acid, nitric acid, and water are mixed at a volume ratio of 1:30:300 made. 4 . The method for manufacturing an n-type IBC silicon solar cell based on ion implantation technology according to claim 1 , wherein the thickness of SiNx on the front surface in the step (9) is 65nm-75nm. 5 . The method for manufacturing an n-type IBC silicon solar cell based on an ion implantation process according to claim 4 , wherein the thickness of the back SiNx in the step (9) is 80nm-150nm. 6 . The method for manufacturing an n-type IBC silicon solar cell based on ion implantation process according to claim 1 , characterized in that: in the step (10), a laser or a corrosive paste is used to complete opening of the passivation film. 7 . 7. The method for manufacturing n-type IBC silicon solar cells based on ion implantation process according to claim 1, characterized in that: the square resistance of the p ⁺ region on the back surface after annealing in the step (8) is controlled at 50Ω/□ Between -100Ω/□.