CN104269394B - Capacitor and manufacturing method thereof - Google Patents
Capacitor and manufacturing method thereof Download PDFInfo
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- CN104269394B CN104269394B CN201410487164.1A CN201410487164A CN104269394B CN 104269394 B CN104269394 B CN 104269394B CN 201410487164 A CN201410487164 A CN 201410487164A CN 104269394 B CN104269394 B CN 104269394B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000003792 electrolyte Substances 0.000 claims description 78
- 239000010410 layer Substances 0.000 claims description 64
- 238000002360 preparation method Methods 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 23
- 230000005611 electricity Effects 0.000 claims description 21
- 239000011241 protective layer Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 description 26
- 238000000034 method Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 208000029152 Small face Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention discloses a capacitor which comprises a substrate, grooves and second dielectric media. First dielectric media are arranged on the substrate, a plurality of stacked finger inserting structures are arranged in the first dielectric media, each finger inserting structure comprises a plurality of first finger-shaped structures and a plurality of second finger-shaped structures, and in the same finger inserting structure, the first finger-shaped structures and the second fingers-shaped structures are oppositely arranged in a staggered mode. The grooves are formed in the first dielectric media, and are formed between the first finger-shaped structures and the second finger-shaped structures in the same finger inserting structure. The grooves are filled with the second dielectric media, and the dielectric constant of the second dielectric media is larger than that of the first dielectric media. Meanwhile, the invention further provides a manufacturing method of the capacitor. According to the capacitor and the manufacturing method, the breakdown voltage and the capacitance value of the capacitor can be effectively improved on the premise of not changing the standard manufacturing procedure of a logic device.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of capacitor and preparation method thereof.
Background technology
In semiconductor integrated circuit, the integrated capacitor made on the same chip with transistor circuit widely should
With.Its form mainly has metal-insulator-metal type (metal-insulator-metal, MIM) capacitor and metal-oxide
Two kinds of thing-metal (metal-oxide-metal, MOM) capacitor.Wherein, MIM capacitor uses upper/lower layer metallic as electric capacity
Pole plate, capacitance mainly determined by capacitor occupied area, therefore, the MIM capacitor meeting used in the occasion for needing bulky capacitor
Cost is caused to greatly increase；And MOM capacitor can be in relatively small face using the method that finger and lamination combine
The bigger electric capacity of capacity is made in product.Additionally, when MOM capacitor is made, without the need for extra photoresist layer and mask, so as to make
Make technique also simpler relative to MIM capacitor, cost is lower.
As shown in figure 1, finger-cross structure of the MOM capacitor of the prior art 1 comprising multiple stackings, each slotting finger knot
Structure includes multiple first fingers 11 and multiple second fingers 12, in the same finger-cross structure, described the
One finger 11 and the arrangement of 12 staggered relative of the second finger, first finger 11 and the second finger 12 lead to
Cross electrolyte to be isolated, in order to clearly show that finger-cross structure, be that the electrolyte is shown in Fig. 1.MOM capacitor 1 is by inserting
Refer to what the transverse electric field between structure was formed, in prior art, the electric field of MOM capacitor 1 is divided into following two situations：
The first, as shown in Fig. 2 in the same finger-cross structure, first finger 11 and the second finger-like knot
The electric field of structure 12 is different, and one of them is negative electricity, and another is positive electricity；The electric field of first finger 11 of adjacent two layers
It is identical；The electric field of second finger 12 of adjacent two layers is identical.Then electric capacity C1 is formed at first finger 11
And second between finger 12, the electric field of electric capacity C1 is transverse electric field.
Secondth, as shown in figure 3, in the same finger-cross structure, first finger 11 and the second finger-like are tied
The electric field of structure 12 is different, and one of them is positive electricity, and another is negative electricity；The electric field of first finger 11 of adjacent two layers
Difference, one of them is positive electricity, and another is negative electricity；The electric field of second finger 12 of adjacent two layers is different, wherein
One is positive electricity, and another is negative electricity.Then electric capacity C2 is formed between first finger 11 and the second finger 12,
The electric field of electric capacity C2 is transverse electric field.Electric capacity C3 is formed between first finger 11 of adjacent two layers or adjacent two layers
Second finger 12 between, the electric field of electric capacity C3 is longitudinal electric field.
In the prior art, MOM capacitor 1 is typically all integrated in the back-end process of logical device technique, and small size
Logical device (the advanced logic technology of characteristic size≤90nm) in back-end process, using Low-k (low k, general k value it is little
In equal to 4) material as interlayer dielectric so that the first finger 11 described in MOM capacitor 1 and the second finger-like knot
Dielectric dielectric constant between structure 12 is low, thus can not improve the capacitance of MOM.Furthermore, with the diminution of capacitor, institute
The size for stating finger-cross structure is less and less so that (in the same finger-cross structure, described first refers to the spacing between finger
The spacing of shape structure 11 and the second finger 12；Or the spacing of first finger 11 of adjacent two layers；Or adjacent two
The spacing of second finger 12 of layer), though contributing to the raising of capacitance, also cause the breakdown potential of MOM capacitor 1
Pressure drop is low.
The content of the invention
It is an object of the present invention to provide a kind of capacitor and preparation method thereof, in the premise for not changing capacitor volume
Under, breakdown voltage and the capacitance of capacitor can be effectively improved, and the method can apply to the standard of logical device
In processing procedure.
For solving above-mentioned technical problem, the present invention provides a kind of preparation method of capacitor, including：
One substrate is provided, there is on the substrate inserting comprising multiple stackings in the first electrolyte, first electrolyte
Refer to structure, each finger-cross structure includes multiple first fingers and multiple second fingers, same described
In finger-cross structure, first finger and the second finger staggered relative are arranged；
First electrolyte is performed etching to form multiple grooves, the groove is located in the same finger-cross structure
First finger and the second finger between；And
The second electrolyte is filled in the groove, and second dielectric dielectric constant is more than first electrolyte
Dielectric constant.
Optionally, in the preparation method of the capacitor, first electrolyte is performed etching multiple recessed to be formed
The step of groove, includes：
Photoresistance is formed on first electrolyte, and the photoresistance exposes first finger and the second finger-like knot
First electrolyte between structure；
The finger-cross structure with the photoresistance and top layer is performed etching to first electrolyte many to be formed as mask
Individual groove.
Optionally, in the preparation method of the capacitor, first electrolyte is performed etching multiple recessed to be formed
The step of groove, includes：
A protective layer is formed on the finger-cross structure of top layer, and the protective layer only covers the described slotting finger of the top layer
Structure；
Photoresistance is formed on first electrolyte, and the photoresistance exposes first finger and the second finger-like knot
First electrolyte between structure；
With the photoresistance and protective layer as mask, first electrolyte is performed etching to form multiple grooves.
Optionally, in the preparation method of the capacitor, the material of the material of the finger-cross structure and the protective layer
It is identical.
Optionally, in the preparation method of the capacitor, second dielectric dielectric constant is more than 7.
Optionally, in the preparation method of the capacitor, the groove is also located at the first finger-like knot of adjacent layer
Between structure and between second finger of adjacent layer.
Another side of the invention, also provides a kind of capacitor, including：
Substrate, has the finger-cross structure comprising multiple stackings in the first electrolyte, first electrolyte on the substrate,
Each finger-cross structure includes multiple first fingers and multiple second fingers, in the same finger-cross structure
In, first finger and the second finger staggered relative arrangement；
Groove, is formed in first electrolyte, and the first finger-like knot in the same finger-cross structure
Between structure and the second finger；And
Second electrolyte, is filled in the groove, and second dielectric dielectric constant is situated between more than the described first electricity
The dielectric constant of matter.
Optionally, in the capacitor, described second dielectric dielectric constant is more than 7.
Optionally, in the capacitor, the groove be also located between first finger of adjacent layer and
Between second finger of adjacent layer.
Optionally, in the capacitor, the material of the finger-cross structure is metal.
Compared with prior art, capacitor that the present invention is provided and preparation method thereof has advantages below：
In described capacitor and preparation method thereof, the groove is formed at first finger and the second finger-like knot
Between structure, the second electrolyte is filled in the groove, second dielectric dielectric constant is more than first electrolyte
Dielectric constant, so as to increase dielectric dielectric constant between first finger and the second finger, with increase
Breakdown voltage between first finger and the second finger so that before not changing the standard processing procedure of logical device
Put, the capacitance of capacitor can be effectively improved.
Description of the drawings
Fig. 1 is schematic diagram of the MOM capacitor of the prior art when electrolyte is omitted；
Fig. 2 and Fig. 3 is schematic diagram of the MOM capacitor of Fig. 1 when being powered；
Fig. 4 is the flow chart of the preparation method of capacitor in first embodiment of the invention；
Schematic diagrams of the Fig. 5 to Fig. 9 for device architecture in the preparation method of capacitor in first embodiment of the invention；
Schematic diagrams of the Figure 10 to Figure 12 for device architecture in the preparation method of capacitor in second embodiment of the invention；
Schematic diagrams of the Figure 13 to Figure 14 for device architecture in the preparation method of capacitor in third embodiment of the invention.
Specific embodiment
Inventor is had found to prior art research, in the MOM capacitor 1 of prior art, as shown in figure 1, due to described
Dielectric dielectric constant between first finger 11 and the second finger 12 is low so that the breakdown potential of MOM capacitor 1
Pressure drop is low.But, MOM capacitor 1 is typically all integrated in the back-end process of logical device technique, and logical device is in back segment system
Cheng Zhong, using Low-k (low k, general k value less than or equal to 4) material as interlayer dielectric, so, MOM capacitor in prior art
The electrolyte of device 1 is Low-k materials, it is impossible to which directly using high-k, (high k, general k value prepare MOM more than or equal to 7) material
Capacitor 1, because directly prepare the technique and structure that MOM capacitor 1 can change logical device using high-k materials.
Inventor is had found to prior art further investigation, if first logically the standard processing procedure of device prepares Low-k materials
The electrolyte (i.e. the first electrolyte) of material, after the interconnection line processing procedure of back segment terminates, then by first finger 11 and
Between two fingers 12, the electrolyte of Low-k materials changes the electrolyte (i.e. the second electrolyte) of high-k materials into, so exists
On the premise of not changing the standard processing procedure of original logical device, increase the anti-breakdown performance of MOM capacitor.
According to the studies above, the core concept of the present invention is, there is provided a kind of preparation method of capacitor, including following step
Suddenly：
Step S11 a, there is provided substrate, has on the substrate in the first electrolyte, first electrolyte comprising multiple
The finger-cross structure of stacking, each finger-cross structure include multiple first fingers and multiple second fingers,
In the same finger-cross structure, first finger and the second finger staggered relative are arranged；
Step S12, performs etching to first electrolyte to form multiple grooves, and the groove is located at same described slotting
Between first finger and the second finger in finger structure；
Step S13, fills the second electrolyte in the groove, and second dielectric dielectric constant is more than described the
One dielectric dielectric constant.
Using above-mentioned preparation method, dielectric dielectric between first finger and the second finger is increased
Constant, to increase the breakdown voltage between first finger and the second finger so that do not change capacitor volume
On the premise of, the capacitance of capacitor can be effectively improved.
Core concept of the invention, also provides a kind of capacitor, including：
Substrate, has the finger-cross structure comprising multiple stackings in the first electrolyte, first electrolyte on the substrate,
Each finger-cross structure includes multiple first fingers and multiple second fingers, in the same finger-cross structure
In, first finger and the second finger staggered relative arrangement；
Groove, is formed in first electrolyte, and the first finger-like knot in the same finger-cross structure
Between structure and the second finger；And
Second electrolyte, is filled in the groove, and second dielectric dielectric constant is situated between more than the described first electricity
The dielectric constant of matter.
Capacitor of the invention and preparation method thereof is described in more detail below in conjunction with schematic diagram, is wherein represented
The preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still real
The advantageous effects of the existing present invention.Therefore, description below be appreciated that it is widely known for those skilled in the art, and and
Not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In sending out, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to relevant system or relevant business
Limit, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Ask book, advantages and features of the invention become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, only aids in illustrating the purpose of the embodiment of the present invention to convenience, lucidly.
Several embodiments of the capacitor and preparation method thereof are exemplified below, with clear explanation present disclosure, should
When it is clear that, present disclosure is not restricted to following examples, and other are by the routine of those of ordinary skill in the art
The improvement of technological means is also within the thought range of the present invention.
【First embodiment】
Refer to Fig. 4-Fig. 9 and illustrate capacitor of the present invention and preparation method thereof, wherein, Fig. 4 is the present invention first
The flow chart of the preparation method of capacitor in embodiment；Fig. 5 to Fig. 9 is the preparation method of capacitor in first embodiment of the invention
The schematic diagram of middle device architecture.In the present invention, the capacitor is integrated in the back-end process of logical device technique, described to patrol
Collect device to prepare using the advanced logic technology of characteristic size≤90nm.
As shown in figure 4, carry out step S11 first, as shown in Figure 6, there is provided a substrate 100, have the on the substrate 100
One electrolyte 200, the finger-cross structure 210 comprising multiple stackings in first electrolyte 200.In the present embodiment, the lining
Bottom 100 can be silicon substrate or silicon-on-insulator etc..Preparing on the substrate 100 has some interconnection layers, figure 6 illustrates
Four layers of interconnection layer, respectively：First interconnection layer M1, the second interconnection layer M2, the 3rd interconnection layer M3 and the 4th interconnection layer M4.But
It is, it is described to state on substrate 100 number of plies of the interconnection layer and be not specifically limited, in other embodiments of the invention, may be used also
To include three layers, five layers, six layers or more interconnection layers.
The finger-cross structure 210 of four stackings is figure 6 illustrates, respectively in four layers of interconnection layer, but in the present invention
Other embodiments in, first electrolyte 200 also in can comprising two, three, five, or more described slotting refer to knot
Structure 210, and the finger-cross structure 210 is also not limited in each layer of interconnection layer.For example, first electrolyte 200
It is also interior to include three finger-cross structures 210, respectively positioned at the second interconnection layer M2, the 3rd interconnection layer M3 and the 4th
In interconnection layer M4, this be it will be appreciated by those skilled in the art that, will not be described here.
Fig. 5 is the top view of first electrolyte 200, and Fig. 6 is profiles of the Fig. 5 along AA ' lines.As shown in figure 5, each
The finger-cross structure 210 includes multiple first fingers 211 and multiple second fingers 212, same described slotting
In referring to structure 210, first finger 211 and 212 staggered relative of the second finger are arranged.In the present embodiment, institute
Stating finger-cross structure 210 also includes the first connecting line 213 and the second connecting line 214, and first connecting line 213 connects multiple institutes
The first finger 211 is stated, thinks that first finger 211 is powered, second connecting line 214 connects multiple described
Two fingers 212, think that second finger 212 is powered.Preferably, the material of the finger-cross structure 210 is metal,
Such as metallic copper etc..In other embodiments of the invention, the material of the finger-cross structure 210 can also be the materials such as polysilicon
Material.General, the material of first electrolyte 200 is low-k materials, for example, electricity Jie of the material of first electrolyte 200
Matter is less than or equal to 4, preferably 2.3,2.4 etc..
As shown in fig. 6, also there is between first electrolyte 200 and substrate 100 etching stop layer 110, it is general,
The material of the etching stop layer 110 is silicon nitride or carbonitride of silicium etc..In addition, per described the between adjacent two interconnection layer
One electrolyte 200 also includes a protective layer 220, general, and the material of the protective layer 220 is silicon nitride or carbonitride of silicium etc.
Deng.
Then, carry out step S12, first electrolyte 200 is performed etching to form multiple grooves, specifically,
The present embodiment includes：
As shown in fig. 7, forming photoresistance 300 on first electrolyte 200, the photoresistance 300 exposes described first
First electrolyte 200 between finger 211 and the second finger 212；
It is as first finger 211 between different layers stacks gradually arrangement and described between different layers
Second finger 212 stacks gradually arrangement, so, the finger-cross structure 210 with the photoresistance 300 and top layer as mask,
When performing etching to described first electricity Jie 200, as shown in figure 8, multiple grooves 230 can be formed, the groove 230 is located at same
Between first finger 211 and the second finger 212 in the finger-cross structure 210.The etching is carved for dry method
Erosion (anisotropic etching), such as reactive ion etching (RIE, full name Reactive Ion Etching), etching stopping is in institute
State on etching stop layer 110, form the groove 230.
Then, step S13 is carried out, fills the second electrolyte 240 in the groove 230, second electrolyte 240
Dielectric constant is more than described first dielectric dielectric constant.Optionally, the dielectric constant of second electrolyte 240 is more than 7,
For example, 10,25,28 etc., specific material can be selected as needed.
Through above-mentioned preparation process, capacitor 2 as shown in Figure 9 is defined, including：Substrate 100, on the substrate 100
With the first electrolyte 200, the finger-cross structure 210 comprising multiple stackings in first electrolyte 200, each slotting finger are tied
Structure 210 includes multiple first fingers 211 and multiple second fingers 212, in the same finger-cross structure 210
In, first finger 211 and 212 staggered relative of the second finger arrangement；Groove 230, is formed at described first electric
In medium 200, and first finger 211 and the second finger 212 in the same finger-cross structure 210 it
Between；Second electrolyte 240, is filled in the groove 230.
As shown in figure 9, in the present embodiment, in the same finger-cross structure, first finger 211 and second
The electric field of finger 212 is different, and one of them is negative electricity, and another is positive electricity；First finger of adjacent two layers
211 electric field is identical；The electric field of second finger 212 of adjacent two layers is identical.Then electric capacity C4 is formed at described first
Between finger 211 and the second finger 212, the electric field of electric capacity C4 is transverse electric field.Due to second electrolyte 240
It is filled in the groove 230, so as to increased electrolyte between first finger 211 and the second finger 212
Dielectric constant, to increase the breakdown voltage between first finger 211 and the second finger 212 so that do not change
On the premise of 2 volume of variodenser, the capacitance of capacitor 2 can be effectively improved.
【Second embodiment】
Figure 10-Figure 12 is referred to, Figure 10 to Figure 12 is device in the preparation method of capacitor in second embodiment of the invention
The schematic diagram of structure.In figs. 10-12, reference number is represented and the statement of Fig. 6-Fig. 9 identicals and first embodiment identical
Structure.The preparation method of the second embodiment is essentially identical with the preparation method of the first embodiment, and its difference is：Step
Rapid S12 specifically includes：
As shown in Figure 10, a protective layer 400 is formed on the finger-cross structure 210 of top layer, and the protective layer 400 only covers
Cover the finger-cross structure 210 of the top layer.Preferably, the material of the material of the finger-cross structure 210 and the protective layer 400
Identical, for example, in the present embodiment, the material of the finger-cross structure 210 is metallic copper, then can adjust chemical vapor deposition
One layer of copper of process deposits so that the protective layer 400 is only grown on the finger-cross structure 210, without being grown in described
On one electrolyte 200.400 specific growth technique of the protective layer be it will be understood by those skilled in the art that,
This does not repeat；
As shown in figure 11, the formation photoresistance 300 on first electrolyte 200, the photoresistance 300 expose described first
First electrolyte 200 between finger 211 and the second finger 212；
As shown in figure 12, with the photoresistance 300 and protective layer 400 as mask, first electrolyte 200 is performed etching
It is to form multiple grooves 230, described to etch as dry etching (anisotropic etching), such as reactive ion etching (RIE, full name
Reactive Ion Etching)。
The groove 230 can also be formed using the method for the present embodiment, the protective layer 400 can protect the institute of top layer
Finger-cross structure 210 is stated, the thickness of the protective layer 400 can be adjusted so that after performing etching, the protective layer 400 can be just
It is removed well.
【3rd embodiment】
Figure 13-Figure 14 is referred to, Figure 13-Figure 14 is device junction in the preparation method of capacitor in third embodiment of the invention
The schematic diagram of structure.In Figure 13-Figure 14, reference number is represented to be tied with the statement of Fig. 6-Fig. 9 identicals and first embodiment identical
Structure.The preparation method of the 3rd embodiment is essentially identical with the preparation method of the first embodiment, and its difference is：In step
In rapid S12, as shown in figure 13, the groove 330 is also located between first finger 211 of adjacent layer and adjacent layer
Second finger 212 between.General can adopt isotropic etching, and such as wet etching is described to be formed
Groove 330.
Carried out in step S12 afterwards, second electrolyte also fill up in adjacent layer first finger 211 it
Between and second finger 212 of adjacent layer between.
In the capacitor 3 for being formed in the present embodiment, in the same finger-cross structure, first finger
211 is different with the electric field of the second finger 212, and one of them is positive electricity, and another is negative electricity；Described the first of adjacent two layers
The electric field of finger 211 is different, and one of them is positive electricity, and another is negative electricity；Second finger of adjacent two layers
212 electric field is different, and one of them is positive electricity, and another is negative electricity.Then electric capacity C5 is formed at 211 He of the first finger
Between second finger 212, the electric field of electric capacity C5 is transverse electric field.Electric capacity C6 is formed at first finger-like of adjacent two layers
Between structure 211 or between second finger 212 of adjacent two layers, the electric field of electric capacity C6 is longitudinal electric field.Electric capacity C5
Increase with the electrolyte of electric capacity C6, the capacitance of electric capacity C5 and electric capacity C6 is increased simultaneously.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of preparation method of capacitor, including：
One substrate is provided, there is on the substrate the slotting finger knot comprising multiple stackings in the first electrolyte, first electrolyte
Structure, each finger-cross structure include multiple first fingers and multiple second fingers, in the same slotting finger
In structure, first finger and the second finger staggered relative are arranged；
First electrolyte is performed etching to form multiple grooves, the groove is located at the institute in the same finger-cross structure
State between the first finger and the second finger；And
The second electrolyte is filled in the groove, and second dielectric dielectric constant is more than described first dielectric Jie
Electric constant.
2. the preparation method of capacitor as claimed in claim 1, it is characterised in that first electrolyte is performed etching with
The step of forming multiple grooves includes：
Form photoresistance on first electrolyte, the photoresistance expose first finger and the second finger it
Between first electrolyte；
The finger-cross structure with the photoresistance and top layer is performed etching to first electrolyte multiple recessed to be formed as mask
Groove.
3. the preparation method of capacitor as claimed in claim 1, it is characterised in that first electrolyte is performed etching with
The step of forming multiple grooves includes：
A protective layer is formed on the finger-cross structure of top layer, and the protective layer only covers the described slotting finger knot of the top layer
Structure；
Form photoresistance on first electrolyte, the photoresistance expose first finger and the second finger it
Between first electrolyte；
With the photoresistance and protective layer as mask, first electrolyte is performed etching to form multiple grooves.
4. the preparation method of capacitor as claimed in claim 3, it is characterised in that the material of the finger-cross structure and the guarantor
The material of sheath is identical.
5. the preparation method of the capacitor as described in any one in Claims 1 to 4, it is characterised in that second electricity is situated between
The dielectric constant of matter is more than 7.
6. the preparation method of the capacitor as described in any one in Claims 1 to 4, it is characterised in that the groove also position
Between first finger of adjacent layer and between second finger of adjacent layer.
7. a kind of capacitor, including：
Substrate, has the finger-cross structure comprising multiple stackings in the first electrolyte, first electrolyte on the substrate, each
The finger-cross structure includes multiple first fingers and multiple second fingers, in the same finger-cross structure,
First finger and the arrangement of the second finger staggered relative；
Groove, is formed in first electrolyte, and first finger in the same finger-cross structure and
Between second finger；And
Second electrolyte, is filled in the groove, and second dielectric dielectric constant is dielectric more than described first
Dielectric constant.
8. capacitor as claimed in claim 7, it is characterised in that second dielectric dielectric constant is more than 7.
9. capacitor as claimed in claim 7, it is characterised in that the groove is also located at the first finger-like knot of adjacent layer
Between structure and between second finger of adjacent layer.
10. capacitor as claimed in claim 7, it is characterised in that the material of the finger-cross structure is metal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410487164.1A CN104269394B (en) | 2014-09-22 | 2014-09-22 | Capacitor and manufacturing method thereof |
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|---|---|---|---|
| CN201410487164.1A CN104269394B (en) | 2014-09-22 | 2014-09-22 | Capacitor and manufacturing method thereof |
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| CN104269394B true CN104269394B (en) | 2017-03-22 |
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| CN104934410B (en) * | 2015-05-08 | 2017-10-24 | 武汉新芯集成电路制造有限公司 | A kind of MOM capacitor and electric capacity method of adjustment |
| JP6747473B2 (en) * | 2018-06-13 | 2020-08-26 | Tdk株式会社 | Non-reciprocal circuit device and communication device using the same |
| CN111029327B (en) * | 2019-12-25 | 2023-11-07 | 上海集成电路研发中心有限公司 | Semiconductor structure and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002270771A (en) * | 2001-03-09 | 2002-09-20 | Hitachi Ltd | Method for manufacturing semiconductor device |
| CN101533838A (en) * | 2008-03-10 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Mom capacitors integrated with air-gaps |
| CN102983117A (en) * | 2011-09-07 | 2013-03-20 | 台湾积体电路制造股份有限公司 | Horizontal interdigitated capacitor structure with vias |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001188A1 (en) * | 2001-06-27 | 2003-01-02 | Nakagawa Osamu Samuel | High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems |
| US8836079B2 (en) * | 2013-01-24 | 2014-09-16 | Qualcomm Incorporated | Metal-on-metal (MoM) capacitors having laterally displaced layers, and related systems and methods |
-
2014
- 2014-09-22 CN CN201410487164.1A patent/CN104269394B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002270771A (en) * | 2001-03-09 | 2002-09-20 | Hitachi Ltd | Method for manufacturing semiconductor device |
| CN101533838A (en) * | 2008-03-10 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Mom capacitors integrated with air-gaps |
| CN102983117A (en) * | 2011-09-07 | 2013-03-20 | 台湾积体电路制造股份有限公司 | Horizontal interdigitated capacitor structure with vias |
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