CN104267244B - A kind of integration ratio circuit and the impedance measurement method based on integration ratio circuit - Google Patents

Abstract

A kind of integration ratio circuit and the impedance measurement method based on integration ratio circuit that the present invention is provided, it is capable of achieving the ratio of the DC component of two combined-voltage signals of measurement, impedance measurement is converted to into the ratio of measurement voltage DC component, the certainty of measurement of impedance is greatly improved.The integration ratio circuit of the present invention, including operational amplifier, integral amplifier, comparator；The positive input terminal of operational amplifier is respectively by four switch connection measured signals, the positive-negative output end of standard voltage source and ground potentials, the outfan of operational amplifier is connected with negative input end, and by the negative input end of current-limiting resistance connection integral amplifier, the outfan of integral amplifier connects the positive input terminal of comparator；Connect integrating capacitor between the negative input end and outfan of integral amplifier, the two ends of integrating capacitor have charge switch；The positive input terminal connection forward end reference voltage of integral amplifier, the negative input end connection negative end reference voltage of comparator.

Description

Integral proportional circuit and impedance measurement method based on integral proportional circuit

Technical Field

The invention relates to the technical field of alternating current measurement, in particular to an integral proportional circuit and an impedance measurement method based on the integral proportional circuit.

Background

Impedance is a general term for the resistance, inductance and capacitance of the circuit to the alternating current. Impedance extends the concept of resistance into the field of alternating current circuits, describing not only the relative amplitudes of voltage and current, but also their relative phases. When the current through the circuit is dc, the resistance is equal to the impedance, and the resistance can be regarded as an impedance with zero phase. The impedance is usually marked by the symbol Z, and according to the active definition of the impedance, the impedance is complex, is the ratio of complex voltage to complex current, i.e. Z ═ U/I, and may also be in phasor Z_m< theta or Z_me^jθTo represent; wherein Z is_mThe expression "phasor representation" refers to a table in which the magnitude of impedance is the absolute value ratio of the voltage amplitude to the current amplitude, and θ represents the phase of impedance and the phase difference between voltage and current.

At present, methods for measuring impedance mainly comprise a bridge method, a resonance method and a vector impedance method, wherein the basic working principle of the bridge method is based on a four-arm bridge circuit, but the bridge method needs to repeatedly perform balance adjustment, is complex and time-consuming in operation method, is limited in measurement range, and is difficult to realize quick automatic measurement; the resonance method is based on the resonance characteristic of the LC loop, the impedance to be tested is calculated by measuring the resonance frequency and the known inductance or capacitance, the vector impedance method is based on the definition of the impedance, the voltage of a test signal is added to the tested piece, the current of the test signal flows through the tested piece, and the impedance of a test end is calculated according to the ratio of the voltage and the current; however, these measurement methods require that the excitation signal is a low-distortion sine wave signal, however, a low-distortion sine wave signal with a high frequency is difficult to obtain, which limits the improvement of the impedance measurement accuracy and the expansion of the measurement range.

In recent years, with the progress of science and technology, methods for measuring impedance are being developed to the levels of digitization, intelligence and programming, so as to improve the measurement accuracy and the measurement range of impedance. Dual-integration circuits are currently used for impedance measurements, the basic principle of which is to convert a measurement of an impedance parameter into a measurement of a voltage quantity. However, most of the currently used double-integration circuits for measuring impedance adopt a double-integration circuit for directly measuring direct-current voltage, four voltage values are respectively measured and then calculated, and because the four voltage values have indefinite polarities and are positive and negative and are respectively measured by a positive voltage source and a negative voltage source, the positive voltage source, the negative voltage source and the integrated initial voltage are easily influenced by long-term drift and temperature and humidity change of the positive voltage source, the negative voltage source and the integrated initial voltage, and the accuracy of the measured value is further influenced.

Disclosure of Invention

The invention provides an integral proportion circuit and an impedance measurement method based on the integral proportion circuit, which can realize the measurement of the proportion of a direct current component, convert the impedance measurement into the proportion of a measurement voltage direct current component and greatly improve the measurement precision of impedance; the integral proportional circuit can be widely used for instruments which need to test the relation between the amplitude and the phase of two voltages, such as an impedance tester, a power analyzer, a phase meter, a phase angle meter and the like.

The technical scheme of the invention is as follows:

1. an integral proportional circuit is used for measuring the proportion of direct current components of two alternating current and direct current voltage signals and is characterized by comprising an operational amplifier, an integral amplifier and a comparator; the positive input end of the operational amplifier is connected with the signal to be detected, the positive and negative output ends of the standard voltage source and the ground potential through a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4 respectively, the output end of the operational amplifier is connected with the negative input end and is connected with the negative input end of the integrating amplifier through an integrating resistor R, and the output end of the integrating amplifier is connected with the positive input end of the comparator; the integration is connected between the negative input end and the output end of the integrating amplifierA capacitor, two ends of the integration capacitor are provided with a charging switch SW 0; the positive input end of the integrating amplifier is connected with a positive end reference voltage U_REF1The negative input end of the comparator is connected with a negative end reference voltage U_REF2。

2. The impedance measurement method based on the integral proportional circuit is characterized in that the in-phase component U of an alternating voltage signal of the impedance to be measured in a reference orthogonal coordinate system is measured_1aAnd the orthogonal component U_1bAnd the in-phase component U of the AC voltage signal of the standard impedance in the reference orthogonal coordinate system_2aAnd the orthogonal component U_2bThe impedance measurement is converted into the proportion of the direct current component of the measurement voltage, and the specific steps are as follows:

step 1), firstly, determining a forward end reference voltage U connected with a positive input end of an integrating amplifier_REF1A negative end reference voltage U connected with the negative input end of the comparator_REF2The size of (d);

step 2), measuring to obtain a forward end reference voltage U connected with the positive input end of the integrating amplifier_REF1A negative end reference voltage U connected with the negative input end of the comparator_REF2Integral initial voltage U_sThe proportional relationship between the two;

step 3), respectively measuring to obtain the in-phase component U of the alternating voltage signal of the impedance to be measured in the reference orthogonal coordinate system_1aQuadrature component U_1bIn-phase component U of standard impedance alternating current voltage signal in reference orthogonal coordinate system_2aQuadrature component U_2bAnd the forward end reference voltage U_REF1Negative end reference voltage U_REF2Integral initial voltage U loaded on integral resistor R_sThe proportional relationship between the two;

step 4), utilizing the results obtained in the step 2) and the step 3), and obtaining the result according to a formula

And calculating to obtain the measured impedance.

3. In the step 1), determining a forward end reference voltage U_REF1And negative terminal reference voltage U_REF2The method comprises the following specific steps:

when the fourth switch SW4 connected to ground potential is closed and the other switches are open, U is selected_REF1So that the charging direction of the capacitor C is always positive or negative, i.e. U_GND+V_OS1-U_eConstant positive or constant negative; during charging:

U_e＝U_REF1+V_OS2+I_B2·R+I_SW0·R

V_OS1、V_OS2-bias voltages of the operational amplifier and the integrating amplifier;

I_B2-bias current of the operational amplifier;

I_SW0split into leakage currents for the closed and open condition of switch SW 0;

likewise, U is selected_REF2So that the voltage difference between the positive input voltage and the negative input voltage of the comparator A3 is constantly positive or constantly negative in the integral zero clearing state; namely U_REF2-V_OS3-U_eConstant positive or constant negative, Vos₃Is the bias voltage of the comparator.

4. In the step 2), the measurement process selects the integral direction as U_GND+V_OS1-U_e>0，U_REF2-V_OS3-U_e>0, comprising the steps of:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) first stageSW3 is closed and the remaining switches are open, with capacitor C and (U)_REF--U_s)/R<Current charging of 0, integrating amplifier output voltage U₁Rising to the inversion of the comparator, ending the stage which is used for providing an integration starting point for integration;

c) in the second stage, SW4 is closed, the other switches are opened, and after SW4 is closed, timing is started, and at this time, the capacitor C is connected with (U)_GND-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₁At this stage U₁The voltage is reduced;

d) in the third phase, SW3 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₂And the stage is finished;

e) in the fourth stage, SW2 is closed, the other switches are opened, and the time is started after SW2 is closed, and then the capacitor is started to be (U)_REF+-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₃At this stage U₁The voltage is reduced;

f) in the fifth stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₄And the stage is finished;

wherein: u shape_REF+、U_REF-The positive and negative ends of the standard voltage source output voltages respectively.

5. In the step 2), the measured t1, t2, t3 and t4,

according to the conservation of charge, the second stage and the third stage can obtain:

get U_GNDWhen 0, we can get:

according to the conservation of charge, the fourth stage and the fifth stage can obtain:

namely, it is

Order to

U_REF+＝a·U_REF-(15)

In the formula:

order to

U_s＝b·U_REF-(17)

In the formula:

6. in the step 3), when U is formed_in-U_s>At 0, the whole integration is divided into four stages:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) in the second phase, SW1 is closed and the remaining switches are opened, with the capacitor turned on (U)_in-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₅At this stage U₁The voltage is reduced; due to U_inThe signal being a superimposed AC-DC signal, t being for filtering out AC components thereof₅Is an integer multiple of its AC component period, in this case according to U_oPolarity judgment U of voltage_in-U_sThe polarity of (1);

d) in the third phase, SW3 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₆And the stage is finished.

7. In the step 3), according to the measured t5 and t6,

according to the principle of charge conservation, the second stage and the third stage can be used

Combined type (15), (16), (17), (18)

The following can be obtained:

order to

U_in＝c·U_REF-(19)

In the formula:

8. in the step 3), when U is formed_in-U_s<At 0, the whole integration is divided into five stages:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) in the second phase, SW1 is closed and the remaining switches are opened, with the capacitor turned on (U)_in-U_s)/R<0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₅At this stage U₁The voltage rises; due to U_inThe signal being a superimposed AC-DC signal, t being for filtering out AC components thereof₅Is an integer multiple of its AC component period, in this case according to U_oPolarity judgment U of voltage_in-U_sThe polarity of (1);

d) in the third phase, SW2 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF+-U_s)/R>Current charging of 0, U₁The voltage drops to the inverse of the comparator, and then the charging is continued for a short time t₀Total integration time of t₆And the stage is finished;

e) in the fourth stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₇And the stage is finished.

9. In the step 3), according to the measured t5, t6 and t7,

based on the principle of conservation of charge, the second, third and fourth stages

Combined type (15), (16), (17), (18)

Namely:

let U_in＝c·U_REF-(22)

In the formula:

the invention has the technical effects that:

1. the invention provides an integral proportional circuit which is used for measuring the proportion of direct current components of two alternating current and direct current voltage signals, respectively charges and discharges an integral capacitor at different integral stages based on a charge balance principle, controls integral time, filters the alternating current components and realizes the measurement of the proportion of the direct current components. The measurement errors of the offset voltage, the bias current and the temperature drift of the operational amplifier and the leakage current of the analog switch on the integrating circuit are eliminated by multiple times of integration, and the measurement precision is improved.

2. The invention provides an impedance measurement method based on an integral circuit, which uses an integral proportional circuit to convert impedance measurement into the proportion of a measurement voltage direct-current component, thereby realizing high-precision impedance measurement. The method firstly measures the proportion among the positive voltage source, the negative voltage source and the integral initial voltage, and then measures the proportion among the four measured voltages, the positive voltage source, the negative voltage source and the integral initial voltage to obtain the proportion among the four measured voltages, eliminates the influence of the long-term drift of the device on the measurement result, and can consider that the external environments such as the temperature and the humidity of the system are basically unchanged because the measurement time is very short (within 1s or shorter time), thereby eliminating the influence of the external environments on the measurement and improving the accuracy of the measurement result.

3. The integral proportional circuit and the impedance measurement method based on the integral proportional circuit can be widely used for testing and measuring capacitance, inductance, resistance and any impedance of 100 Hz-1 MHz, and the quadrature demodulation method based on the integral proportional circuit and the circuit can be widely used for instruments which need to test the relation between the amplitude and the phase of two voltages, such as an impedance tester, a power analyzer, a phase meter, a phase angle meter and the like. Therefore, based on the technical scheme provided by the invention, the various instruments can be developed.

Drawings

Fig. 1 is a circuit diagram of an integral proportional circuit of the present invention.

FIG. 2 shows a measurement U of the method of the invention_REF1、U_REF2、U_sAn integration time sequence diagram of the proportional relation between.

FIG. 3 shows a measurement U of the method of the invention_1a、U_1b、U_2a、U_2bAnd U_REF1、U_REF2、U_sOne of the integration time sequence diagrams (U) of the proportional relation between_in-U_s>0)。

FIG. 4 shows a measurement U of the method of the invention_1a、U_1b、U_2a、U_2bAnd U_REF1、U_REF2、U_sSecond integration time sequence diagram (U) of proportional relation between_in-U_s<0)。

Detailed Description

The embodiments of the present invention will be further described with reference to the accompanying drawings.

As shown in fig. 1, the circuit diagram of the integral proportional circuit of the present invention is capable of measuring the proportion of the dc component of two ac/dc voltage signals, that is, the proportion between the dc components of the in-phase component and the quadrature component of two ac voltage signals having dc components in the reference coordinate system. An integral proportional circuit comprises an operational amplifier, an integral amplifier and a comparator; the positive input end of the operational amplifier is connected with a signal to be measured, the positive and negative output ends of a standard voltage source and the ground potential through a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4 respectively, the output end of the operational amplifier is connected with the negative input end and is connected with the negative input end of the integrating amplifier through an integrating resistor R, the output end of the integrating amplifier is connected with the positive input end of the comparator, an integrating capacitor is connected between the negative input end and the output end of the integrating amplifier, and two ends of the integrating capacitor are provided with a charging switch SW 0; the positive input end of the integrating amplifier is connected with a positive end reference voltage U_REF1The negative input end of the comparator is connected with a negative end reference voltage U_REF2。

Drawing (A)₁In, U_REF+、U_REF-Positive and negative standard voltage sources respectively; u shape_inFor the signal under test, i.e. U_inIs U_1a、U_1b、U_2a、U_2bOne of the four, U_1aIs the in-phase component, U, of the first measured signal in a reference orthogonal coordinate system_1bIs the orthogonal component, U, of the first measured signal in the reference orthogonal coordinate system_2aIs the in-phase component, U, of the second measured signal in the reference orthogonal coordinate system_2bOrthogonal components of a second measured signal under a reference orthogonal coordinate system are obtained; GND is ground potential; the operational amplifier A1 is a cache amplifier; a2 is an integrating amplifier; a3 is a comparator; u shape_REF1Is a2 positive terminal reference voltage; u shape_REF2Is A3 negative terminalA reference voltage.

The impedance measurement method based on the integral proportion circuit is used for measuring the proportion of in-phase components and orthogonal components of alternating current voltage signals of measured impedance in a reference orthogonal coordinate system and the proportion of direct current components between the in-phase components and the orthogonal components of the alternating current voltage signals of standard impedance in the reference orthogonal coordinate system, and converting the impedance measurement into the proportion of direct current components of measured voltage.

According to the measurement principle of the phasor orthogonal decomposition proportion method, the measured impedance and the standard impedance pass through the same current, and then the voltage signal on the measured impedance and the voltage signal on the standard impedance are taken for processing and analysis to obtain the information of the measured impedance.

Let the measured impedance upper voltage signal and the standard impedance upper voltage signal be u₁And u₂The voltage phasor in the reference orthogonal coordinate system can be expressed as:

wherein,are respectively an AC voltage u₁And u₂Voltage phasors, U, in a reference orthogonal coordinate system_1a、U_1bAre respectively an AC voltage u₁In-phase and quadrature components, U, in a reference orthogonal coordinate system_2a、U_2bAre respectively AC voltage and u₂An in-phase component and a quadrature component in a reference orthogonal coordinate system.

And multiplying a pair of orthogonal basis functions on a reference coordinate system with the measured signal respectively to obtain the in-phase or orthogonal component of the measured signal. Setting the signal u to be measured₁The time domain expression of (a):

u₁(t)＝Asin(ωt+θ) (3)

in the formula, A is u₁ω is u₁At an angular frequency of (e), theta being u₁The initial phase of (a).

The time domain expression of a pair of orthogonal basis functions of a reference coordinate system is:

u_a(t)＝sin(ωt) (4)

the orthogonal basis function is unit amplitude, and the angular frequency must be equal to u₁The orthogonal basis functions are multiplied with the measured signals respectively:

similar availabilityAnd (3) filtering the terms of the upper two-equation band 2 ω t by using a low-pass filter to obtain the in-phase component or the orthogonal component of the measured signal on the reference coordinate system:

the same principle can obtain U_2aAnd U_2bThe measured impedance can be calculated:

according to the principle, the key point of measuring the impedance is to measure the in-phase component and the quadrature component U_1a、U_1b、U_2a、U_2bThe direct current component in between.

The method comprises the following specific steps:

step 1), firstly, determining a forward end reference voltage U connected with a positive input end of an integrating amplifier_REF1A negative end reference voltage U connected with the negative input end of the comparator_REF2The size of (d);

step 2), measuring to obtain a forward end reference voltage U connected with the positive input end of the integrating amplifier_REF1A negative end reference voltage U connected with the negative input end of the comparator_REF2Integral initial voltage U loaded on integral resistor R_sThe proportional relationship between the two;

step 3), respectively measuring to obtain the in-phase component U of the alternating voltage signal of the impedance to be measured in the reference orthogonal coordinate system_1aQuadrature component U_1bIn-phase component U of standard impedance alternating current voltage signal in reference orthogonal coordinate system_2aQuadrature component U_2bAnd the forward end reference voltage U_REF1Negative end reference voltage U_REF2Integral initial voltage U loaded on integral resistor R_sThe proportional relationship between the two;

step 4), utilizing the results obtained in the step 1) and the step 2), and obtaining the result according to a formula

And calculating to obtain the measured impedance.

In general, in the basic integration circuit, U_REF1And U_REF2At ground potential, this method has the following problems:

1、U_REF1ground potential: so that when SW4 is closed and the other switches are open, the capacitor charge direction may be positive or negative, requiring additional integration time to determine its charge direction.

2、U_REF2Ground potential: so that the output voltage of the comparator a3 after being cleared can be positive or negative, which brings trouble to the selection of the integration voltage.

Therefore, before the start of the integration measurement process, the reference voltage U is first applied_REF1And U_REF2Determining the voltage value in advance, and selecting U_REF1So that when SW4 is closed, the direction of capacitor charging is determined and U is selected_REF2The value determination clears the a3 output voltage. The specific determination method is as follows:

when SW4 is closed and the other switches are open, U is selected in consideration of system drift_REF1So that the charging direction of the capacitor C is always positive or negative, i.e. U_GND+V_OS1-U_eEither constant positive or constant negative. During charging:

U_e＝U_REF1+V_OS2+I_B2·R+I_SW0·R (10)

V_OS1、V_OS2bias voltages of the operational amplifier 1 and the operational amplifier 2;

I_B2-bias current of the operational amplifier;

I_SW0a division into leakage currents in the closed and open condition of the switch, since this current is small and is pairedThe system index has no effect and is not distinguished in the formula.

Since the larger the absolute value of this voltage, the slower the measurement speed, it is usually appropriate to select it to be several tens mV to several hundreds mV, while its absolute value is smaller than U_REF+And U_REF-。

The voltage is U_GND+V_OS1-U_eIt can be seen from the formula that the value is influenced by multiple factors, and it is theoretically best to zero, but due to the long-term drift and environmental changes of the device, the value will also drift, and the drift size is influenced by the selected device and environmental changes, if the value is zero when the device is delivered from factory, the value influenced by the long-term drift may be larger than zero and may be smaller than zero. The drift is determined by the variation of the environmental factors such as the drift of the selected device and the system temperature, and generally, the drift is between several mV and tens of mV, but may be larger or smaller values, but the formula is not changed. In selecting U_REF1In time, U is calculated according to the device manual and the working environment change thereof_GND+V_OS1-U_eMaximum drift of in the guarantee of U_GND+V_OS1-U_eSelecting U under the premise of constant positive or constant negative_REF1And make U_GND+V_OS1-U_eIs as small as possible and a corresponding margin is left, since an excessive absolute value would reduce the measurement speed.

Likewise, U is selected_REF2So that the voltage difference between the positive input voltage and the negative input voltage of the comparator A3 is constantly positive or constantly negative in the integral zero clearing state; namely U_REF2-V_OS3-U_eEither constant positive or constant negative. The larger the absolute value of this voltage, the slower the measurement speed, so it is generally appropriate to choose it from tens of mV to hundreds of mV, the absolute value of which is less than U_REF+And U_REF-。

Similarly, this voltage refers to U_REF2-V_OS3-U_eThe formula shows that the value of the device is influenced by multiple factors, and theoretically, the value of the device is optimally adjusted to zero, but the device is subjected to long-term driftAnd environmental changes, the value of which may also drift, the magnitude of which is affected by the selected device and environmental changes, and if factory adjusted to zero, the value of which may be greater than zero and may be less than zero due to long-term drift. The drift is determined by the variation of the environmental factors such as the drift of the selected device and the system temperature, and generally, the drift is between several mV and tens of mV, but may be larger or smaller values, but the formula is not changed. In selecting U_REF2In time, U is calculated according to the device manual and the working environment change thereof_REF2-V_OS3-U_eMaximum drift of in the guarantee of U_REF2-V_OS3-U_eSelecting U under the premise of constant positive or constant negative_REF2And make U_REF2-V_OS3-U_eIs as small as possible and a corresponding margin is left, since an excessive absolute value would reduce the measurement speed.

The whole measuring process is divided into two steps, wherein the first step is measuring U_REF+、U_REF-、U_sIn the second step of measuring U separately_1a、U_1b、U_2a、U_2bAnd U_REF+、U_REF-、U_sThe proportional relation between the two can be calculated to obtain U_1a、U_1b、U_2a、U_2bThe proportional relationship between them.

According to U_REF1And U_REF2The difference in selection can occur in four cases:

U_GND+V_OS1-U_e>0，U_REF2-V_OS3-U_e>0；

U_GND+V_OS1-U_e>0，U_REF2-V_OS3-U_e<0；

U_GND+V_OS1-U_e<0，U_REF2-V_OS3-U_e>0；

U_GND+V_OS1-U_e<0，U_REF2-V_OS3-U_e<0；

the four cases differ in the measurement process in that the selected integration direction is different, but the basic principle is the same, now U is used_GND+V_OS1-U_e>0，U_REF2-V_OS3-U_e>0 illustrates the integration process:

the first step is as follows: measurement U_REF+、U_REF-、U_sProportional relationship between them

Note: u shape_s＝U_e-V_OS1

a) And (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) in the second phase, SW4 is closed and the remaining switches are opened, with the capacitor turned on (U)_GND-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₁At this stage U₁The voltage is reduced;

the method of selecting the integration time is as follows:

SW4 is closed and timing is started, with timing selected in relation to the selected clock and the required resolution, while reducing the effect of the ac component. The count value of the counter determines the resolution of the system, if the index is 10^-4The count value is then more than ten times the target resolution, e.g. 10⁵～10⁶Time-clock cycle × count value, to prevent leakage of the integrating capacitor itself, a teflon capacitor with low leakage current is used on one hand, and the integration time does not exceed 0.1s on the other hand, and the integration time should be an integral multiple of the measured signal cycle/2(because the system frequency can be set, it is a known condition) to eliminate the influence of the alternating current component of the measured signal on the measurement, so as to achieve the purpose of filtering the alternating current component.

d) In the third phase, SW3 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₂And the stage is finished;

e) in the fourth stage, SW2 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF+-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₃At this stage U₁The voltage is reduced;

after SW2 is closed, timing is started, the count value of the counter determines the resolution of the system, if the index is 10^-4The count value is then more than ten times the target resolution, e.g. 10⁵～10⁶In order to prevent leakage of the integrating capacitor, a polytetrafluoroethylene capacitor with small leakage current is used on one hand, and the integrating time does not exceed 0.1s on the other hand, and the integrating time is an integral multiple of the measured signal period/2 (since the system frequency can be set, the system frequency is a known condition);

f) in the fifth stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₄And the stage is finished.

Note: the positive and negative current for charging the capacitor determines the charging direction of the capacitor, and U is used for charging with negative current₁Increasing and vice versa.

According to the conservation of charge, the second stage and the third stage can obtain:

get U_GNDWhen 0, we can get:

according to the conservation of charge, the fourth stage and the fifth stage can obtain:

namely, it is

Order to

U_REF+＝a·U_REF-(15)

In the formula:

order to

U_s＝b·U_REF-(17)

In the formula:

the second step is that: measurement U_1a、U_1b、U_2a、U_2bAnd U_REF+、U_REF-、U_sThe proportional relationship between:

for an integrating circuit, measuring the four voltage values is the same for the integrating circuitNeed to be measured in sequence, and now give the measured voltage U_inTiming diagram of (2):

by U_in-U_sCan divide the integration process into two cases, the first case U_in-U_s>0, as shown in FIG. 3, second case U_in-U_s<0, as shown in FIG. 4:

first case U_in-U_s>0: the whole integration can be divided into four phases, wherein the zero clearing phase is not shown in the figure:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) in the second phase, SW1 is closed and the remaining switches are opened, with the capacitor turned on (U)_in-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₅At this stage U₁The voltage rises; due to U_inThe signal being a superimposed AC-DC signal, t being for filtering out AC components thereof₅Which is an integer multiple of the period of its alternating current component. At this time according to U_oPolarity judgment U of voltage_in-U_sThe polarity of (1);

d) in the third phase, SW3 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₆And the stage is finished.

According to the principle of charge conservation, the second stage and the third stage can be used

Combined type (15), (16), (17), (18)

The following can be obtained:

order to

U_in＝c·U_REF-(19)

In the formula:

second case U_in-U_s<0, the whole integration can be divided into five phases, wherein the zero clearing phase is not shown in the figure:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) in the second phase, SW1 is closed and the remaining switches are opened, with the capacitor turned on (U)_in-U_s)/R<0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₅At this stage U₁The voltage rises; due to U_inThe signal being a superimposed AC-DC signal, t being for filtering out AC components thereof₅Which is an integer multiple of the period of its alternating current component. At this time according to U_oPolarity judgment U of voltage_in-U_sThe polarity of (1);

d) third stage, SW2 closed, the rest openOff, when the capacitor is turned off_REF+-U_s)/R>Current charging of 0, U₁The voltage drops to the inverse of the comparator, and then the charging is continued for a short time t₀Total integration time of t₆And the stage is finished.

e) In the fourth stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₇And the stage is finished.

The reason why the timing is not ended when the comparator is inverted in the third stage is to reduce the error caused by the inconsistent transmission delay of the comparator in different directions and at different slew rates. Because the comparator brings the error from different direction reversals, can make the index decline, and after recharging a period of time, cooperate with the fourth stage, make the starting point of the integral the comparator is from the same direction, the reversal of the same slew rate is got out, dispel the error brought by the delay inconsistency of two reversals of the comparator to the greatest extent.

Based on the principle of conservation of charge, the second, third and fourth stages

Combined type (15), (16), (17), (18)

Namely:

let U_in＝c·U_REF-(22)

In the formula:

after the second step, U can be obtained from the formulae (19), (20), (22) and (23)_inAnd U_REF-In relation to (1), i.e. U_1a、U_1b、U_2a、U_2bAnd U_REF-The relationship of (1): (due to U)_REF+、U_REF-、U_sThe proportional relationship between the two is known, and U can also be obtained_1a、U_1b、U_2a、U_2bAnd U_REF+Or U_sIn relation to (1)

U_1a＝c_1a·U_REF-(24)

U_1b＝c_1b·U_REF-(25)

U_2a＝c_2a·U_REF-(26)

U_2b＝c_2b·U_REF-(27)

From the formulae (24), (25), (26), (27):

the above description is intended to be illustrative of the present invention and should not be taken as limiting the scope of the invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (9)

1. An integral proportional circuit is used for measuring the proportion of direct current components of two alternating current and direct current voltage signals and is characterized by comprising an operational amplifier, an integral amplifier and a comparator; the positive input end of the operational amplifier is connected with the signal to be measured, the positive and negative output ends of the standard voltage source and the ground potential through a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4 respectively, the output end of the operational amplifier is connected with the negative input end and is connected with the negative input end of the integrating amplifier through an integrating resistor R, the output end of the integrating amplifier is connected with the comparatorThe positive input end of (a); an integrating capacitor is connected between the negative input end and the output end of the integrating amplifier, and two ends of the integrating capacitor are provided with a charging switch SW 0; the positive input end of the integrating amplifier is connected with a positive end reference voltage U_REF1The negative input end of the comparator is connected with a negative end reference voltage U_REF2。

2. An impedance measuring method based on the integrating proportional circuit as claimed in claim 1, characterized in that the in-phase component U of the AC voltage signal of the impedance to be measured in the reference orthogonal coordinate system is measured_1aAnd the orthogonal component U_1bAnd the in-phase component U of the AC voltage signal of the standard impedance in the reference orthogonal coordinate system_2aAnd the orthogonal component U_2bThe impedance measurement is converted into the proportion of the direct current component of the measurement voltage, and the specific steps are as follows:

step 1), firstly, determining a forward end reference voltage U connected with a positive input end of an integrating amplifier_REF1A negative end reference voltage U connected with the negative input end of the comparator_REF2The size of (d);

step 2), measuring to obtain a forward end reference voltage U connected with the positive input end of the integrating amplifier_REF1A negative end reference voltage U connected with the negative input end of the comparator_REF2Integral initial voltage U loaded on current limiting resistor R_sThe proportional relationship between the two;

step 3), respectively measuring to obtain the in-phase component U of the alternating voltage signal of the impedance to be measured in the reference orthogonal coordinate system_1aQuadrature component U_1bIn-phase component U of standard impedance alternating current voltage signal in reference orthogonal coordinate system_2aQuadrature component U_2bRespectively connected with the forward end reference voltage U_REF1Negative end reference voltage U_REF2Or a voltage U applied to a resistor R_sThe proportional relationship between the two;

step 4), utilizing the results obtained in the step 2) and the step 3), and obtaining the result according to a formula

$Z_1=\frac{\sqrt{U_{1a}^2+U_{1b}^2}}{\sqrt{U_{2a}^2+U_{2b}^2}}\left|Z_2\right|$

And calculating to obtain the measured impedance.

3. The impedance measurement method according to claim 2, wherein in step 1), a forward-end reference voltage U is determined_REF1And negative terminal reference voltage U_REF2The method comprises the following specific steps:

when the fourth switch SW4 connected to ground potential is closed and the other switches are open, U is selected_REF1So that the charging direction of the capacitor C is always positive or negative, i.e. U_GND+V_OS1-U_eConstant positive or constant negative; during charging:

U_e＝U_REF1+V_OS2+I_B2·R+I_SW0·R

V_OS1、V_OS2-bias voltages of the operational amplifier and the integrating amplifier;

I_B2-bias current of the operational amplifier;

I_SW0split into leakage currents for the closed and open condition of switch SW 0;

likewise, U is selected_REF2So that the voltage difference between the positive input voltage and the negative input voltage of the comparator A3 is constantly positive or constantly negative in the integral zero clearing state; namely U_REF2-V_OS3-U_eConstant positive or constant negative, Vos₃Is the bias voltage of the comparator.

4. The impedance measuring method according to claim 3, wherein in the step 2), the measurement process selects the integration direction as U_GND+V_OS1-U_e>0，U_REF2-V_OS3-U_e>0, comprising the steps of:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor C is connected to the capacitor U_REF--U_s)/R<Current charging of 0, integrating amplifier output voltage U₁Rising to the inversion of the comparator, ending the stage which is used for providing an integration starting point for integration;

c) in the second stage, SW4 is closed, the other switches are opened, and after SW4 is closed, timing is started, and at this time, the capacitor C is connected with (U)_GND-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₁At this stage U₁The voltage is reduced;

d) in the third phase, SW3 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₂And the stage is finished;

e) in the fourth stage, SW2 is closed, the other switches are opened, and the time is started after SW2 is closed, and then the capacitor is started to be (U)_REF+-U_s)/R>0, according to the selected clock and the requiredSelecting proper integration time, and timing the time to be t₃At this stage U₁The voltage is reduced;

f) in the fifth stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₄And the stage is finished;

wherein: u shape_REF+、U_REF-The positive and negative ends of the standard voltage source output voltages respectively.

5. The impedance measuring method according to claim 4, wherein in the step 2), the impedance of the impedance measured by the measured t1, t2, t3, t4,

according to the conservation of charge, the second stage and the third stage can obtain:

$\frac{U_{GND}-U_s}{R}\&CenterDot;t_1+\frac{U_{REF-}-U_s}{R}\&CenterDot;t_2=0---\left(11\right)$

get U_GNDWhen 0, we can get:

$\frac{U_s}{U_{REF-}}=\frac{t_2}{t_1-t_2}---\left(13\right)$

according to the conservation of charge, the fourth stage and the fifth stage can obtain:

$\frac{U_{REF+}-U_s}{R}\&CenterDot;t_3+\frac{U_{REF-}-U_s}{R}\&CenterDot;t_4=0---\left(13\right)$

namely, it is

$\frac{U_{REF+}}{U_{REF-}}=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(14\right)$

Order to

U_REF+＝a·U_REF-(15)

In the formula:

$a=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---2\left(16\right)$

order to

U_s＝b·U_REF-(17)

In the formula:

$b=\frac{t_2}{t_1-t_2}.---\left(18\right)$

6. the impedance measuring method according to claim 5, wherein in the step 3), when U is measured_in-U_s>At 0, the whole integration is divided into four stages:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) second oneStage, SW1 is closed, the other switches are opened, and the capacitor is connected with (U)_in-U_s)/R>0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₅At this stage U₁The voltage is reduced; due to U_inThe signal being a superimposed AC-DC signal, t being for filtering out AC components thereof₅Is an integer multiple of its AC component period, in this case according to U_oPolarity judgment U of voltage_in-U_sThe polarity of (1);

d) in the third phase, SW3 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₆And the stage is finished.

7. The impedance measuring method according to claim 6, wherein in the step 3), according to the measured t5, t6,

according to the principle of charge conservation, the second stage and the third stage can be used

$\frac{U_{in}-U_s}{R}\&CenterDot;t_5+\frac{U_{REF-}-U_s}{R}\&CenterDot;t_6=0$

Combined type (15), (16), (17), (18)

The following can be obtained:

$\frac{U_{in}}{U_{REF-}}=\frac{b(t_5+t_6)-t_6}{t_5}---\left(18\right)$

order to

U_in＝c·U_REF-(19)

In the formula:

$c=\frac{b(t_5+t_6)-t_6}{t_5}.---\left(20\right)$

8. the impedance measuring method according to claim 5, wherein in the step 3), when U is measured_in-U_s<At 0, the whole integration is divided into five stages:

a) and (3) clearing: SW0 and SW4 are closed, and the integrating capacitor is discharged;

b) in the first stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the stage is ended and is used for providing an integration starting point for integration;

c) in the second phase, SW1 is closed and the remaining switches are opened, with the capacitor turned on (U)_in-U_s)/R<0, selecting proper integration time according to the selected clock and the required resolution, and timing the time to be t₅At this stage U₁The voltage rises; due to U_inThe signal being a superimposed AC-DC signal, t being for filtering out AC components thereof₅Is an integer multiple of its AC component period, in this case according to U_oPolarity judgment U of voltage_in-U_sThe polarity of (1);

d) in the third phase, SW2 is closed and the remaining switches are opened, so that the capacitor is connected to (U)_REF+-U_s)/R>Current charging of 0, U₁The voltage drops to the inverse of the comparator, and then the charging is continued for a short time t₀Total integration time of t₆And the stage is finished;

e) in the fourth stage, SW3 is closed and the remaining switches are opened, so that the capacitor is connected with (U)_REF--U_s)/R<Current charging of 0, U₁The voltage rises until the comparator reverses, and the timing time is t₇And the stage is finished.

9. The impedance measuring method according to claim 8, wherein in the step 3), according to the measured t5, t6, t7,

based on the principle of conservation of charge, the second, third and fourth stages

$\frac{U_{in}-U_s}{R}\&CenterDot;t_5+\frac{U_{REF+}-U_s}{R}\&CenterDot;t_6+\frac{U_{REF}--U_s}{R}\&CenterDot;t_7=0$

Combined type (15), (16), (17), (18)

Namely:

$\frac{U_{in}}{U_{REF-}}=\frac{b(t_5+t_6)-{\mathrm{at}}_6+(b-1)t_7}{t_5}---\left(21\right)$

let U_in＝c·U_REF-(22)

In the formula:

$c=\frac{b(t_5+t_6)-{\mathrm{at}}_6+(b-1)t_7}{t_5}.---\left(23\right)$