CN104253160A - B4-Flash with convexity grid electrode structure - Google Patents
B4-Flash with convexity grid electrode structure Download PDFInfo
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- CN104253160A CN104253160A CN201410375182.0A CN201410375182A CN104253160A CN 104253160 A CN104253160 A CN 104253160A CN 201410375182 A CN201410375182 A CN 201410375182A CN 104253160 A CN104253160 A CN 104253160A
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- 238000003860 storage Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 230000008961 swelling Effects 0.000 claims description 7
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910015900 BF3 Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000005641 tunneling Effects 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 229920006395 saturated elastomer Polymers 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000006396 nitration reaction Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002707 nanocrystalline material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 235000019633 pungent taste Nutrition 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a non-volatile memory, in particular to a B4-Flash with a convexity grid electrode structure. The convexity grid electrode structure successively comprises a tunnel oxide layer, an electric charge storage layer, a dielectric barrier layer and a conducting layer from bottom to top, wherein the tunnel oxide layer is of a convexity type structure of which two sides of the top surface bulge to the middle; meanwhile, the electric charge storage layer is of an arch bridge shaped structure, wherein two sides of the top surface edge of the arch bridge shaped structure bulge to the middle, and the bottom surface of the arch bridge shaped structure sink to the middle from two sides; the electric charge storage layer is integrally covered on the upper surface of the tunnel oxide layer. According to the B4-Flash with the convexity grid electrode structure, the convexity grid electrode structure is adopted in the B4-Flash, so that tunneling from the electric charge storage layer to a substrate is greater than the tunneling injected into the electric charge storage layer from a gate pole so as to inhibit even eliminate and erase saturation and improve erasing speed.
Description
Technical field
The present invention relates to nonvolatile memory, be specifically related to a kind of B4-Flash with convex surface grid structure.
Background technology
Flash memory is the one of non-volatile memory device, and traditional flash memory utilizes floating boom extremely to store data, and floating boom generally uses polysilicon (poly) material to make.
For NOR flash memory mnemon, most important what limit that its size continues reduction is the long shortenings of grid.This is mainly due to channel hot electron (channel Hot Electrons, be called for short CHE) inject compile mode requirement drain terminal and have certain voltage, and this voltage has a great impact penetrating of source and drain end, inapplicable for short channel device channel hot electron mode.Another one problem compares with NAND with AND data storage device, which has limited the compiling rate of NOR flash memory.According to document " G.Servalli, et al., IEDM Tech.Dig., 35_1,2005 " prediction, the long physics limit reduced of grid of conventional flash memory structure is 130nm.
The article " A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot Electron Injection " delivered according to people such as Shuo Ji Shukuri refer to the principle of the device dimensions shrink of B4 (Back Bias Assisted Band-to-Band)-Flash Memory.
As shown in Figure 1, typical floating boom B4-Flash structure is by substrate 10, tunnel oxide (tunnel oxide) 11, charge storage layer (floating boom, floating gate, FG) 12, block media layer 13 and conductive layer (control gate, control gate, CG, or claim gate pole) 14 compositions.Source electrode (source) and drain electrode (drain) is comprised in substrate.The principle of this structure storing information is: when compiling, and applies a larger voltage, and by source-drain electrode and Substrate ground, because tunneling effect makes the electron tunneling in substrate 10 cross tunnel oxide 11, be stored in charge storage layer 12 on conductive layer 14.When wiping, apply a negative voltage to conductive layer 14, and by source-drain electrode and substrate 10 ground connection, the electronics reverse tunnel of charge storage layer 12 returns substrate 10.For making the speed of compiling and erasing improve, need thinner tunnel oxide, but so thin thickness can make the durability in the hold facility of electric charge and compiling/erase process reduce.But the speed of erasing is directly proportional to electric field strength, and electric field is larger, and erasing speed is faster.Carry out in erase process, there are two tunnelling processes in this structure: one is that electronics is tunneling to substrate 10 from charge storage layer 12; Two is that electronics enters charge storage layer 12 from grid through block media layer 13.
Continue with reference to shown in Fig. 1, in traditional floating boom B4-Flash structure, because each layer (tunnel oxide 11, charge storage layer 12, block media layer 13, conductive layer 14) upper and lower surface is horizontal plane and arranged in parallel, therefore compile with power line when wiping by the parallel distribution of each layer, wipe start time charge storage layer 12 in the quantity of electronics many, the electric field of tunnel oxide 11 is much larger than the electric field of block media layer 13; But along with the carrying out of erasing, the electronics of catching in charge storage layer 12 reduces gradually, the electric field therefore in tunnel oxide 11 constantly reduces and electric field in block media layer 13 constantly increases, until completely erasing time two place's electric field strength equal.Therefore, in charge storage layer 12, electron tunneling can weakening and weaken with tunnel oxide 11 electric field to the tunnelling speed of substrate 10, and can strengthen gradually through the tunnelling that conductive layer 14 is tunneling in charge storage layer 12.When the speed of two tunnellings is equal, the electronics in charge storage layer 12 loses and injection reaches dynamic balance, enters the state that erasing is saturated, erasing can not be proceeded, and erasing speed reduces.
Prior art Problems existing: because existing floating boom B4-Flash technology still adopts the grid structure of plane, there is the problem that erasing is saturated.
Patent (CN 102376770A) discloses a kind of floating-gate device and method thereof, and this floating-gate device comprises: substrate, has channel region; Floating boom dielectric substance, over the channel region side; Floating boom, on floating boom dielectric substance, and comprises: polycrystalline silicon material, and impurity, in polycrystalline silicon material, and is configured to interact with polycrystalline silicon material and changes to resist the polycrystalline silicon material crystallite dimension that hotness is raw in fact; Control gate dielectric, on floating boom; And control gate, on control gate dielectric.
This patent carrys out by the impurity adulterated in polysilicon gate material the change producing the crystallite dimension interacted during heating treatment to resist polycrystalline silicon material with polycrystalline silicon material, and arranges floating-gate device charge storage ability relative to threshold voltage.But because this structure is identical with traditional Flash structure, the floating boom dielectric substance that it comprises and the upper and lower surface of floating boom are a horizontal plane, therefore in programming process, the distribution of its power line is identical with shown in Fig. 1, therefore still has the problem that erasing is saturated.
Summary of the invention
The defect that the present invention exists according to B4-Flash of the prior art, provide a kind of B4-Flash with convex-surface type grid structure, wherein, described grid structure is arranged at an active area substrate, the active area substrate being arranged in described grid structure two bottom sides is formed with source doping region and drain doping region, forms a raceway groove between described source doping region and drain doping region;
Described grid structure is followed successively by tunnel oxide, charge storage layer, block media layer and conductive layer from bottom to top;
Wherein, described tunnel oxide is the convex-surface type structure of swelling in the middle part of end face two side direction, and the end face of this tunnel oxide is a level and smooth convex cambered surface;
Described charge storage layer is protuberance and the arch bridge-type structure of bottom surface two side direction medial recess in the middle part of end face two side direction, and the end face of described charge storage layer and bottom surface are a level and smooth cambered surface with the complete upper surface being covered in described tunnel oxide;
Described storage medium layer selects the polysilicon or nanocrystalline of N-type or the doping of P type.
Above-mentioned B4-Flash, wherein, described block media layer and conductive layer are all identical from the shape of described charge storage layer and thickness is different.
Above-mentioned B4-Flash, wherein, described substrate is silicon substrate.
Above-mentioned B4-Flash, wherein, described tunnel oxide is silica.
Above-mentioned B4-Flash, wherein, described conductive layer is polysilicon.
Above-mentioned B4-Flash, wherein, described raceway groove is P type raceway groove.
Above-mentioned B4-Flash, wherein, the contact-making surface bottom described substrate and described tunnel oxide is the convex cambered surface of swelling in the middle part of two side direction.
Above-mentioned B4-Flash, wherein, described block media layer is silicon dioxide layer or silicon oxide-silicon nitride-silicon dioxide (ONO) layer.
Above-mentioned B4-Flash, wherein, described charge storage layer thickness is 50-100nm, and described conductive layer thickness is 150-200nm.
Above-mentioned B4-Flash, wherein, when described block media layer is silicon dioxide, described block media layer thickness is 5-15nm;
When described block media layer is silicon oxide-silicon nitride-silicon dioxide layer, then the thickness of the bottom silicon dioxide silicon of this block media layer is 2nm-5nm, and the thickness of middle nitride silicon is 6nm-10nm, and the thickness of top silicon dioxide silicon is 2nm-5nm.
Above-mentioned B4-Flash, wherein, the maximum ga(u)ge of described tunnel oxide is no more than in 5nm.
Above-mentioned B4-Flash, wherein, selects phosphorus or arsenic to carry out N-type doping to described storage medium layer.
Above-mentioned B4-Flash, wherein, selects boron or boron fluoride to carry out the doping of P type to described storage medium layer.
Utilizing B4-Flash provided by the present invention when wiping, charge storage layer can be made to be greater than the tunnelling from grid iunjected charge accumulation layer to the tunnelling of substrate, thus can suppress even to eliminate the saturated appearance of erasing, improve erasing speed.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is power line and the structural representation of typical floating boom B4-Flash device;
Fig. 2 a is the principle schematic of B4-Flash memory;
Fig. 2 b is the electron energy band schematic diagram of drain terminal;
Fig. 2 c is the electron energy band schematic diagram of source;
Fig. 3 is power line and the structural representation that the present invention has the B4-Flash of convex-surface type grid structure.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The invention provides a kind of B4-Flash with convex surface grid structure, with reference to shown in Fig. 3, this grid structure is arranged at an active area (active area, AA) on substrate 10, the active area substrate 10 being arranged in grid structure two bottom sides is formed with source doping region (source) and drain doping region (drain), forms a raceway groove (channel) between source doping region and drain doping region.An optional but embodiment of not limiting to is, this raceway groove P type raceway groove (P-channel).
Wherein, above-mentioned grid structure is followed successively by tunnel oxide 11, charge storage layer 12, block media layer 13 and conductive layer 14 from bottom to top.
In an embodiment of the present invention, tunnel oxide 11 is the convex-surface type structure of swelling in the middle part of end face two side direction, and the end face of this tunnel oxide 11 is also a level and smooth convex cambered surface simultaneously.Charge storage layer 12 is that in the middle part of end face two side direction, protuberance and bottom surface are from the arch bridge-type structure of two side direction medial recess, and the end face of this charge storage layer 12 and bottom surface are a level and smooth cambered surface with the complete upper surface being covered in tunnel oxide 11 simultaneously.
Further, an optional execution mode is, substrate 10 is the convex cambered surface of swelling in the middle part of two side direction with the contact-making surface bottom tunnel oxide 11, and then makes the bottom surface two side direction medial recess of tunnel oxide 11, forms a tunnel oxide 11 identical with charge storage layer 12 shape.But those skilled in the art are to be understood that, tunnel oxide 11 and the contact-making surface of substrate 10 are that convex surface is only a preferably execution mode, be not limited to this execution mode in actual applications, such as in some other execution mode, the cross section that substrate 10 contacts with tunnel oxide 11 is that horizontal plane does not affect the present invention.
In an embodiment of the present invention, block media layer 13 is with conductive layer 14 is identical from the shape of charge storage layer 12 and thickness is different.An optional but execution mode do not limited to is, block media layer 13 is identical from the shape of charge storage layer 12 with the shape of conductive layer 14 and thickness is different, namely block media layer 13 also encircles bridge-like structure to cover the upper surface of charge storage layer 12 in one, same, conductive layer 14 is also that an arch bridge-like structure is to cover the upper surface of block media layer 13.In yet another embodiment of the present invention, the two bottom sides of block media layer 13 to medial recess to cover the upper surface of charge storage layer 12, but the top planes of this block media layer 13 is a horizontal plane, the bottom therefore covering the conductive layer 14 of block media layer 13 upper surface is also a horizontal plane; Meanwhile, when the bottom of conductive layer 14 is a horizontal plane, its top planes can be the convex-surface type structure of swelling in the middle part of two side direction, or is horizontal plane.
In an embodiment of the present invention, an optional but execution mode do not limited to is, tunnel oxide 11 is silica, conductive layer 14 is polysilicon layer (poly silicon), block media layer 13 is for silicon dioxide or select silicon oxide-silicon nitride-silicon dioxide (Oxide-Nitride-Oxide is called for short ONO) layer.Select ONO three-decker as the dielectric layer between charge storage layer 12 and conductive layer 14, this is that comparatively nitration case is good due to the combination of oxide layer and base crystalline substance, and nitration case is placed in the middle, then can stop the extension of defect (as pinhole), so three-decker can be complementary lack, be conducive to boost device performance.
In embodiments of the invention, one optional but the execution mode do not limited to is that above-mentioned charge storage layer 12 can select polysilicon layer or nanocrystalline (nanocrystalline).Current Flash device generally adopts polysilicon as floating boom, but in the present invention, also can adopt the floating boom that the nanocrystalline material of better performance can be brought as Flash device; Meanwhile, this charge storage layer 12 for having the material layer of N-type doping type or P type doping type, by the threshold voltage (Voltage threshold, Vt) of adjusting means of adulterating to charge storage layer 12.Optionally, N-type impurity comprises phosphorus (P), and arsenic (As) etc., p type impurity comprises boron (B), boron fluoride (BF
2) etc.
In one embodiment of the invention, the grid length preparing the floating boom B4-Flash device with convex surface grid is 50nm, the thickness that convex surface grid structure bends each layer is: the maximum ga(u)ge of tunnel oxide 11 is no more than in 5nm, preferred further, the height of the both sides, top of tunnel oxide 11 is 3nm; The thickness of charge storage layer 12 is 50-100nm, is preferably 90nm; Conductive layer 14 thickness is 150-200nm, is preferably 175nm; In the present invention, because block media layer 13 is chosen as silicon dioxide or ono dielectric layer, therefore thickness is also different in both cases: when block media layer is silicon dioxide, and block media layer 13 thickness is 5-15nm simultaneously, is preferably 8nm; When block media layer 13 is ono dielectric layer, then the bottom silicon dioxide silicon thickness of this block media layer 13 is 2nm-5nm, and the thickness of middle nitride silicon is 6nm-10nm, and top silicon dioxide silicon thickness is 2nm-5nm, and preferably this block media layer 13 gross thickness is 15nm.
The upper and lower contact-making surface degree of crook of each layer is even, and charge storage layer 12, block media layer 13 and conductive layer 14 thickness is even everywhere.
Just the operation principle of B4-Flash device provided by the present invention is described further below.Fig. 2 a is depicted as two steps that BTBT (Band-to-Band Tunneling)-HE produces: (1) is BTBT generation; (2) be the acceleration of electronics.Fig. 2 b is depicted as the energy band diagram of drain terminal, and Fig. 2 c is depicted as the energy band diagram of source, can learn according to Fig. 2 c, BTBT suppress by source voltage terminal 1.8V.
The BTBT-HE production model that backgate bias voltage is assisted is with reference to shown in Fig. 2 a to Fig. 2 c, wherein, 3 are expressed as depletion layer (depletion layer), and 4 is accumulation layer (accumulation layer), and 5 is the N-type ring-shaped area (N-halo) near source/drain.The generation of B4-HEs needs two steps: 1, the generation of BTBT controls by vertical electric field (Vg-Vd); 2, the BTBT electronics in the depletion layer 3 produced accelerates by tying electric field (Vd-Vb).Source because be applied with 1.8V voltage, knot electric field and vertical electric field all weakened, cause compiling suppressed.Under the assistance accelerated BTBT-HE of such backgate bias voltage, the voltage difference of source and drain end can be very little, can ensure that device size can be reduced like this.
Utilizing B4-Flash provided by the invention when performing write operation, conductive layer 14 applying a larger voltage, and by source and drain doped region and substrate 10 ground connection, because tunneling effect makes electron tunneling cross tunnel oxide 11, is stored in charge storage layer 12; When wiping, apply a negative voltage to conductive layer 14, and by source and drain doped region and substrate 10 ground connection, the electronics reverse tunnel of charge storage layer 12 returns substrate 10.Have in the floating boom B4-Flash device of convex surface grid at this, due to power line be perpendicular to dielectric layer surface distribution, so in the structure of convex surface grid, power line between substrate and grid is no longer parallel distribution as in floating boom B4-Flash device typical in Fig. 1, but focuses on substrate 10 from conductive layer 14 perpendicular to block media layer 13, charge storage layer 12 and tunnel oxide 11.As shown in Figure 3, the density of power line represents the size of electric field strength, and such electric force lines distribution makes grid constantly increase to the electric field strength of substrate.When wiping, charge storage layer can be made to be greater than the tunnelling from gate pole iunjected charge accumulation layer to the tunnelling of substrate, thus can suppress even to eliminate the saturated appearance of erasing, improve erasing speed.
The B4-Flash of convex surface grid structure provided by the present invention can complete compatible existing CMOS making technology, process variations is little, can be prepared based on gate first or gate last technique, the structure of the present invention is applied in the Flash preparation technology of HKMG simultaneously and is suitable for too, and effectively can reduce the critical dimension (Critical Dimension, CD) of device.
In sum, because B4-Flash provided by the invention is owing to having the grid structure of convex surface, charge storage layer can be made to be greater than the tunnelling from gate pole iunjected charge accumulation layer to the tunnelling of substrate, thus can to suppress even to eliminate the saturated appearance of erasing, improve erasing speed.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (13)
1. one kind has the B4-Flash of convex-surface type grid structure, it is characterized in that, described grid structure is arranged at an active area substrate, the active area substrate being arranged in described grid structure two bottom sides is formed with source doping region and drain doping region, forms a raceway groove between described source doping region and drain doping region;
Described grid structure is followed successively by tunnel oxide, charge storage layer, block media layer and conductive layer from bottom to top;
Wherein, described tunnel oxide is the convex-surface type structure of swelling in the middle part of end face two side direction, and the end face of this tunnel oxide is a level and smooth convex cambered surface;
Described charge storage layer is protuberance and the arch bridge-type structure of bottom surface two side direction medial recess in the middle part of end face two side direction, and the end face of described charge storage layer and bottom surface are a level and smooth cambered surface with the complete upper surface being covered in described tunnel oxide;
Described storage medium layer selects the polysilicon or nanocrystalline of N-type or the doping of P type.
2. B4-Flash as claimed in claim 1, it is characterized in that, described block media layer and conductive layer are all identical from the shape of described charge storage layer and thickness is different.
3. B4-Flash as claimed in claim 1, it is characterized in that, described substrate is silicon substrate.
4. B4-Flash as claimed in claim 1, it is characterized in that, described tunnel oxide is silica.
5. B4-Flash as claimed in claim 1, it is characterized in that, described conductive layer is polysilicon.
6. B4-Flash as claimed in claim 1, it is characterized in that, described raceway groove is P type raceway groove.
7. B4-Flash as claimed in claim 1, is characterized in that, the contact-making surface bottom described substrate and described tunnel oxide is the convex cambered surface of swelling in the middle part of two side direction.
8. B4-Flash as claimed in claim 1, it is characterized in that, described block media layer is silicon dioxide layer or silicon oxide-silicon nitride-silicon dioxide (ONO) layer.
9. B4-Flash as claimed in claim 1, it is characterized in that, described charge storage layer thickness is 50-100nm, and described conductive layer thickness is 150-200nm.
10. B4-Flash as claimed in claim 8, it is characterized in that, when described block media layer is silicon dioxide, described block media layer thickness is 5-15nm;
When described block media layer is silicon oxide-silicon nitride-silicon dioxide layer, then the thickness of the bottom silicon dioxide silicon of this block media layer is 2nm-5nm, and the thickness of middle nitride silicon is 6nm-10nm, and the thickness of top silicon dioxide silicon is 2nm-5nm.
11. B4-Flash as claimed in claim 1, it is characterized in that, the maximum ga(u)ge of described tunnel oxide is no more than in 5nm.
12. B4-Flash as claimed in claim 1, is characterized in that, select phosphorus or arsenic to carry out N-type doping to described storage medium layer.
13. B4-Flash as claimed in claim 1, is characterized in that, select boron or boron fluoride to carry out the doping of P type to described storage medium layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107863298A (en) * | 2017-12-06 | 2018-03-30 | 武汉新芯集成电路制造有限公司 | The preparation method and floating gate type flash memory of floating gate type flash memory |
| CN110265399A (en) * | 2018-03-12 | 2019-09-20 | 爱思开海力士有限公司 | Semiconductor device and its manufacturing method |
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| CN102290444A (en) * | 2011-08-31 | 2011-12-21 | 上海宏力半导体制造有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory |
| CN102683398A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) gate structure, manufacture method, and semiconductor device |
| CN102832175A (en) * | 2012-09-11 | 2012-12-19 | 上海华力微电子有限公司 | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863298A (en) * | 2017-12-06 | 2018-03-30 | 武汉新芯集成电路制造有限公司 | The preparation method and floating gate type flash memory of floating gate type flash memory |
| CN110265399A (en) * | 2018-03-12 | 2019-09-20 | 爱思开海力士有限公司 | Semiconductor device and its manufacturing method |
| CN110265399B (en) * | 2018-03-12 | 2023-10-31 | 爱思开海力士有限公司 | Semiconductor device and manufacturing method thereof |
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