CN104241371A - Nanowire transistor - Google Patents

Abstract

A nanowire transistor, which relates to the technical field of semiconductor field effect transistors, wherein the transistor is cylindrical, and the transistor has a cylindrical substrate made of SiGe material, and the two ends of the cylindrical substrate located in the direction of the central axis are respectively used as A source region and a drain region of the nanowire transistor, a channel region is formed between the source and the drain; a cylindrical gate oxide layer covers the substrate surface between the source region and the drain region, and The outer side of the gate oxide layer is covered by a polysilicon gate; wherein, the Ge content of the source region and the drain region is different from the Ge content of the channel region. Using compressive strain SiGe as the material of the nanowire transistor improves the hole mobility of the nanowire transistor and reduces the parasitic resistance.

Description

nanowire transistor

technical field

The invention relates to the technical field of semiconductor field effect transistors, in particular to a nanowire transistor.

Background technique

Under the guidance of Moore's Law, the size of integrated circuit semiconductor devices is getting smaller and smaller, but it cannot be reduced infinitely. It will reach its physical limit when it is reduced to a certain extent, and serious short-channel effects and gate leakage currents will appear. This will be a challenge to the validity of Moore's Law. However, people are actively looking for alternative ways to shorten the device size to improve performance. People put the focus of technical exploration on the use of high-K materials and the exploration of new device structures, especially the latter. The new device structure will be the future of semiconductor devices. Research and development directions and trends. The silicon nanowire transistor is a novel device structure that is one of the best hopeful contenders at the 22nm end node of the integrated circuit development roadmap. At present, the silicon nanowire structure transistors initially reported at home and abroad have beneficial subthreshold characteristics, carrier mobility and off-state characteristics, which can well suppress the short channel effect. Compared with the traditional bulk silicon planar devices, the one-dimensional quasi-ballistic transport nanowire MOSFET shows a strong size reduction advantage, and the nanowire transistor will show great potential for realizing the established goal of the semiconductor roadmap. Because the area of the gate surrounding the channel is enlarged, the ability to control the inversion electrons of the channel is improved, the short channel effect of the MOS device is reduced, and the reduction of the thickness of the gate oxide layer required to reduce the size of the device is avoided. , thereby reducing the gate leakage current.

When the characteristic size of MOSFET enters the nanometer scale, the reduction of carrier mobility becomes one of the main factors limiting the performance of the device.

By applying stress in the direction of the channel, or by employing different substrate orientations, the performance of MOSFETs can be significantly enhanced without changing the size of the device assembly.

For the short trench surround gate type nanowire transistor, according to the report in the literature "A UnifiedCarrier-Transport Model for the Nonsocial Surrounding-GateMOSFET Comprising Quantum–Mechanical Effects", its electron mobility is 120cm ² /V·s, which is still far lower Compared with the 1300cm2/V·s electron mobility of the general long trench planar MOSFET. Under the same conditions, the mobility of electrons is close to three times the mobility of holes, so the hole mobility of short-groove surrounding gate nanowire transistors and general long-groove planar MOSFETs are 40cm ² /V·s and 433cm ² / V·s, the former is only 1/10 of the latter. Therefore, the problem of too small mobility needs to be solved urgently for this kind of gate-enclosed nanowire transistor.

Chinese patent (CN102082096A) has introduced a kind of preparation method of Ge or SiGe nanometer field effect transistor, first forms polysilicon gate on the isolation layer on sinking the bottom; The SiGe film is deposited, the source and drain of the SiGe film are doped, and the source and drain region pattern is defined by photolithography, and the SiGe film is anisotropically dry etched to form SiGe sidewalls on both sides of the polysilicon gate. A source region and a drain region are formed at both ends of the sidewall, and finally the SiGe sidewall is oxidized to remove the oxide layer formed on the surface to obtain Ge nanowires or SiGe nanowires with high Ge content.

Chinese patent (CN102822971A) describes a technique for embedding silicon germanium source and drain stressors in field effect transistors based on nanoscale channels. In one aspect, a method of manufacturing FETs includes the following steps, providing doping A substrate having a dielectric on the doped substrate, on which at least one silicon nanowire is disposed. masking one or more parts of the nanowires and exposing other parts of the nanowires, growing epitaxial germanium on the exposed parts of the nanowires, making the epitaxial germanium and Si in the nanowires interact Diffusion to form SiGe regions embedded in the nanowires, the SiGe regions introduce compressive strain in the nanowires, the doped substrate serves as the gate of the FET, the masking of the nanowires A portion serves as the channel of the FET, and the embedded SiGe region serves as the source and drain regions of the FET.

The above two patents do not record the technical characteristics of the nanowire transistor formed by combining the heterojunction SiGe with the <100> crystal orientation as the crystal orientation of the channel, and improving the carrier mobility and driving current of the junctionless transistor.

Contents of the invention

In view of the above problems, the present invention provides a nanowire transistor.

A nanowire transistor, wherein the transistor has a cylindrical substrate of SiGe material, and the two ends of the cylindrical substrate located in the direction of the central axis are respectively used as a source region and a drain region of the nanowire transistor, and the source A channel region is formed between the electrode and the drain;

A cylindrical gate oxide layer covers the substrate surface between the source region and the drain region, and the outer side of the gate oxide layer is covered by a polysilicon gate;

Wherein, the Ge content of the source region and the drain region is different from the Ge content of the channel region.

In the above-mentioned transistor, wherein, the crystal orientation of the channel region along the direction from the source region to the drain region is <100>.

In the above transistor, the chemical molar ratio of Ge in the source region and the drain region is smaller than the chemical molar ratio of Ge in the channel region.

In the above transistor, the chemical molar ratio of Ge in the source region and the drain region is the same.

In the above transistor, BF ₂ is selected to dope both ends of the substrate to form a source region and a drain region, and the doping concentration is 1e20/cm ³ .

The above transistor, wherein the chemical molar ratio of Ge in the source region and the drain region is 1%-100%.

The above transistor, wherein the chemical molar ratio of Ge in the channel region is 1%-100%.

In the above transistor, the source and drain are P-type, and the channel region is N-type.

In the above-mentioned transistor, the polysilicon gate is cylindrical.

In summary, the nanowire transistor disclosed by the present invention increases the mobility of carriers by using SiGe with different Ge contents as the source and drain regions and the channel region (because the lattice constant of SiGe is higher than that of Si Large), and because the Ge content of the source and drain regions and the channel region are different, the band gap and lattice constant of the channel region are different from those of the source and drain regions, resulting in an increase in hole velocity and resulting in lateral compressive stress The hole mobility is further enhanced, and the present invention uses <100> as the crystal orientation of the transistor channel, thereby further improving the hole mobility of the nanowire transistor and reducing the parasitic resistance of the nanowire transistor.

Description of drawings

Embodiments of the present invention are more fully described with reference to the accompanying drawings. However, the accompanying drawings are for illustration and illustration only, and do not limit the scope of the present invention.

Fig. 1 is the structural representation of transistor of the present invention;

Fig. 2 is a schematic diagram of the source, drain and channel structure of the transistor of the present invention;

Fig. 3 is a schematic diagram of the electronic energy bands of the channel and source and drain terminals of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

The invention provides a nanowire transistor, which can be applied to the technical field of semiconductor field effect transistors. When the transistor is used, the carrier mobility and driving current of the nanowire transistor are improved because SiGe is used as the material of the nanowire transistor.

The core idea of the present invention is to adopt SiGe as the material of the nano-transistor, the addition of Ge can improve the mobility of electrons and holes of the junction-free transistor, and the source-drain end of the device is different from the Ge content in the channel. The structure of the heterojunction can increase the emission speed and mobility of the holes. At the same time, the <100> crystal orientation that can improve the hole mobility is used as the crystal orientation of the channel, and the effect of enhancing the hole mobility with the heterojunction SiGe Work together to solve the problem of too small mobility of nanowire transistors.

Comparison of the electrical characteristics of 13nm diameter heterogeneous SiGe nanowire PMOSFET and planar homogeneous SiGe channel device (width 1μm), the former is 4.5 times that of the latter, while 13nm diameter heterogeneous SiGe nanowire PMOSFET and planar homogeneous SiGe channel The comparison of the relationship between gm and Vg of the device (width 1μm) shows that the former is 4.5 times larger than the latter in both the saturation region and the linear region; if the p-MOSFET with stress Si0.8Ge0.2 adopts the <100> crystal orientation as the channel Crystal orientation, p-MOSFET with stress Si0.8Ge0.2 compared with <110> channel crystal orientation has 25% higher hole mobility and 20% lower parasitic resistance. The latter has superior mobility and threshold voltage roll-off (Threshold Voltage Roll-Off) effect characteristics than Sip-MOSFET.

Therefore, it can be predicted that if the SiGe heterojunction junctionless transistor adopts <100> as the crystal orientation of the channel, the hole mobility can be significantly improved and the parasitic resistance can be reduced.

Example 1:

The structure of the transistor is shown in Figure 1, the transistor has a cylindrical substrate of SiGe material, a cylindrical oxide layer 2 is coated on the outside of the substrate, and both ends of the substrate are exposed to form a source region 4 and the drain region 3, the channel region 5 of the transistor is formed between the source region 4 and the drain region 3, a cylindrical polysilicon gate 1 is covered on the outside of the gate oxide layer 2, and the source region 4 and the drain region 3 are formed Doping of BF ₂ donor ions, the doping concentration is 1e20/cm ³ . During the manufacturing process, select the <100> crystal orientation on the wafer as the direction of the channel region, and point from the source region 4 to the drain region 3 along the axis (the direction of the arrow shown in the figure). Regarding the manufacturing process of the nanowire transistor, As long as the crystal orientation of the channel is selected to be <100> during photolithography. The energy band structure of the device of the present invention is shown in Figure 3, the chemical molar ratio of Ge in the source region 4 and the drain region 3 of the transistor is the same, and the chemical molar ratio of Ge in the source region 4 and the drain region 3 is smaller than that in the channel region 5 The chemical molar ratio of Ge, wherein, the content of Ge in the SiGe of source region 4 and drain region 3 is 30%, the content of Ge in the SiGe of intermediate channel region 5 is 70%, such source region 4, drain region 3 The structure of the heterojunction with the channel region 5 brings about an upward shift of the valence band of the intermediate channel region 5 , and the upward shift of the valence band can improve the hole emission velocity and mobility. As shown in Figure 1 and Figure 2, it can be seen from the figure that the structure of the transistor is cylindrical, the left and right ends are P-type doped source and drain regions with SiGe and Ge content of 30%, and the middle part is SiGe and Ge content 70% N-type doped silicon.

As shown in Figure 1, the cylindrical surrounding gate structure can enhance the gate control capability, effectively suppress the short-channel effect, and contribute to the reduction of the transistor size. SiGe, as a material for source, drain and channel, can increase the mobility of carriers because its lattice constant is larger than that of Si. At the same time, the <100> oriented channel can suppress the diffusion of P-type dopant impurities at the drain end, increase the concentration of dopant impurities at the drain end, and reduce parasitic resistance.

Example 2:

The structure of the transistor is shown in Figure 1, the transistor has a cylindrical substrate made of SiGe, a cylindrical upper oxide layer 2 is coated on the outside of the substrate, and both ends of the substrate are exposed to form a source region 4 and the drain region 3, the channel region 5 of the transistor is formed between the source region 4 and the drain region 3, a cylindrical polysilicon gate 1 is covered on the outside of the gate oxide layer 2, and the source region 4 and the drain region 3 are formed Doping of BF ₂ ions, the doping concentration is 1e20/cm ³ . During the manufacturing process, select the <100> crystal orientation on the wafer as the direction of the channel region, and point from the source region 4 to the drain region 3 along the axis line (the direction of the arrow shown in the figure), regarding the manufacturing process of nanowire transistors , as long as the crystal orientation of the channel is selected to be <100> during photolithography. The energy band structure of the device of the present invention is shown in Figure 3, the chemical molar ratio of Ge in the source region 4 and the drain region 3 of the transistor is the same, and the chemical molar ratio of Ge in the source region 4 and the drain region 3 is smaller than that in the channel region 5 The chemical molar ratio of Ge, wherein, the content of Ge in the SiGe of source region 4 and drain region 3 is 20%, the content of Ge in the intermediate channel region 5 SiGe is 80%, such source region 4, drain region 3 and ditch The structure of the heterojunction in the channel region 5 brings about an upward shift of the valence band in the middle channel region, and the upward shift of the valence band can improve the hole emission velocity and mobility. As shown in Figure 1 and Figure 2, it can be seen from the figure that the structure of the transistor is cylindrical, and the left and right ends are P-type doped source and drain regions with SiGe and Ge content of 20%, and the middle part is SiGe and Ge content 80% N-type doped silicon.

As shown in Figure 1, the cylindrical surrounding gate structure can enhance the gate control capability, effectively suppress the short-channel effect, and contribute to the reduction of the transistor size. SiGe, as a material for source, drain and channel, can increase the mobility of carriers because its lattice constant is larger than that of Si. At the same time, the channel in the <100> direction can suppress the diffusion of P-type dopant impurities at the drain end, increase the concentration of dopant impurities at the drain end, and reduce parasitic resistance.

SiGe as the substrate has different Ge content in different regions. The chemical molar ratio of the Ge content in the source region and the drain region is 1%-100%, and the chemical molar ratio of Ge in the source region and the drain region is are the same, the Ge content chemical molar ratio of the channel region is 1%-100%, wherein the chemical molar ratio of Ge in the source region and the drain region is less than the chemical molar ratio of Ge in the channel region, such a structural design makes The structure of the heterojunction between the left and right sides and the middle channel part brings up the valence band of the middle channel part, and the upward shift of the valence band improves the emission speed and mobility of holes.

In order to obtain a junction-free transistor with better effect, the polysilicon gate length of the transistor is 300-400nm (such as 300nm, 340nm, 350nm and 400nm); the thickness is 70-80nm (such as 73nm, 75nm, 78nm and 80nm); it can be seen that The length of the channel region in the SiGe substrate is the same as the length of the polysilicon gate, and the thickness of the silicon dioxide layer as the gate oxide layer is 5-10nm (such as 5nm, 7nm, 8nm and 10nm); the source region, drain of the transistor The regions and channel regions are 10-15 nm in diameter (eg 10 nm, 12 nm, 13 nm and 15 nm).

The SiGe heterojunction structure applied to the nanowire transistor can improve the hole mobility and driving current of the transistor, and the <100> crystal orientation of the channel in the SiGe substrate can be used as the channel crystal orientation, which can significantly improve the hole mobility. As well as reducing the parasitic resistance, the combination of the two can greatly improve the hole mobility and driving current of the P-type junctionless transistor, and reduce the parasitic resistance.

Through the description and drawings, typical examples of specific structures of specific implementations are given, and other transformations can also be made based on the spirit of the present invention. While the above invention presents preferred embodiments, such disclosure is not intended to be limiting.

Various changes and modifications will no doubt become apparent to those skilled in the art upon reading the foregoing description. Therefore, the appended claims should be considered to cover all changes and modifications within the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should still be deemed to be within the intent and scope of the present invention.

Claims (9)

1. A kind of nanowire transistor, it is characterized in that, described transistor has a cylindrical substrate of SiGe material, and this cylindrical substrate is positioned at the two ends exposed on central axis direction as the source region and the drain region of nanowire transistor respectively , a channel region is formed between the source and the drain; A cylindrical gate oxide layer covers the substrate surface between the source region and the drain region, and the outer side of the gate oxide layer is covered by a polysilicon gate; Wherein, the Ge content of the source region and the drain region is different from the Ge content of the channel region. 2 . The transistor according to claim 1 , wherein the crystal orientation of the channel region along the direction from the source region to the drain region is <100>. 3. The transistor according to claim 1, wherein the chemical molar ratio of Ge in the source region and the drain region is smaller than the chemical molar ratio of Ge in the channel region. 4. The transistor according to claim 1, wherein the chemical molar ratio of Ge in the source region and the drain region is the same. 5 . The transistor according to claim 1 , wherein BF ₂ is selected to dope both ends of the substrate to form a source region and a drain region, and the doping concentration is 1e20/cm ³ . 6. The transistor according to claim 1, wherein the chemical molar ratio of Ge in the source region and the drain region is 1%-100%. 7. The transistor according to claim 1, wherein the chemical molar ratio of Ge in the channel region is 1%-100%. 8. The transistor according to claim 1, wherein the source and drain are P-type, and the channel region is N-type. 9. The transistor according to claim 1, wherein the polysilicon gate is cylindrical.