CN104241346B - Insulated gate bipolar transistor and method for making same - Google Patents

Abstract

The invention relates to the field of electronic devices, and discloses an insulated gate bipolar transistor and a preparation method thereof. In the present invention, the gate of the IGBT structure is not a whole piece, but the gate located on the field oxide layer is partially removed to reduce the area of the gate region, so that the static power consumption of the IGBT can be effectively Minimize the dynamic power consumption of the IGBT. The preparation of the IGBT with the gate structure only needs to modify the photolithographic layout accordingly, which is easy to operate and easy to produce in batches. Further, the use of the field stop region can be applied to high voltage and make the structure of the IGBT thinner. Further, doping impurities in the polysilicon gate makes its property closer to that of metal, and reduces the resistance value.

Description

Insulated gate bipolar transistor and method for making same

technical field

The invention relates to the field of electronic devices, in particular to an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT for short) and a preparation method thereof.

Background technique

In recent years, the demand for high-voltage IGBT devices has greatly increased in high-speed trains, large-scale mechanical equipment and other fields because of their strong traction and low power consumption. IGBT is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar junction transistor (Bipolar Junction Transistor, referred to as BJT) and an insulated gate field effect transistor (Metal-Oxide-Semiconductor Field Effect Transistor, referred to as MOSFET). The advantages of high input impedance and low conduction voltage drop.

However, as the breakdown voltage increases, the current capability of the high-voltage IGBT device decreases, which leads to an increase in the static conduction voltage drop and a corresponding increase in static power consumption. In order to reduce static power consumption, high-voltage IGBT devices, especially ultra-high-voltage IGBT devices with a breakdown voltage greater than _6500V , have a very wide junction field-effect transistor (JFET) region in the two P-body intervals. Large, so the gate-collector capacitance C _gc of the device will increase, thereby increasing the turn-off delay of the device, increasing the dynamic power consumption of the device, and affecting the application frequency of the device. Figure 1 is a schematic structural diagram of a high-voltage IGBT in the prior art, the high-voltage IGBT includes a drift region 1, a first body region 5A, a second body region 5B, a first doped region 6A, a second doped region 6B, Gate oxide layer 3 , field oxide layer 2 , gate 4 , insulating dielectric layer 7 , emitter 8 , field stop region 9 , collector region 10 and collector 11 .

One way to generally reduce C _gc is to increase the thickness d _oxide of the oxide layer under the gate of the JFET region, thereby reducing C _gs (s represents the silicon surface). But in fact, this method is very limited to reduce C _gc .

C _gc is formed by connecting C _gs and C _Sc in series, C _gs is the capacitance between the gate and the silicon surface, and C _Sc is the capacitance between the silicon surface and the collector.

c _gs =Aε ₀ ε _oxide /d _oxide , c _sc =Aε ₀ ε _silicon /d _silicon

Among them, A represents the area of the gate region corresponding to the JFET regions of two adjacent p-body regions, and ε ₀ is the vacuum dielectric constant. ε _oxide is the dielectric constant of the oxide layer under the gate, and d _oxide is the thickness of the oxide layer under the gate. ε _silicon is the dielectric constant of silicon, and d _silicon is the thickness of silicon.

ε _oxide =3.9, d _oxide =2μm (thick oxygen), 0.12μm (thin oxygen)

ε _silicon =11.9, d _silicon =40μm

c _sc /c _gs =ε _silicon d _oxide /ε _oxide d _silicon =1/6.55

Therefore, C _gc is mainly determined by C _sc , and increasing the thickness of the oxide layer under the gate can only reduce C _gs , and the reduction effect on the entire C _gc is very limited.

Another way to lower C _gc is to lower C _sc . It can be seen from the formula of C _sc that reducing C _sc can be realized by reducing the area of JFET. Reducing the JFET area will increase the static voltage drop, thereby increasing the static power consumption. Due to the existence of this pair of contradictions, only a middle-of-the-road solution can be adopted, that is, to choose an appropriate JFET area width to obtain a choice of static power consumption and dynamic power consumption. It is impossible to effectively reduce dynamic power consumption under the premise of keeping static power consumption unchanged.

Contents of the invention

The purpose of the present invention is to provide an insulated gate bipolar transistor and its preparation method, which can effectively reduce the gate-collector capacitance C _gc without reducing the static voltage drop of the IGBT, that is, keep its static power consumption unchanged. This results in lower dynamic power consumption.

In order to solve the above technical problems, an embodiment of the present invention discloses an insulated gate bipolar transistor, comprising a substrate of a first semiconductor type, the substrate has a first surface and a second surface, and the first surface and the second surface form a drift region of the first semiconductor type;

comprising a first body region and a second body region of a second semiconductor type adjacent the first surface of the substrate;

The first body region and the second body region respectively include a first doped region and a second doped region of the first semiconductor type, the first and second doped regions are separated from the drift region, and the first body region, the second doped region The two-body region, the first doped region, and the second doped region jointly form an emitter region, which is connected to the emitter through the first and second metal holes;

A field oxide layer is included on the first surface of the drift region between the first body region and the second body region, a gate oxide layer is included on the first surface not covered by the field oxide layer, the thickness of the field oxide layer is greater than that of the gate oxide layer The thickness of the gate oxide layer and the field oxide layer form a ladder structure;

The gate oxide layer and the field oxide layer between the first and second doped regions contain a gate, at least a part of the field oxide layer is not covered by the gate, the gate is connected to the outside through the third metal hole, and the gate Including an insulating dielectric layer;

A collector region of the second semiconductor type is included adjacent the second surface of the substrate, the collector region being connected to the collector electrode.

The embodiment of the present invention also discloses a preparation method of an insulated gate bipolar transistor, comprising the following steps:

providing a substrate of a first semiconductor type, the substrate having a first surface and a second surface forming a drift region of the first semiconductor type;

forming a field oxide layer corresponding to the drift region on the first surface of the substrate;

forming a gate oxide layer on the field oxide layer, the thickness of the field oxide layer is greater than the thickness of the gate oxide layer, and the gate oxide layer and the field oxide layer form a ladder structure on the first surface of the substrate;

forming a gate on the field oxide layer and its adjacent part of the gate oxide layer, at least a part of the field oxide layer not covered by the gate;

forming a first body region and a second body region of the second semiconductor type on both sides of the field oxide layer near the first surface of the substrate;

A first doped region and a second doped region of the first semiconductor type are formed in the first and second body regions, the gate is located on the gate oxide layer and the field oxide layer between the first and second doped regions, The first and second doped regions are spaced apart from the drift region, and the first body region, the second body region, the first doped region, and the second doped region jointly form an emission region;

forming an insulating dielectric layer on the gate;

Form first, second and third metal holes on the insulating dielectric layer and the gate oxide layer respectively, and deposit in the first and second metal holes to form an emitter connected to the emitter region, and in the third Deposited in the metal hole to connect the gate to the outside;

forming a collector region of the second semiconductor type proximate the second surface of the substrate;

A collector electrode connected to the collector region is formed on the second surface of the substrate.

Compared with the prior art, the embodiment of the present invention has the main difference and its effects in that:

In the present invention, the gate of the IGBT structure is not a whole piece, but the gate located on the thick field oxide layer is partially removed to reduce the area of the gate region, so as not to reduce the static voltage drop of the IGBT, that is, to maintain its When the static power consumption remains unchanged, the dynamic power consumption of the IGBT can be effectively reduced; the preparation of the IGBT with this gate structure only needs to modify the photolithography layout accordingly, and the operation is simple and easy for mass production.

Further, the use of the field stop region can be applied to high voltage and make the structure of the IGBT thinner.

Further, doping impurities in the polysilicon gate makes its property closer to that of metal, and reduces the resistance value.

Description of drawings

FIG. 1 is a schematic structural diagram of an insulated gate bipolar transistor in the prior art;

2 is a schematic structural diagram of an insulated gate bipolar transistor in the first embodiment of the present invention;

3 is a schematic structural diagram of an insulated gate bipolar transistor in a second embodiment of the present invention;

4 is a schematic flowchart of a method for manufacturing an insulated gate bipolar transistor in a third embodiment of the present invention;

5a to 5i are schematic diagrams of various steps of a method for manufacturing an insulated gate bipolar transistor in the third embodiment of the present invention;

FIG. 6 is a schematic diagram of forming a field stop region in a method for manufacturing an IGBT according to the fourth embodiment of the present invention.

detailed description

In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that without these technical details and various changes and modifications based on the following implementation modes, the technical solution claimed in each claim of the present application can be realized.

In order to make the purpose, technical solution and advantages of the present invention clearer, the following will further describe the implementation of the present invention in detail in conjunction with the accompanying drawings.

Like reference numerals designate like parts throughout the drawings. The drawings are not intentionally scaled according to the actual size, and the emphasis is on illustrating the gist of the present invention.

The first embodiment of the present invention relates to an IGBT, and FIG. 2 is a schematic structural diagram of the IGBT. Specifically, as shown in Figure 2, the IGBT includes:

A substrate of a first semiconductor type, the substrate having a first surface and a second surface forming a drift region 1 of the first semiconductor type. It can be understood that the substrate material may be single crystal silicon, strained silicon, germanium, silicon germanium, etc., and the semiconductor substrate may also be a semiconductor substrate with an insulating buried layer. Theoretically, an N-type or P-type substrate can be used. Preferably, the present invention uses a lightly doped N-type substrate.

A first body region 5A and a second body region 5B of the second semiconductor type are contained near the first surface of the substrate.

The first body region 5A and the second body region 5B respectively include a first doped region 6A and a second doped region 6B of the first semiconductor type, and the first doped region 6A and the second doped region 6B are the same as the drift region 1 In addition, the first body region 5A, the second body region 5B, the first doped region 6A, and the second doped region 6B together form an emitter region, which is connected to the emitter 8 through the first and second metal holes.

A field oxide layer 2 is included on the first surface of the drift region 1 between the first body region 5A and the second body region 5B, and a gate oxide layer 3 is included on the first surface not covered by the field oxide layer 2. The field oxide layer The thickness of the gate oxide layer 2 is greater than the thickness of the gate oxide layer 3, and the gate oxide layer 3 and the field oxide layer 2 form a ladder structure.

The gate oxide layer 3 and the field oxide layer 2 between the first doped region 6A and the second doped region 6B contain a gate 4, at least a part of the field oxide layer 2 is not covered by the gate 4, and the gate 4 It is connected with the outside through the third metal hole. Preferably, in this implementation manner, the gate 4 is polysilicon, and the polysilicon is doped with impurities of the first semiconductor type. Doping impurities in the polysilicon gate 4 can make its properties closer to that of metals and reduce the resistance value.

It can be understood that in other embodiments of the present invention, the material of the gate 4 can also be metal, or polysilicon not doped with impurities.

The gate 4 includes an insulating dielectric layer 7. Preferably, the insulating dielectric layer 7 in this embodiment is made of phosphosilicate glass. It can be understood that in other embodiments of the present invention, other materials such as silicon glass and borophosphosilicate glass may also be used for the insulating medium layer.

A collector region 10 of the second semiconductor type is contained near the second surface of the substrate, the collector region 10 being connected to a collector electrode 11 .

In this implementation manner, preferably, the first semiconductor type is N-type, and the second semiconductor type is P-type. It can be understood that, in other implementation manners of the present invention, the first semiconductor type may also be P-type, and the second semiconductor type may be N-type.

It should be pointed out that, in this embodiment, the doping concentration of the first body region 5A and the second body region 5B is higher than that of the drift region 1, and the doping concentration of the first doping region 6A and the second doping region 6B The impurity concentration is higher than the doping concentration of the first body region 5A and the second body region 5B, the doping concentration of the collector region 10 is higher than the doping concentration of the drift region 1, and the doping concentration of the above-mentioned regions is known to those skilled in the art common knowledge, and will not be repeated here.

In the embodiment of the present invention, the gate of the IGBT structure is not a whole piece, but the gate located on the thick field oxide layer is partially removed to reduce the area of the gate region, so as not to reduce the static voltage drop of the IGBT, that is, In the case of keeping its static power consumption unchanged, the dynamic power consumption of the IGBT can be effectively reduced.

The second embodiment of the present invention relates to an insulated gate bipolar transistor. FIG. 3 is a schematic structural diagram of the IGBT. The second embodiment is improved on the basis of the first embodiment. Specifically, as shown in FIG. 3 , the main improvements are as follows:

A field stop region 9 of the first semiconductor type is also included near the second surface of the substrate. The field stop region 9 is above the collector region 10. The doping concentration of the field stop region 9 is higher than that of the drift region 1. The doping concentration of the electrical region 10 is higher than that of the field stop region 9 .

Adopting the field stop region 9 can be applied to high voltage and make the structure of the IGBT thinner.

In order to better understand the present invention, as a preferred example of the present invention, the material and doping concentration parameters of each component of the IGBT will be described in detail below, but it is not limited thereto.

At present, most IGBT devices are made on silicon wafers. In this preferred example, the wafer is an N-type material with a doping concentration of 10 ¹² cm ^-3 to 10 ¹³ cm ^-3 , which is N-drift District 1.

The P body region (namely the first body region 5A and the second body region 5B) is formed by doping the N-drift region 1 with P-type impurity boron, and its concentration is on the order of 10 ¹⁷ cm ^-3 . It can be understood that in other embodiments of the present invention, aluminum can also be used as the P-type impurity. The N+ region (that is, the first doped region 6A and the second doped region 6B) is formed by doping the P body region with a high concentration of arsenic or phosphorus, and its concentration is on the order of 10 ²⁰ cm ^-3 .

The P body region and the N+ region are shorted together to form the emitter 8 of the IGBT.

A layer is grown on the surface (ie, the first surface) of the wafer (equivalent to the substrate) thick _{SiO2 gate} oxide 3. Corresponding to the surface of the wafer in the middle of the two P body regions, there is a thick _{SiO 2} field oxide layer 2 with a thickness of about 2 μm. It can be understood that in other embodiments of the present invention, the thickness of the gate oxide layer 3 can also be etc., the thickness of the field oxide layer 2 may also be 1.9 μm, 2.1 μm or the like.

Preferably, above the oxide layer is thick polysilicon. There is heavily doped phosphorus in polysilicon, the concentration is on the order of 10 ²⁰ cm ^-3 . Polysilicon constitutes the gate 4 of the IGBT, which is partially removed on the field oxide layer 2, and the remaining gates 4 are connected to each other and to the outside of the device through metal. It can be understood that in other embodiments of the present invention, the gate 4 can also be metal, or polysilicon doped with other impurities such as aluminum and arsenic, or undoped polysilicon, and the gate thickness can also be , Wait.

Furthermore, it will be appreciated that partially removed polysilicon electrodes can only be located on thick field oxide layers. This prevents the current capability of the device from degrading, thereby keeping its quiescent voltage drop constant.

On the polysilicon structure is an insulating dielectric layer 7 formed of phosphosilicate glass with a thickness of 2 μm. It can be understood that in other embodiments of the present invention, the insulating dielectric layer can also be made of other materials such as silicon glass, borophosphosilicate glass, and the thickness can also be 1.9 μm, 2.1 μm, or the like.

The backside of the wafer (that is, the second surface) is doped with N-type impurities at a concentration of 10 ¹⁵ cm ⁻³ , and its thickness is about 10 μm, which is the field stop region 9 . It can be understood that, in other embodiments of the present invention, the thickness of the field stop region 9 may also be 9 μm, 11 μm or the like.

Finally, a thin layer of P-type impurity boron with a thickness of 0.5 μm and a concentration of 10 ¹⁷ cm ^-3 is doped on the back of the wafer, which is the collector region 10 of the IGBT. The metal deposited on the collector area is the collector electrode 11 of the IGBT. It can be understood that in other embodiments of the present invention, aluminum can also be used as the P-type impurity, and the thickness of the thin layer can also be 0.4 or 0.6 μm.

It can be understood that the above is only a preferred example of the present invention, and the parameters such as doping impurities, doping concentration, and thickness of each region are not limited to the above-mentioned settings. The common knowledge of personnel is not repeated here.

The simulation results show that through the above improvements, the conduction voltage drop of the device is basically unchanged, only increased from 3.885v to 3.890v, but the gate collector capacitance Cgc is only 1/2 of the original, from the original 0.11nF, reduced to 0.05nF.

The third embodiment of the present invention relates to a method for manufacturing an insulated gate bipolar transistor. FIG. 4 is a schematic flowchart of a method for manufacturing an IGBT in the third embodiment of the present invention. The preparation method of the insulated gate bipolar transistor comprises the following steps:

In step 101, a substrate of a first semiconductor type is provided, the substrate has a first surface and a second surface, and the first surface and the second surface form a drift region 1 of the first semiconductor type, as shown in FIG. 5a. It can be understood that the substrate material may be single crystal silicon, strained silicon, germanium, silicon germanium, etc., and the semiconductor substrate may also be a semiconductor substrate with an insulating buried layer. Theoretically, an N-type or P-type substrate can be used. Preferably, the present invention uses a lightly doped N-type substrate.

Then enter step 102, and form a field oxide layer 2 corresponding to the drift region on the first surface of the substrate, as shown in FIG. 5b.

Then enter step 103, form gate oxide layer 3 on field oxide layer 2, the thickness of field oxide layer 2 is greater than the thickness of gate oxide layer 3, gate oxide layer 3 and field oxide layer 2 form a ladder structure on the first surface of the substrate , as shown in Figure 5c.

Then enter step 104, forming gate 4 on field oxide layer 2 and its adjacent part of gate oxide layer 3, at least a part of field oxide layer 2 is not covered by gate 4, as shown in FIG. 5d. Preferably, in this implementation manner, the gate 4 is polysilicon, and the polysilicon is doped with impurities of the first semiconductor type. Doping impurities in the polysilicon gate 4 can make its properties closer to that of metals and reduce the resistance value.

It can be understood that in other embodiments of the present invention, the material of the gate 4 can also be metal, or polysilicon not doped with impurities.

Then enter step 105, forming a first body region 5A and a second body region 5B of the second semiconductor type on both sides of the field oxide layer 2 near the first surface of the substrate, as shown in FIG. 5e.

Then enter step 106, form the first doped region 6A and the second doped region 6B of the first semiconductor type in the first and second body regions 5A and 5B, and the gate 4 is located in the first and second doped regions 6A On the gate oxide layer 3 and the field oxide layer 2 between , 6B, the first and second doped regions 6A, 6B are spaced from the drift region 1, and the first body region, the second body region, the first doped region region and the second doped region together form the emitter region, as shown in Figure 5f.

Then enter step 107, and form an insulating dielectric layer 7 on the gate 4, as shown in FIG. 5g. Preferably, the insulating dielectric layer 7 in this embodiment is made of phosphosilicate glass. It can be understood that in other embodiments of the present invention, other materials such as silicon glass and borophosphosilicate glass may also be used for the insulating medium layer.

Then enter step 108, respectively form the first, second and third metal holes on the insulating dielectric layer 7 and the gate oxide layer 3, and deposit in the first and second metal holes to form the emitter connected to the emitter region. electrode 8, and deposited in the third metal hole to connect the gate 4 to the outside, as shown in FIG. 5h.

Then enter step 109, forming a collector region 10 of the second semiconductor type near the second surface of the substrate, as shown in FIG. 5i.

Afterwards, enter step 110 , and form a collector electrode 11 connected to the collector region 10 on the second surface of the substrate to form a structure as shown in FIG. 2 .

Thereafter, this flow ends.

In this implementation manner, preferably, the first semiconductor type is N-type, and the second semiconductor type is P-type. It can be understood that, in other implementation manners of the present invention, the first semiconductor type may also be P-type, and the second semiconductor type may be N-type.

It should be pointed out that, in this embodiment, the doping concentration of the first body region 5A and the second body region 5B is higher than that of the drift region 1, and the doping concentration of the first doping region 6A and the second doping region 6B The impurity concentration is higher than the doping concentration of the first body region 5A and the second body region 5B, the doping concentration of the collector region 10 is higher than the doping concentration of the drift region 1, and the doping concentration of the above-mentioned regions is known to those skilled in the art common knowledge, and will not be repeated here.

It can be understood that the above steps can be etched by plasma etching, wet etching and other processes, and deposited by chemical vapor deposition (chemical vapor deposition, referred to as "CVD"), electroplating, sputtering, thermal oxidation and other processes. , and each doped region is formed by ion implantation, alloying, diffusion and other processes. Since these processes are well known to those skilled in the art, details are not described herein.

In this embodiment, the above steps are based on the self-alignment process of the polysilicon gate and the doped regions on both sides. It can be understood that in other embodiments of the present invention, the steps and processes for preparing IGBTs with gates made of other materials will be slightly different. product gate, but as long as it conforms to the main idea of the present invention, it is within the protection scope of the present invention.

In the embodiment of the present invention, the gate of the IGBT structure is not a whole piece, but the gate located on the thick field oxide layer is partially removed to reduce the area of the gate region, so as not to reduce the static voltage drop of the IGBT, that is, In the case of keeping its static power consumption unchanged, the dynamic power consumption of the IGBT can be effectively reduced. The preparation of the IGBT with the gate structure only needs to modify the photolithographic layout accordingly, which is easy to operate and easy to produce in batches.

This embodiment is a method embodiment corresponding to the first embodiment, and this embodiment can be implemented in cooperation with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and will not be repeated here in order to reduce repetition. Correspondingly, the relevant technical details mentioned in this implementation manner can also be applied in the first implementation manner.

The fourth embodiment of the present invention relates to a method for manufacturing an insulated gate bipolar transistor. The fourth embodiment is improved on the basis of the third embodiment, and the main improvements are as follows:

After step 101 and before step 102, the following steps are also included:

A field stop region 9 of the first semiconductor type is formed near the second surface of the substrate to form an IGBT as shown in FIG. 3 . The field stop region 9 is above the collector region 10 , the doping concentration of the field stop region 9 is higher than that of the drift region 1 , and the doping concentration of the collector region 10 is higher than that of the field stop region 9 .

Adopt field stop region, can be applied to high voltage, and make the structure of IGBT thinner.

In addition, in order to better understand the present invention, as a preferred example of the present invention, the fabrication method of the edge-gate bipolar transistor will be described in detail below in combination with various process parameters and possible process methods, but it is not limited thereto.

First prepare a wafer with a resistivity of 660 ohm-cm and a thickness of 560 μm, as shown in Figure 5a. Implant phosphorus or arsenic with a dose of 1e ¹² cm ^-2 on the back of the wafer, and form a field stop region 9 with a thickness of 10 μm by advancing, as shown in FIG. 6 . It can be understood that, in other embodiments of the present invention, the thickness of the field stop region 9 may also be 9 μm, 11 μm or the like.

Then a field oxide layer 2 with a thickness of 2 μm is thermally grown on the front side (ie, the first surface) of the wafer (equivalent to the substrate), and a thick oxide layer is formed between the two P body regions by photolithography, as shown in Figure 5b.

reheat growth Thick gate oxide layer 3, as shown in Figure 5c. It can be understood that in other embodiments of the present invention, the thickness of the gate oxide layer 3 can also be etc., the thickness of the field oxide layer 2 may also be 1.9 μm, 2.1 μm or the like.

Deposit on the surface of the gate oxide layer 3 Thick self-doped polysilicon, that is, doping with impurities while depositing polysilicon, the doping concentration of the polysilicon formed by this process is relatively uniform, and then the polysilicon structure as shown in Figure 5d is formed by photolithography and etching, which constitutes Gate 4 of the IGBT. From FIG. 5d, the gate 4 is partially removed on the field oxide layer 2, and the remaining gates 4 are connected to each other. It can be understood that in other embodiments of the present invention, the gate 4 can also be metal, or polysilicon doped with other impurities such as aluminum and arsenic, or undoped polysilicon, and the process steps will be different, and The gate thickness can also be Wait.

Boron is then implanted and formed by advancing the P body region of the IGBT (ie the first body region 5A and the second body region 5B), as shown in Figure 5e. It can be understood that in other embodiments of the present invention, aluminum can also be used as an impurity to form the P body region.

Arsenic or phosphorus is then implanted to form the N+ region of the IGBT (that is, the first doped region 6A and the second doped region 6B), as shown in FIG. 5f.

Deposit phosphosilicate glass with a thickness of 2 μm on the polysilicon structure to form an insulating dielectric layer 7 and form metal holes by photolithography as shown in Figure 5g. It can be understood that in other embodiments of the present invention, the insulating dielectric layer 7 can also be made of other materials such as silicon glass, borophosphosilicate glass, and the thickness can also be 1.9 μm, 2.1 μm, and the like.

Deposit aluminum with a thickness of 4 μm to form the emitter 8 of the IGBT, as shown in Figure 5h. Boron is implanted at a dose of 1e ¹⁴ cm ^-2 on the backside of the wafer (that is, the second surface) to form the collector region of the IGBT, as shown in Figure 5i. Finally, AlTiNiAg is deposited on the back of the wafer to form the collector of the IGBT, as shown in Figure 3. It can be understood that in other embodiments of the present invention, aluminum can also be used as the P-type impurity, and other metal materials such as copper can also be used as the material of the collector and emitter.

It can be understood that the above is only a preferred example of the present invention, and the parameters such as doping impurities, doping dose, and thickness of each region are not limited to the above settings. The common knowledge of those skilled in the art will not be repeated here.

This embodiment is a method implementation corresponding to the second embodiment, and this embodiment can be implemented in cooperation with the second embodiment. The relevant technical details mentioned in the second embodiment are still valid in this embodiment, and will not be repeated here to reduce repetition. Correspondingly, the relevant technical details mentioned in this embodiment mode can also be applied in the second embodiment mode.

In summary, only reducing the area of the gate plate without reducing the area of the JFET region will not affect the current capability of the device, and the static on-state voltage drop will not increase, so that the Cgc can be effectively reduced, thereby Reduces dynamic power consumption of the device without increasing static power consumption.

It should be noted that in the claims and description of this patent, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or Any such actual relationship or order between such entities or operations is implied. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Although the present invention has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the present invention. The spirit and scope of the invention.

Claims (10)

1. a kind of igbt, it is characterised in that the substrate comprising the first semiconductor type, the substrate have the One surface and second surface, the first surface and second surface form the drift region of the first semiconductor type；

Include the first body area and the second body area of the second semiconductor type near the first surface of the substrate；

The first body area and the second body area include first doped region and the second doped region of the first semiconductor type respectively, First, second doped region with the drift region separately, also, the first body area, the second body area, the first doped region, Second doped region is collectively forming launch site, is connected with emitter stage by first, second metal aperture；

Include field oxide on the first surface of the drift region between the first body area and the second body area, not described Include gate oxide on the first surface that field oxide is covered, the thickness of the field oxide is more than the thickness of the gate oxide Degree, the gate oxide form hierarchic structure with the field oxide；

Include grid on gate oxide and field oxide between first, second doped region, the field oxide is up to A rare part is not covered by the grid, and the grid is included absolutely on the grid by the 3rd metal aperture and external connection Edge dielectric layer；

Include the collecting zone of the second semiconductor type near the second surface of the substrate, the collecting zone is connected with colelctor electrode Connect；

The each several part of the grid is connected with each other.

2. igbt according to claim 1, it is characterised in that first semiconductor type is N-type, Second semiconductor type is p-type.

3. igbt according to claim 1, it is characterised in that the doping in the first, second body area Doping content of the concentration higher than the drift region, the doping content of first doped region and the second doped region is higher than described the One area and the doping content in the second body area；

Doping content of the doping content of the collecting zone higher than the drift region.

4. igbt according to any one of claim 1 to 3, it is characterised in that in the substrate Also include the field cut-off region of the first semiconductor type near second surface, the field cut-off region is above the collecting zone, described Doping content of the doping content of field cut-off region higher than the drift region, the doping content of the collecting zone are ended higher than the field The doping content in area.

5. igbt according to any one of claim 1 to 3, it is characterised in that the grid is many Crystal silicon, in the polysilicon mixed with the first semiconductor type impurity.

6. a kind of preparation method of igbt, it is characterised in that comprise the following steps：

The substrate of one first semiconductor type is provided, the substrate has first surface and second surface, the first surface and Two surfaces form the drift region of the first semiconductor type；

Field oxide is formed corresponding to the drift region on the first surface of the substrate；

Gate oxide is formed on the field oxide, and the thickness of the field oxide is more than the thickness of the gate oxide, institute Stating gate oxide, hierarchic structure is formed on the first surface of the substrate with the field oxide；

Grid is formed on the field oxide and its neighbouring part gate oxide, at least part of on the field oxide Do not covered by the grid；

The field oxide both sides near the first surface of the substrate formed the first body area of the second semiconductor type and Second body area；

First doped region and the second doped region of the first semiconductor type, the grid is formed in the first, second body area It is located on the gate oxide and field oxide between first, second doped region, first, second doped region and the drift Move area separately, also, the first body area, the second body area, the first doped region, the second doped region are collectively forming launch site；

Insulating medium layer is formed on the grid；

Form first, second, and third metal aperture on the insulating medium layer and the gate oxide respectively, and this first, Deposit to form the emitter stage being connected with the launch site in second metal aperture, and deposit so that described in the 3rd metal aperture Grid and external connection；

In the collecting zone that the second surface of the substrate is formed about the second semiconductor type；

The colelctor electrode being connected with the collecting zone is formed on the second surface of the substrate；

Wherein, each several part of the grid is connected with each other.

7. the preparation method of igbt according to claim 6, it is characterised in that first semiconductor Type is N-type, and second semiconductor type is p-type.

8. the preparation method of igbt according to claim 6, it is characterised in that described first, second The doping content of doping content of the doping content in body area higher than the drift region, first doped region and the second doped region is high In the first body area and the doping content in the second body area；

Doping content of the doping content of the collecting zone higher than the drift region.

9. the preparation method of the igbt according to any one of claim 6 to 8, it is characterised in that After the substrate of one first semiconductor type is provided, further comprising the steps of：

In the field cut-off region that the second surface of the substrate is formed about the first semiconductor type；

, above the collecting zone, the doping content of the field cut-off region is dense higher than the doping of the drift region for the field cut-off region Degree, the doping content of the collecting zone are higher than the doping content of the field cut-off region.

10. the preparation method of the igbt according to any one of claim 6 to 8, it is characterised in that institute Grid is stated for polysilicon, in the polysilicon mixed with the first semiconductor type impurity.