CN104201107B - Semiconductor devices and preparation method thereof - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor device, comprising: providing a substrate, the substrate includes an N well and a P well, a gate is formed on the substrate, and the gate respectively covers part of the N well. Well and part of the P well, first sidewalls are formed on both sides of the gate; a groove is formed in the N well, and the groove is located at the side of the first sidewall away from the gate One side; a second sidewall is formed on the sidewall of the groove and both sides of the grid, and the first sidewall is located between the second sidewall and the grid; in the P well A source is formed, and a drain is formed in the N well, and the groove is located between the drain and the gate. Meanwhile, the invention also provides a semiconductor device. The semiconductor device and the preparation method of the invention can improve the working voltage of the semiconductor device.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the technical field of drain-extended metal oxide semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background technique

An integrated circuit (integrated circuit) device includes a circuit composed of MOS (Metal Oxide Semiconductor) transistors. Such high-density circuits are commonly used in various electronic products. Many devices require MOS transistors to work under high voltage (greater than 5V). In order to increase the working voltage of devices, Extended Drain MOS (EDMOS for short) devices are often used at present.

As shown in FIG. 1 , this is a simple schematic diagram of an existing EDMOS device 1 . An N well 11 and a P well 12 are formed in the substrate 10 , a drain 13 is formed in the N well 11 , a source 14 is formed in the P well 12 , and an isolation structure 15 is formed in the substrate 10 . A gate 21 is formed on the substrate 10 , and the gate 21 respectively covers part of the N well 11 and part of the P well 12 . The source 14 is adjacent to the gate 21, and there is a drain extension region 16 between the drain 13 and the gate 21. The drain extension region 16 is covered with a barrier layer 30, and is formed in a self-aligned polysilicon (salicide) The formation of salicide in the drain extension region 16 is blocked during the process. The EDMOS device 1 uses an N well 11 , and the N well 11 increases the distance between the drain 13 and the source 14 , which fully increases the working voltage of the EDMOS device 1 . The EDMOS device 1 improves the breakdown voltage (BVdss) and reduces the on-resistance (Rdson), achieving a trade-off between the breakdown voltage and the on-resistance (trade-off). Therefore, the EDMOS device 1 is widely used in integrated circuit devices.

However, as the size of the semiconductor device shrinks, the size of the drain extension region 16 decreases accordingly, so that the breakdown voltage of the EDMOS device 1 decreases, so that it cannot meet the requirement of high voltage operation.

Contents of the invention

The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the breakdown voltage of the semiconductor device, so that the working voltage of the semiconductor device can be improved.

In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:

A substrate is provided, the substrate includes an N well and a P well, and a gate is formed on the substrate, and the gate respectively covers part of the N well and part of the P well, and the two sides of the gate are The side is formed with a first side wall;

forming a groove in the N well, the groove being located on a side of the first sidewall away from the gate;

forming second sidewalls on sidewalls of the groove and both sides of the grid, the first sidewalls being located between the second sidewalls and the grid; and

An ion implantation process is performed to form a source in the P well and a drain in the N well, and the groove is located between the drain and the gate.

Optionally, in the manufacturing method of the semiconductor device, between the step of forming a second sidewall on the sidewall of the groove and both sides of the gate and the step of performing an ion implantation process, further comprising:

A barrier layer covering the groove is formed on the substrate.

Optionally, in the manufacturing method of the semiconductor device, the barrier layer is a silicide barrier layer.

Optionally, in the manufacturing method of the semiconductor device, the P well further includes a lightly doped drain region, and the lightly doped drain region is located on both sides of the gate.

Optionally, in the manufacturing method of the semiconductor device, the material of the first sidewall is oxide.

Optionally, in the manufacturing method of the semiconductor device, the material of the second sidewall is nitride.

According to another aspect of the present invention, a semiconductor device is also provided, including:

A substrate, the substrate includes an N well and a P well, and a gate is formed on the substrate, and the gate covers part of the N well and part of the P well respectively, and the two sides of the gate are formed has a first side wall;

a groove located in the N well and located on a side of the first sidewall away from the gate;

a second sidewall located on both sides of the sidewall of the groove and the grid, the first sidewall located between the second sidewall and the grid; and

A source and a drain, the source is located in the P well, the drain is located in the N well, and the groove is located between the drain and the gate.

Optionally, in the semiconductor device, a barrier layer covering the groove is further formed on the substrate.

Optionally, in the semiconductor device, the barrier layer is a silicide barrier layer.

Optionally, in the semiconductor device, the P-well further includes lightly doped drain regions, and the lightly doped drain regions are located on both sides of the gate.

Optionally, in the semiconductor device, the material of the first sidewall is oxide.

Optionally, in the semiconductor device, the material of the second sidewall is nitride.

Compared with the prior art, the semiconductor device provided by the invention and its preparation method have the following advantages:

In the semiconductor device and its manufacturing method, a groove is formed in the N well, the groove is located between the drain and the gate, and the groove increases the gap between the source and the gate. The carrier flow path effectively increases the breakdown voltage without increasing the on-resistance, thereby increasing the working voltage of the semiconductor device.

Description of drawings

FIG. 1 is a schematic diagram of an EDMOS device in the prior art;

Fig. 2 is the flowchart of the preparation method of semiconductor device in an embodiment of the present invention;

3 to 7 are schematic diagrams of device structures in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

detailed description

The semiconductor device of the present invention and its preparation method will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the present invention beneficial effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The core idea of the present invention is to provide a method for preparing a semiconductor device, comprising the following steps:

In step S11, a substrate is provided, the substrate includes an N well and a P well, and a gate is formed on the substrate, and the gate respectively covers a part of the N well and a part of the P well, and the gate First side walls are formed on both sides of the pole;

Step S12, forming a groove in the N well, the groove being located on a side of the first sidewall away from the gate;

Step S13, forming second sidewalls on the sidewalls of the groove and both sides of the grid, the first sidewalls being located between the second sidewalls and the grid;

Step S14 , performing an ion implantation process to form a source in the P well and a drain in the N well, and the groove is located between the drain and the gate.

By adopting the above preparation method, the carrier flow path between the source and the gate is increased, and the breakdown voltage is effectively increased without increasing the on-resistance, thereby increasing the operating voltage of the semiconductor device.

According to the core idea of the present invention, a semiconductor device is also provided, including:

A substrate, the substrate includes an N well and a P well, and a gate is formed on the substrate, and the gate covers part of the N well and part of the P well respectively, and the two sides of the gate are formed has a first side wall;

a groove located in the N well and located on a side of the first sidewall away from the gate;

a second sidewall located on both sides of the sidewall of the groove and the grid, the first sidewall located between the second sidewall and the grid; and

A source and a drain, the source is located in the P well, the drain is located in the N well, and the groove is located between the drain and the gate.

Several embodiments of the semiconductor device and its preparation method are listed below to clearly illustrate the content of the present invention. It should be clear that the content of the present invention is not limited to the following examples. The improvement of technical means is also within the thought scope of the present invention.

Please refer to Fig. 2-Fig. 7 to specifically illustrate the semiconductor device and its preparation method of the present invention, wherein Fig. 2 is a flow chart of the preparation method of a semiconductor device in an embodiment of the present invention; Fig. 3 to Fig. 7 are an embodiment of the present invention Schematic diagram of the device structure in the fabrication method of the semiconductor device in .

As shown in Figure 2, step S11 is first performed, as shown in Figure 3, a substrate 100 is provided, the substrate 100 can be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, and the substrate 100 has a first A type of light doping. The substrate 100 includes an N well 110 with light doping of the second type and a P well 120 with light doping of the first type. In this embodiment, the first type is P type, and the second type is N type. In other embodiments of the present invention, the first type can also be N type, and the second type can also be Can be P type. The N well 110 includes a drain extension region 160 and a drain region 161, wherein the drain region 161 is used to form a drain, and the drain extension region 160 is located between the gate 210 and the drain region 161 In between, in subsequent steps, a barrier layer is formed on the drain region 161 , and in the step of ion implantation to form the drain, the barrier layer prevents; ions from being implanted into the drain region 161 .

A gate 210 is formed on the substrate 100, and the gate 210 respectively covers a part of the N well 110 and a part of the P well 120. Generally, there is also a gate 210 between the gate 210 and the substrate 100. A gate dielectric layer 211, the gate dielectric layer 211 may be a gate oxide layer or the like. First sidewalls 220 are formed on both sides of the gate 210. Preferably, the material of the first sidewalls 220 is oxide, such as silicon oxide.

In this embodiment, the P well 120 further includes lightly doped drain regions 141 and 142 , and the lightly doped drain region 141 is located on both sides of the gate 210 . In this embodiment, the lightly doped drain region 141 has the second type of heavy doping. In addition, the substrate 100 may further include an isolation structure 150 and the like, and the isolation structure 150 may be a shallow trench isolation and the like, which is understandable by those skilled in the art and will not be described in detail here.

Next, step S12 is performed. As shown in FIG. 4 , a groove 170 is formed in the N well 110 , and the groove 170 is located on a side of the first sidewall 220 away from the gate 210 . Generally, the groove 170 can be prepared by an etching process. In this embodiment, one side of the groove 170 is as close as possible to the first side wall 220, and the other side of the groove 170 is as close as possible to the drain region 161. In this embodiment , the groove 170 is located in the drain extension region 160 . The depth of the groove 170 is not specifically limited, generally, the deeper the groove 170 is, the higher the operating voltage required by the semiconductor device is.

Then proceed to step S13. As shown in FIG. 5 , second sidewalls 230 are formed on the sidewalls of the groove 170 and both sides of the grid 210 , and the first sidewalls 220 are located on the second sidewalls. 230 and gate 210. The formation process of the second sidewall 230 is preferably as follows: firstly form a second sidewall layer, the second sidewall layer covers the gate 210, the groove 170 and the surface of the substrate 100; The second sidewall layer is etched back to remove the second sidewall layer on the top of the gate 210, the top of the groove 170, and the surface of the substrate 100, and retain the sidewall of the gate 210 and the sidewall of the groove 170. The second side wall layer, so as to form the second side wall 230 . The above steps can be understood by those skilled in the art, and are not specifically shown in the figure. Preferably, the material of the second sidewall 230 is nitride, such as silicon nitride and the like.

Then step S14 is performed to perform an ion implantation process. As shown in FIG. 6, a source 140 is formed in the P well 120, and a drain 130 is formed in the N well 110. In this embodiment, the The drain 130 is formed in the drain region 161 , and the groove 170 is located between the drain 130 and the gate 210 .

In this embodiment, after step S14 , as shown in FIG. 7 , a barrier layer 300 covering the groove 170 is formed on the substrate 100 . Preferably, the barrier layer 300 is a silicide barrier layer. The silicide barrier layer can prevent salicide 260 from being formed in the N well 110 under the barrier layer 300 in subsequent steps.

After the above steps, a semiconductor device 2 as shown in FIG. 7 is formed, and the semiconductor device 2 includes: a substrate 100 , a groove 170 , a source 140 and a drain 130 . The substrate 100 includes an N well 110 and a P well 120, and a gate 210 is formed on the substrate 100, and the gate 210 covers a part of the N well 110 and a part of the P well 120 respectively, and the gate First sidewalls 220 are formed on both sides of the pole 210 . The groove 170 is located in the N well 110 and located on a side of the first sidewall 220 away from the gate 210 . The second sidewall 230 is located on the sidewall of the groove 170 and two sides of the grid 210 , and the first sidewall 220 is located between the second sidewall 230 and the grid 210 . The source 140 is located in the P well 120 , the drain 130 is located in the N well 110 , and the groove 170 is located between the drain 130 and the gate 210 .

When the semiconductor device 2 is working, power is supplied to the gate 210, the source 140 and the drain 130, as shown in FIG. Only after the groove 170 can flow into the gate 210, the setting of the groove 170 increases the flow path of the carrier 190, thereby increasing the size of the semiconductor device 2 without increasing the size of the semiconductor device 2. breakdown voltage; and, the setting of the groove 170 does not increase the on-resistance of the semiconductor device 2, so the semiconductor device 2 of the present invention effectively increases the on-resistance without increasing the on-resistance breakdown voltage, thereby increasing the operating voltage of the semiconductor device 2 . In the 65/55nm node MOS transistor manufacturing process, the operating voltage of the semiconductor device 2 can be increased to above 8V;

At the same time, the above-mentioned manufacturing method of the semiconductor device can be integrated into the manufacturing of the logic device, so that the semiconductor device 2 and the logic device can be prepared simultaneously by using one flow.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (6)

1. A method for preparing a semiconductor device, comprising: A substrate is provided, the substrate includes an N well and a P well, and a gate is formed on the substrate, and the gate respectively covers part of the N well and part of the P well, and the two sides of the gate are The side is formed with a first side wall; forming a groove in the N well, the groove being located on a side of the first sidewall away from the gate; forming second sidewalls on sidewalls of the groove and both sides of the grid, the first sidewalls being located between the second sidewalls and the grid; and An ion implantation process is performed to form a source in the P well and a drain in the N well, and the groove is located between the drain and the gate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming a second sidewall on the sidewall of the groove and both sides of the gate and the step of performing an ion implantation process room, also includes: A barrier layer covering the groove is formed on the substrate. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the barrier layer is a silicide barrier layer. 4. The method for preparing a semiconductor device according to any one of claims 1 to 3, wherein the P well further comprises a lightly doped drain region, and the lightly doped drain region is located at the gate of the gate. side. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the first sidewall is oxide. 6 . The method for manufacturing a semiconductor device according to claim 1 , wherein the material of the second sidewall is nitride.