CN104201101B - A kind of manufacturing method of double contact hole etch stop layer - Google Patents

Abstract

The invention discloses a method for manufacturing a double-contact hole etching stop layer, which comprises alternating silicon nitride layers and silicon oxide layers on a high tensile stress silicon nitride layer used as a contact hole etching stop layer on a MOS device. As the UV blocking layer in the PMOS region, the multi-layer stack of the PMOS region is subjected to selective UV curing treatment for the high tensile stress silicon nitride layers in the PMOS and NMOS regions to obtain high tensile stress with relatively low coverage on the PMOS region. The silicon nitride layer is covered with a high tensile stress silicon nitride layer with relatively high tensile stress on the NMOS region, so as to realize the etch stop layer of silicon nitride double contact holes with different high tensile stress in the PMOS and NMOS regions, which not only avoids the The negative effect of single-step high tensile stress silicon nitride deposition on the hole mobility of PMOS devices is avoided, and the complexity of the two-step silicon nitride deposition to form a double contact hole etch stop layer process is avoided, and the cost increase is realized. the electrical properties of the device.

Description

A kind of manufacturing method of double contact hole etch stop layer

technical field

The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and more particularly, to a method for manufacturing a double-contact hole etch stop layer based on strained silicon technology.

Background technique

With the development of the CMOS integrated circuit manufacturing process and the reduction of critical dimensions, many new methods have been applied to the device manufacturing process to improve device performance. The high-stress silicon nitride film is introduced into the integrated circuit manufacturing process because it can effectively improve the carrier mobility of the MOS tube, thereby increasing the operating speed of the device. The compressive stress in the direction of the PMOS channel can improve the hole mobility in the PMOS device, while the tensile stress in the direction of the NMOS channel can improve the electron mobility in the NMOS device.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a conventional device structure for forming an etch stop layer for a contact hole of a high-stress silicon nitride film on a MOS device. As shown in the figure, a high stress silicon nitride film 2 is formed on the MOS device 1 as a contact hole etch stop layer. In terms of device performance, a silicon nitride contact hole etch stop layer with high compressive stress is required on PMOS devices, while a silicon nitride contact hole etch stop layer with high tensile stress is required on NMOS devices. This requires the application of the Dual CESL process (dual contact hole etch stop layer process).

The traditional Dual CESL process requires two-step silicon nitride deposition. The main process is high tensile stress silicon nitride deposition (including UV curing process) → silicon oxide mask layer deposition → photolithography → removal of high tensile stress in the PMOS region Silicon nitride layer→high pressure stress silicon nitride deposition→lithography→removal of high pressure stress silicon nitride layer in NMOS region. Since two-step lithography is required in the conventional Dual CESL process to remove the high tensile stress silicon nitride in the PMOS region and the high pressure stress silicon nitride in the NMOS region, this process greatly increases the process cost and process complexity . Therefore, the single CESL process is widely used at present, that is, a single-step silicon nitride deposition process is used to form a CESL layer (contact hole etch stop layer). Generally speaking, since the electron mobility index in NMOS devices is more critical, the general Single CESL process is to use high tensile stress silicon nitride to form a contact hole etch stop layer in both the PMOS region and the NMOS region.

The high tensile stress silicon nitride film (High Tensile Stress SiN) is deposited in PECVD (plasma enhanced chemical vapor deposition system), the reactants are silane (SiH ₄ ) and ammonia (NH ₃ ), and radio frequency excitation is required The plasma keeps the reaction going. Since the silicon nitride film formed by this method contains a large amount of H (hydrogen atoms), its structure is loose, so that the stress cannot meet the requirements, only about 0.7Gpa. Therefore, the next step is to UV cure the film (ultraviolet light curing), using ultraviolet light to destroy the hydrogen bonds in the film, so that hydrogen atoms form hydrogen gas precipitation, and the remaining dangling bonds Si- and N- can form Si-N key. In this way, the spatial network structure of the silicon nitride film is changed, so that a high tensile stress silicon nitride film with satisfactory stress can be formed. At present, the stress limit of the tensile stress silicon nitride film deposited by PECVD is about 1.7 Gpa (after UV curing), which can significantly improve the performance of NMOS. Therefore, this silicon nitride film is usually used as a contact hole etching barrier, and its thickness is generally 300-600A.

However, the high tensile stress silicon nitride contact hole etch stop layer is formed simultaneously in the PMOS region and the NMOS region by the Single CESL process, and the existence of high tensile stress silicon nitride has an adverse effect on the electrical properties of the PMOS device, so After all, the Single CESL process is a compromise at the expense of hole mobility in PMOS devices. Therefore, how to avoid the negative impact of single-step high tensile stress silicon nitride deposition on PMOS devices and the complexity of the two-step silicon nitride deposition to form a double-contact etch stop layer process has become an important issue in the current industry.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the above-mentioned defects in the prior art, and to provide a method for making a double contact hole etching stop layer, by depositing a high tensile stress silicon nitride layer on a MOS device as a contact hole etching stop layer, depositing The amorphous carbon layer is used as the protective layer of the high tensile stress silicon nitride layer, and the multilayer layer composed of alternately composed of silicon nitride layers and silicon oxide layers is used as the ultraviolet light blocking layer in the PMOS region of the MOS device. The high tensile stress silicon nitride layer in the region is subjected to selective UV curing treatment to realize the high tensile stress silicon nitride double contact hole etch stop layer with different tensile stress in the PMOS and NMOS regions, which can avoid single-step high tensile stress. The negative effect of silicon nitride deposition on the hole mobility of PMOS devices can also avoid the complexity of the two-step silicon nitride deposition to form a double-contact etch stop layer process.

For achieving the above object, technical scheme of the present invention is as follows:

A method for manufacturing a double-contact hole etch stop layer, comprising the following steps:

Step 1: providing a MOS device, and depositing a high tensile stress silicon nitride layer on the MOS device as a contact hole etching stop layer;

Step 2: depositing an amorphous carbon layer on the high tensile stress silicon nitride layer as a protective layer of the high tensile stress silicon nitride layer;

Step 3: alternately depositing a silicon nitride layer and a silicon oxide layer on the amorphous carbon layer to form a multi-layer stack consisting of the silicon nitride layer and the silicon oxide layer as an ultraviolet light blocking layer;

Step 4: removing the stack in the NMOS region of the MOS device;

Step 5: performing ultraviolet light curing treatment on the high tensile stress silicon nitride layer;

Step 6: Remove the stack in the PMOS region of the MOS device, and then remove the amorphous carbon layer to form silicon nitride double contact holes with different high tensile stress on the MOS device. Etch stop Floor.

In the above technical solution, since the PMOS region still retains a multi-layered layer composed of alternating silicon nitride layers and silicon oxide layers during the UV curing process, and the multi-layered layer can pass through air, nitrogen with different refractive indices The dielectric interface between the silicon oxide layer and the silicon oxide layer reflects the ultraviolet light, so that the light intensity of the ultraviolet light is gradually attenuated during the process of reaching the underlying high tensile stress silicon nitride layer through the multilayer stack and the amorphous carbon layer. The number of repetitions of alternating deposition of silicon nitride and silicon oxide layers determines the intensity of UV light that eventually reaches the high tensile stress silicon nitride layer. Therefore, after UV curing, the increase of the tensile stress of the high tensile stress silicon nitride layer in the PMOS region will be significantly affected. This relatively low tensile stress state significantly reduces the detrimental effect on the electrical performance of the PMOS device. As for the high tensile stress silicon nitride layer in the NMOS region, since the multilayer stack consisting of alternating silicon nitride layers and silicon oxide layers has been removed, the UV curing process will not be affected. After the UV curing process, The high tensile stress silicon nitride layer in this region can reach the ultimate tensile stress of about 1.7 Gpa, which can significantly improve the electron mobility in NMOS devices.

In the present invention, a multi-layered layer composed of alternately composed silicon nitride layers and silicon oxide layers is used as the ultraviolet light blocking layer in the PMOS region, and the high tensile stress silicon nitride layer in the PMOS and NMOS regions is subjected to a selective ultraviolet light curing process. The etch stop layer of silicon nitride double contact holes with different high tensile stress in the PMOS and NMOS regions can cover the high tensile stress silicon nitride layer with relatively low tensile stress on the PMOS region and the tensile stress on the NMOS region. Relatively high tensile stress silicon nitride layer. Therefore, the present invention can avoid the negative influence of the single-step high tensile stress silicon nitride deposition on the PMOS device, and also avoid the complexity of the two-step silicon nitride deposition to form the double contact hole etch stop layer process. Moreover, the process method of the present invention is simpler and lower in cost than the traditional double-contact hole etching stop layer process.

Preferably, in step 1, the deposition thickness of the high tensile stress silicon nitride layer is 300-1000A.

Preferably, in step 2, the deposition thickness of the amorphous carbon layer is 1000-5000A.

Preferably, in step 3, the number of the silicon nitride layers in the stack is 3 or more, and the number of the silicon oxide layers is 2 or more.

Preferably, in step 3, the uppermost layer in the stack is the silicon nitride layer.

Preferably, in step 3, the thickness of each layer of the silicon nitride layer is 100-300A.

Preferably, in step 3, the thickness of each silicon oxide layer is 100-300A.

Preferably, in step 4, a photolithography process is used to cover the PMOS region of the MOS device with photoresist, and then a dry etching process is used to remove the stack of the NMOS region of the MOS device.

Preferably, in step 5, ultraviolet light with a wavelength of 190-400 nm is used to perform ultraviolet light curing treatment on the high tensile stress silicon nitride layer.

Preferably, in step 6, the photoresist in the PMOS region of the MOS device is first removed by a plasma oxidation process, then the stack in the PMOS region of the MOS device is removed by a dry etching process, and finally plasma oxidation is used. The process removes the amorphous carbon layer.

It can be seen from the above technical solutions that the present invention deposits a high tensile stress silicon nitride layer on the MOS device as a contact hole etching stop layer, and an amorphous carbon layer is deposited as a protective layer for the high tensile stress silicon nitride layer. On the amorphous carbon layer, a multilayer layer consisting of alternating silicon nitride layers and silicon oxide layers is used as an ultraviolet light blocking layer in the PMOS region of the MOS device, and the high tensile stress silicon nitride layer in the PMOS and NMOS regions of the MOS device is selected. A high tensile stress silicon nitride layer with relatively low tensile stress is obtained on the PMOS region, and a high tensile stress silicon nitride layer with relatively high tensile stress is covered on the NMOS region. Silicon nitride double-contact etch stop layer with different high tensile stress regions, which can not only avoid the negative impact of single-step high tensile stress silicon nitride deposition on the hole mobility of PMOS devices, but also avoid two-step silicon nitride deposition The complexity of the process of forming the double contact hole etch stop layer. Moreover, the process method of the present invention is simpler and lower in cost than the traditional double-contact hole etch stop layer process, and thus has a significant improvement in improving the electrical performance of the device at a lower cost.

Description of drawings

1 is a schematic diagram of a device structure for forming a contact hole etch stop layer of a high-stress silicon nitride film on a MOS device in the prior art;

2 is a flow chart of a method for manufacturing a double-contact hole etching stop layer of the present invention;

3 to 11 are schematic diagrams of device structures for fabricating a double-contact hole etch stop layer according to the fabrication method of FIG. 2 according to an embodiment of the present invention;

FIG. 12 is an enlarged schematic view of a partial structure of the multilayer stack.

Detailed ways

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Of course, the present invention is not limited to the following specific embodiments, and general substitutions known to those skilled in the art are also covered within the protection scope of the present invention.

It should be noted that, in the following embodiments, the device structure formed by the method for fabricating the double-contact hole etch stop layer of the present invention is described in detail by using the schematic diagrams of FIGS. 3 to 12 . When describing the embodiments of the present invention in detail, for the convenience of description, each schematic diagram is not drawn in accordance with the general scale and partially enlarged and omitted, therefore, it should be avoided as a limitation of the present invention.

Please refer to FIG. 2 . FIG. 2 is a flow chart of a method for fabricating a double-contact hole etch stop layer according to the present invention. Meanwhile, please refer to FIG. 3 to FIG. 11 and FIG. 12. FIG. 3 to FIG. 11 are schematic diagrams of the device structure of a double-contact hole etch stop layer according to the manufacturing method of FIG. 2 according to an embodiment of the present invention; An enlarged schematic view of the partial structure of the silicon nitride-silicon oxide multilayer stack of the light blocking layer. The device structures illustrated in FIGS. 3 to 11 correspond to the fabrication steps in FIG. 2 respectively, so as to facilitate the understanding of the method of the present invention.

As shown in FIG. 2 , the present invention provides a method for manufacturing a double-contact hole etching stop layer, including:

As shown in block 1, step 1: a MOS device is provided, and a high tensile stress silicon nitride layer is deposited on the MOS device as a contact hole etch stop layer.

Referring to FIG. 3 , a high tensile stress silicon nitride layer 4 is deposited on the fabricated MOS device 3 as a contact hole etch stop layer. The fabrication process of the MOS device 3 is the same as that of the prior art. The MOS device 3 has an NMOS region 9 and a PMOS region 8 . The silicon nitride layer 4 may be formed by deposition using a plasma-enhanced chemical vapor deposition (PECVD) method, and the reactive gases may include SiH ₄ (silane) and NH ₃ (ammonia), but are not limited thereto. The deposition thickness is 300-1000A. The reaction process requires the use of radio frequency to excite the plasma to maintain the reaction. As an example, the deposition thickness of the silicon nitride layer 4 can be 600A, and the stress of the silicon nitride layer 4 is about 0.7Gpa at this time.

As shown in block 2, step 2: depositing an amorphous carbon layer on the high tensile stress silicon nitride layer as a protective layer of the high tensile stress silicon nitride layer.

Referring to FIG. 4 , an amorphous carbon layer 5 is deposited on the high tensile stress silicon nitride layer 4 as a protective layer for the high tensile stress silicon nitride layer. In the subsequent steps, since the ultraviolet light blocking layer on the amorphous carbon layer needs to be removed (see the description later), in order to avoid damage to the high tensile stress silicon nitride layer when the ultraviolet light blocking layer is removed, this non- The crystalline carbon layer 5 is used as an etch stop layer for the high tensile stress silicon nitride layer when removing the ultraviolet light blocking layer to protect the underlying high tensile stress silicon nitride layer 4 thin film. The thickness of the amorphous carbon layer 5 can be 1000-5000A, and can be formed by using an existing process method. As an example, an amorphous carbon layer 5 having a thickness of 3000 Å may be deposited on the high tensile stress silicon nitride layer 4 .

As shown in Box 3, step 3: alternately depositing silicon nitride layers and silicon oxide layers on the amorphous carbon layer to form a multi-layer stack composed of the silicon nitride layers and the silicon oxide layers, as UV light blocking layer.

Referring to FIG. 5 , a stack 6 is deposited on the amorphous carbon layer 5 , and the stack 6 is used as a PMOS region 8 when the high tensile stress silicon nitride layer 4 is subjected to ultraviolet light curing treatment in a subsequent step. The ultraviolet light blocking layer is formed to reduce the radiation intensity of ultraviolet light to the high tensile stress silicon nitride layer 4 of the PMOS region 8 (for details, please refer to the description later).

Referring to FIG. 12 , the stack 6 in FIG. 5 is composed of silicon nitride layers and silicon oxide layers alternately deposited in sequence. As a preferred embodiment of the present invention, the stack 6 consists of 3 layers of silicon nitride layers 10-1, 10-2, 10-3 and 2 layers of silicon oxide layers 11-1, which are sequentially alternately deposited on the amorphous carbon layer 5 , 11-2 constitute a multi-layer stack. The uppermost layer in the stack 6 is the silicon nitride layer 10-3. The thickness of each silicon nitride layer is 100-300A; the thickness of each silicon oxide layer is 100-300A. It should be noted that theoretically, the more alternating layers of silicon nitride layers and silicon oxide layers in the stack 6, the greater the blocking effect on ultraviolet light (the blocking mechanism will be described in detail later), but it is necessary to combine device design requirements. Therefore, as other optional embodiments of the present invention, the stack may consist of three or more silicon nitride layers and two or more silicon oxide layers to form a multi-layer stack; and the number of layers of silicon nitride layers and silicon oxide layers may be Likewise, the uppermost layer in the stack at this time will become the silicon oxide layer.

As shown in block 4, step 4: remove the stack in the NMOS region of the MOS device.

Referring to FIG. 6 , a photolithography process is used to coat the photoresist 7 on the entire MOS device 3 , that is, the stack 6 of the NMOS region 9 and the PMOS region 8 is covered over the entire MOS device 3 .

Please refer to FIG. 7 , through exposure and development, the photoresist 7 of the NMOS region 9 is removed (the photoresist 7 of the NMOS region 9 is shown in the removed state), so that the stack 6 of the NMOS region 9 is exposed, while the PMOS region Above 8 is still covered by photoresist 7 .

Referring to FIG. 8 , a dry etching process is used to remove the stack 6 of the NMOS region 9 by means of a fluorine-containing plasma gas (the state of the stack 6 of the NMOS region 9 being removed is shown in the figure).

As shown in block 5, step 5: performing ultraviolet light curing treatment on the high tensile stress silicon nitride layer.

Referring to FIG. 9, in the state of the device as shown in FIG. 9, ultraviolet light with a wavelength of 190-400 nm, such as ultraviolet light with a wavelength of 193 nm, is used to perform ultraviolet light curing treatment on the high tensile stress silicon nitride layer (in the figure The downward hollow arrow represents the irradiation direction of UV light).

The silicon nitride film formed by the plasma-enhanced chemical vapor deposition method contains a large amount of H (hydrogen atoms), and its structure is loose, so that the stress cannot meet the requirements, only about 0.7Gpa. Therefore, it is also necessary to perform UV cure (ultraviolet light curing) on the film, and use ultraviolet light to destroy the hydrogen bonds in the film, so that hydrogen atoms form hydrogen gas precipitation, and the remaining dangling bonds Si- and N- can form Si-N bonds. In this way, the spatial network structure of the silicon nitride film changes, so that a silicon nitride film with a stress limit of about 1.7 Gpa can be formed, which can significantly improve the performance of the NMOS.

Since the PMOS region 8 still retains the multi-layered layer 6 composed of alternating silicon nitride layers and silicon oxide layers during the UV curing process, the multi-layered layer 6 can pass through the air with different refractive indices,

The dielectric interface between the silicon nitride layer and the silicon oxide layer reflects the ultraviolet light, so that the light intensity of the ultraviolet light gradually reaches the high tensile stress silicon nitride layer 4 through the multilayer layer 6 and the amorphous carbon layer 5. attenuation. The number of repetitions of alternating deposition of silicon nitride and silicon oxide layers determines the intensity of UV light that eventually reaches the high tensile stress silicon nitride layer.

According to the principle of reflection of light, light is reflected at the interface of two media with different refractive indices. When the beam is near normal incidence (incidence angle is approximately equal to 90 degrees), the reflectance calculation formula is:

R=(n1-n2) ² /(n1+n2) ²

Among them, R represents the reflectivity, and n1 and n2 are the real refractive indices of the two media (ie, the refractive indices relative to vacuum).

Taking the above-mentioned stack of three silicon nitride layers 10-1, 10-2, 10-3 and two silicon oxide layers 11-1 and 11-2 as shown in FIG. 12 as an example, according to the existing data, Under the ultraviolet light of 193nm wavelength, the refractive index of silicon nitride film is about 2.7, silicon oxide is about 1.5, amorphous carbon film is about 1.5, and air is 1. Substituting the data into the above reflectance calculation formula, the transmittance of ultraviolet light in each layer (ie 1-reflectance) and the total transmittance of ultraviolet light when it reaches the high tensile stress silicon nitride layer 4 can be obtained, as shown in the following table :

It can be seen from the data in the table that the ultraviolet light that can finally pass through the amorphous carbon film is only about 50% of the initial incident light, so the light intensity of the ultraviolet light reaching the PMOS region 8 will be attenuated by nearly half. Therefore, after UV curing, the increase of the tensile stress of the high tensile stress silicon nitride layer 4 in the PMOS region will be significantly affected, and the ultimate tensile stress state of 1.7 Gpa cannot be reached. This relatively low tensile stress state significantly reduces the detrimental effect on the electrical performance of the PMOS device. For the high tensile stress silicon nitride layer in the NMOS region, since the multilayer stack consisting of alternating silicon nitride layers and silicon oxide layers has been removed, the UV curing process will not be affected. After the UV curing process, The high tensile stress silicon nitride layer in this region will be converted into a high tensile stress silicon nitride layer 4-1 (marked here with 4-1 to have a relatively lower tensile stress than the PMOS region) The tensile stress of the high tensile stress silicon nitride layer 4) can significantly improve the electron mobility in the NMOS device.

As shown in block 6, step 6: removing the stack of the PMOS region of the MOS device, and then removing the amorphous carbon layer to form silicon nitride with different high tensile stress on the MOS device Double contact hole etch stop layer.

Referring to FIG. 10 , first, a plasma oxidation process is used to remove the photoresist 7 in the PMOS region 8 of the MOS device by using an oxidizing gas such as oxygen plasma gas excited by oxygen (the photoresist 7 in the PMOS region 8 is shown in the figure has been removed) Then, using a dry etching process, the stack 6 of the PMOS region 8 is removed by etching with a fluorine-containing plasma gas (the illustration shows that the stack 6 of the PMOS region 8 has been removed).

Finally, please refer to FIG. 11 , a plasma oxidation process is used to remove all the amorphous carbon layer 5 (the state in which the amorphous carbon layer 5 has been removed is shown in the figure) by using an oxidizing gas such as oxygen plasma gas excited by oxygen, so that the MOS device is in a state of being removed. A high tensile stress silicon nitride layer 4-1 with relatively high tensile stress (up to a limit state of about 1.7 Gpa) and a relatively low tensile stress (apparently less than 1.7 GPa) are finally formed on the NMOS region 9 and PMOS region 8 of 3. ) of the high tensile stress silicon nitride layer 4 with different high tensile stress silicon nitride double contact hole etch stop layer.

To sum up, in the present invention, the high tensile stress silicon nitride layer in the PMOS and NMOS regions of the MOS device is subjected to high tensile stress by using the multilayer layer consisting of alternating silicon nitride layers and silicon oxide layers as the ultraviolet light blocking layer in the PMOS region of the MOS device. Selective UV curing treatment can obtain a high tensile stress silicon nitride layer with relatively low tensile stress on the PMOS region, and a high tensile stress silicon nitride layer with relatively high tensile stress on the NMOS region. , The NMOS region has silicon nitride double-contact etch stop layers with different high tensile stress, which can not only avoid the negative impact of the existing single-step high tensile stress silicon nitride deposition process on the hole mobility of PMOS devices, but also can Avoid the complexity of the two-step silicon nitride deposition to form the double-contact etch stop layer process. Moreover, the process method of the present invention is simpler and lower in cost than the traditional double-contact hole etching stop layer process, and ultimately improves the electrical performance of the device at a lower cost.

The above are only the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the patent protection of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and the accompanying drawings of the present invention shall also include within the protection scope of the present invention.

Claims (10)

1. A manufacturing method of a double-contact-hole etching stop layer is characterized by comprising the following steps:

the method comprises the following steps: providing an MOS device, and depositing a layer of high tensile stress silicon nitride layer on the MOS device to be used as a contact hole etching stop layer;

step two: depositing an amorphous carbon layer on the high-tensile-stress silicon nitride layer to serve as a protective layer of the high-tensile-stress silicon nitride layer;

step three: depositing silicon nitride layers and silicon oxide layers on the amorphous carbon layers in sequence and alternately to form a multilayer lamination consisting of the silicon nitride layers and the silicon oxide layers as an ultraviolet light blocking layer;

step four: removing the lamination of the NMOS area of the MOS device;

step five: carrying out ultraviolet curing treatment on the high-tensile-stress silicon nitride layer, and destroying hydrogen bonds in the high-tensile-stress silicon nitride layer by using ultraviolet light to enable hydrogen atoms to form hydrogen to be separated out and form Si-N bonds; the multi-layer laminated layer in the PMOS area reflects ultraviolet light through medium interfaces with different refractive indexes, so that the light intensity of the ultraviolet light is gradually attenuated in the process of reaching the high-tensile-stress silicon nitride layer below, and the ultraviolet light curing process of the high-tensile-stress silicon nitride layer in the NMOS area cannot be influenced because the multi-layer laminated layer is removed;

step six: and removing the laminated layer in the PMOS region of the MOS device, and then removing the amorphous carbon layer to form a silicon nitride double-contact-hole etching stop layer with different high tensile stress on the MOS device.

2. The method for forming a dual-contact etch stop layer as claimed in claim 1, wherein in step one, the high tensile stress silicon nitride layer is deposited to a thickness of 300-1000 angstroms.

3. The method for manufacturing a dual-contact etching stop layer as claimed in claim 1, wherein in the second step, the deposition thickness of the amorphous carbon layer is 1000-5000 angstroms.

4. The method of claim 1, wherein in step three, the number of silicon nitride layers in the stack is 3 or more, and the number of silicon oxide layers is 2 or more.

5. The method for forming a dual-contact etching stop layer as claimed in claim 1 or 4, wherein in step three, the uppermost layer of the stack is the silicon nitride layer.

6. The method for manufacturing a dual-contact etching stop layer as claimed in claim 1 or 4, wherein in the third step, the thickness of each silicon nitride layer is 100-300 angstroms.

7. The method for manufacturing a dual-contact etching stop layer as claimed in claim 1 or 4, wherein in the third step, the thickness of each silicon oxide layer is 100-300 angstroms.

8. The method for forming a dual-contact etch stop layer as claimed in claim 1, wherein in step four, a photolithography process is used to cover the PMOS region of the MOS device with photoresist, and then a dry etching process is used to remove the stack layer in the NMOS region of the MOS device.

9. The method for manufacturing the double-contact hole etching stop layer as claimed in claim 1, wherein in the fifth step, ultraviolet light with wavelength of 190-400 nm is adopted to carry out ultraviolet light curing treatment on the high-tensile stress silicon nitride layer.

10. The method of claim 8, wherein in step six, the photoresist in the PMOS region of the MOS device is removed by a plasma oxidation process, the stack layer in the PMOS region of the MOS device is removed by a dry etching process, and the amorphous carbon layer is removed by a plasma oxidation process.

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