CN104199758B - A kind of method for designing being easy to mainboard VR Debug test - Google Patents

Abstract

The present invention provides a kind of method for designing being easy to mainboard VR Debug test, belongs to server for electrical domain, and the present invention, in the EVT stage of mainboard, will often organize series connection sense resistance on VR input current path, and reserve GAP on output end current path.When mainboard Debug, only need to being linked up by GAP scolding tin and can realize energising, it is ensured that mainboard VR is when debug, and VR confirms one by one, the function being finally completed all VR confirms, it is prevented that during Debug, because certain group VR exists design problem, causes the risk that circuit burns out.

Description

A design method for VR Debug testing of motherboards

technical field

The invention relates to the field of server power supply, relates to a design method for VRDebug testing of the mainboard, and improves the accuracy and debugging efficiency of the VRDebug testing of the mainboard.

Background technique

On the mainboard of the current server, functional modules such as CPU, memory, south bridge unit, network unit, BMC unit, and SAS controller are included. In the motherboard system, these functional units form an organic whole through the power supply network, signal lines, data lines, and control lines. Each functional unit needs a corresponding power supply voltage to maintain its normal and stable operation. Correct and stable power supply is the prerequisite to ensure the stable operation of each functional unit of the motherboard. However, the VRs on the actual motherboard are generally related to each other.

For example: the P3V3_STBY required by the BMC unit on the motherboard is transferred from the P5V_STBY of the PSU, and the 1.1V standby power supply voltage required by the south bridge chip is transferred from the P3V3_STBY. When carrying out load measurement for VR:P3V3_STBY on the motherboard (for example, pulling a load current of 3A, at this time, BMC is also eating P3V3_STBY), the actual loading current for VR:P3V3_STBY=3A+the current consumed by BMC. This will cause a deviation in the actual measurement of VR. Therefore, at the beginning of the motherboard VR design, the convenience and accuracy of VR testing need to be taken into consideration to improve the efficiency and accuracy of VR testing.

Contents of the invention

In order to ensure the accuracy of VR design and improve the efficiency of VR testing, this paper proposes a design method for VRDebug testing of the motherboard.

The invention proposes a design method for VRDebug testing of the main board. The main idea is: by connecting the sense resistor in series on the input current path of VR, and reserving a gap on the output current path (that is, cutting off the current path on the PCB, exposing the copper foil at both ends of the cut-off current path), to Improve the accuracy and Debug efficiency of the motherboard VRDebug test.

On the current path of the VR input terminal, the sense resistor can be connected in series, and the voltage at both ends of the sense resistor can be measured to determine the input current of the VR, which is convenient for measuring the conversion efficiency of VR and improving the accuracy of efficiency measurement; on the current path of the VR output terminal , GAP is reserved to ensure that it is not affected by the next-level VR during the VR load test (that is, the output of the VR is used as the input of the next-level VR), and the accuracy of the VR load test is improved.

When debugging the main board, you only need to connect the GAPs with solder to realize power-on, to ensure that the VR on the main board is confirmed one by one when debugging, and finally complete the function confirmation of all VRs, so as to prevent the design problems of a certain group of VRs during debugging. Risk of wire burnout.

1) When measuring VR conversion efficiency:

Weld the load line on the left side of the GAP, and use the electronic load to pull the current Io. The corresponding input current can be measured by a precision multimeter. The voltage across the sense resistor (resistance: Rsense): Vsense; then, VR input current:

Isense=Vsense/Rsense

It can conveniently and accurately measure the conversion efficiency of VR under the load condition.

2) When measuring VR under full load, medium load, or light load conditions, the voltage ripple:

Weld the load line on the left side of the GAP, use the electronic load to pull the current Io, connect the oscilloscope signal probe near the GAP copper foil, and then accurately measure the ripple of the voltage under the condition that the load current is Io.

At the same time, when debugging the main board, only need to connect the GAP with solder to realize power supply. Ensure that the motherboard VR is confirmed one by one when debugging, and finally complete the functional confirmation of all VRs to prevent the risk of circuit burnout during debugging.

It is the layout of each functional unit VR on a common server motherboard. During the debug process of the motherboard EVT, at the beginning of the design, connect the sense resistor in series with the input end of each group of VR, and reserve a gap on the VR output current path. According to the power-on sequence of the main board, debug the VRs on the main board one by one. For each group of VRs, connect the GAPs of the output terminals of the group of VRs with solder, and then debug the next level of VR until all the VRs on the main board are completed. Debug, to achieve boot.

Description of drawings

Figure 1 is a schematic diagram of the current path of a single set of VR.

FIG. 2 is a general diagram of the layout of functional units VR on a mainboard of a server.

detailed description

The present invention will be further described below according to accompanying drawing.

In Figure 1, a sense resistor is connected in series with the current path of the input terminal, and after being converted by VR, the output voltage is reserved for the GAP on the output current path (marked by the box on the right of Figure 1).

As shown in FIG. 2 , it shows the layout of each functional unit VR on a common server motherboard. During the debug process of the motherboard EVT, at the beginning of the design, connect the sense resistor in series with the input end of each group of VR, and reserve a gap on the VR output current path. According to the power-on sequence of the main board, debug the VRs on the main board one by one. For each group of VRs, connect the GAPs of the output terminals of the group of VRs with solder, and then debug the next level of VR until all the VRs on the main board are completed. Debug, to achieve boot.

In order to clearly illustrate the implementation of the design method, the following are the implementation and application steps of the design method in this paper. details as follows:

1) When designing the VR circuit of the motherboard, select the appropriate sense resistor in the peripheral VR (the voltage conversion circuit on the motherboard except the CPU and memory VR) according to the input current of different VR designs. The sense resistor is generally selected at 5mohm. The rated current of the resistor must be greater than the input current designed by VR;

2) In the output current path of VR (the copper foil between the output capacitor of the VR line and the power consumption terminal), reserve a GAP. When designing the pcb, the copper foil width of the GAP is calculated according to the thickness of 1oz copper foil and 40mil/a Sure;

3) In the EVTDebug test phase of the main board, according to the power-on sequence of the main board, connect the GAP of the output end of the VR with solder, and debug one by one after powering on until the power is turned on;

4) In the PVT stage of the motherboard, the sense resistor and GAP can be removed, and copper foil can be directly laid on the input sense resistor position and the output GAP position.

According to the above steps, by adopting the design method proposed in this paper, the test accuracy of the motherboard VR can be improved and the debugging progress can be accelerated.

Glossary:

VR: VoltageRegulation, that is, a voltage conversion circuit, which converts one voltage into another DC voltage.

Claims (1)

1. the method for designing being easy to mainboard VRDebug test, it is characterised in that

In the EVT stage of mainboard, will often organize series connection sense resistance on VR input current path, and output end current path reserve GAP and cuts off by current path on PCB, expose Copper Foil at the current path two ends cut off；When mainboard Debug, only need to being linked up by GAP scolding tin and can realize energising, it is ensured that mainboard VR is when debug, and VR confirms one by one, the function being finally completed all VR confirms；

On the current path of VR input, sense resistance of connecting, it is possible to the voltage measuring sense resistance two ends determines the input current of VR；On the current path of VR outfan, reserved GAP, it is ensured that when VR draws load test, not by the impact of next stage VR；

Concretely comprise the following steps:

1), when the VR circuit of mainboard designs, selecting suitable sense resistance at peripheral VR according to the input current of different VR designs, sense resistance is generally selected in the rated current of 5mohm, sense resistance more than the VR input current designed；

2), at the output current path of VR, during reserved GAP, pcb design, the Copper Foil width of GAP is according to 1oz copper thickness, and 40mil/a calculates and determines；

3), at mainboard EVTDebug test phase, according to mainboard electrifying timing sequence, being connected by the GAP scolding tin of the outfan of VR, energising is debugged one by one, until start；

4), in the mainboard PVT stage, can sense resistance and GAP being taken away, Copper Foil is directly laid in input sense resistance position and output GAP position.