CN104184441A - Clock data recovery circuit - Google Patents

Abstract

A clock data recovery circuit achieves the function of clock data recovery through a phase locked loop or a delay locked loop. And the clock data recovery circuit includes a control voltage adjustment module. The control voltage adjustment module is coupled to the clock frame selection module in the phase locked loop or the delay locked loop to adjust the control voltage within a preset voltage range. . Through the clock data recovery circuit disclosed in the present invention, the control voltage adjustment module is used to determine whether the control voltage used to control the delay time or oscillation frequency is lower than the lower limit of the preset voltage range, thereby avoiding the occurrence of a "lock-up" state.

Description

Clock Data Recovery Circuit

technical field

The invention relates to a clock data recovery circuit, in particular to a clock data recovery circuit with an anti-lock mechanism.

Background technique

Clock and Data Recovery circuit (CDR) is widely used in various data transmission related devices. In the clock data recovery circuit, the function of clock data recovery is often achieved through a phase-locked loop (Phase-Locked Loop, PLL) or a delay-locked loop (Delay-Locked Loop, DLL). However, both the phase-locked loop and the delay-locked loop may be in a "locked" state in operation, which will lead to a stoppage or error of the entire clock data recovery circuit and even the entire data transmission device. Therefore, how to avoid the "locked" state is an urgent problem to be solved.

Contents of the invention

In view of the above problems, the present invention proposes a clock data recovery circuit. When it is judged that the loop in it is locked, the entire clock data recovery circuit is reset to try to make the loop in it lock normally.

A clock data recovery circuit disclosed in one or more embodiments of the present invention includes a clock delay module, a phase detection module, a clock frame selection module and a control voltage adjustment module. The clock delay module is used for receiving the reference clock and delaying for a delay time to generate the first clock. The phase detection module is coupled to the clock delay module for comparing the phase difference between the reference clock and the first clock. The clock frame selection module is coupled to the phase detection module and the clock delay module, and generates a control voltage according to the phase difference, and the control voltage is used to control the aforementioned delay time. The control voltage adjustment module is coupled to the clock frame selection module and the clock delay module for adjusting the control voltage within a preset voltage range. In an embodiment of the present invention, when the control voltage is lower than the lower limit of the preset voltage range, the control voltage adjustment module at least increases the control voltage to the upper limit of the preset voltage range. In another embodiment of the present invention, when the control voltage is greater than the upper limit of the preset voltage range, the control voltage adjustment module at least reduces the control voltage to the lower limit of the preset voltage range.

Another clock data recovery circuit disclosed according to one or more embodiments of the present invention includes an oscillation module, a phase frequency detection module, a clock frame selection module and a control voltage adjustment module. The oscillation module is controlled by the control voltage to generate the second clock. The phase frequency detection module is coupled to the oscillation module and is used for comparing the phase difference and the frequency difference between a reference clock and a second clock. The clock frame selection module is coupled to the phase frequency detection module and the oscillation module, and generates the aforementioned control voltage according to the phase difference and the frequency difference. The control voltage adjustment module is coupled to the clock frame selection module and the oscillation module for adjusting the control voltage within a preset voltage range. Wherein when the control voltage is lower than the lower limit of the preset voltage range, the control voltage adjustment module increases the control voltage to the upper limit of the preset voltage range.

Through the clock data recovery circuit disclosed in the present invention, the control voltage adjustment module is used to judge whether the control voltage used to control the delay time or the oscillation frequency is lower than the lower limit of the preset voltage range. And when the control voltage is lower than the lower limit of the preset voltage range, the control voltage is increased to the upper limit of the preset voltage range, thereby trying to make the loop achieve locking again. In this way, a "locked" state can be avoided.

The above descriptions about the content of the present invention and the following descriptions of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide further explanations of the scope of the claims of the present invention.

Description of drawings

FIG. 1 is a functional block diagram of a clock data recovery circuit according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a clock delay module according to an embodiment of the invention.

FIG. 3 is a schematic circuit diagram of a control voltage adjustment module according to an embodiment of the invention.

FIG. 4 is a functional block diagram of a clock data recovery circuit according to an embodiment of the invention.

FIG. 5 is a timing diagram of signals in the clock data recovery circuit according to an embodiment of the invention.

1, 4 Clock data recovery circuit

11 Clock delay module

13 Phase detection module

15, 45 Clock frame selection module

17, 47 Control voltage adjustment module

171 switch unit

173, 175 Comparators

177 latch

178, 179, 182 Inverter

180, 181 NAND gate

183 Transistors

185 Temperature Compensation Unit

41 Oscillator module

43 Phase frequency detection module

G _ND ground terminal

LOCK lock signal

R ₁₇ resistor

T ₁ first time point

T ₂ second time point

T3 The third time point

V _ctrl control voltage

V _DD high voltage terminal

V _REFH first reference voltage

V _REFL second reference voltage

V _XLOCK lock indication signal

V _LOCK lock indication signal

Q output terminal

S, R input terminal

mode1, mode2 mode signal

Detailed ways

The detailed features and advantages of the present invention are described in detail below in the embodiments, the content of which is sufficient for any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and according to the contents disclosed in this specification, claims and accompanying drawings, The related objects and advantages of the present invention can be easily understood by anyone skilled in the art. The following examples further illustrate the concept of the present invention in detail, but do not limit the scope of the present invention in any way.

Regarding a clock-data recovery circuit (clock-data recovery circuit, DCR) disclosed according to an embodiment of the present invention, please refer to FIG. 1 , which is a functional block diagram of a clock-data recovery circuit according to an embodiment of the present invention. As shown in FIG. 1 , the clock data recovery circuit 1 may include a clock delay module 11 , a phase detection module 13 , a clock frame selection module 15 and a control voltage adjustment module 17 . The phase detection module 13 is coupled to the clock delay module 11, the clock frame selection module 15 is coupled to the phase detection module 13 and the clock delay module 11, and the control voltage adjustment module 17 is coupled to the clock frame selection module 15 and the clock frame selection module 15. Pulse delay module 11.

The clock delay module 11 is used for receiving a reference clock and delaying for a delay time to generate a first clock. For implementation, please refer to FIG. 2 , which is a schematic circuit diagram of a clock delay module according to an embodiment of the present invention. As shown in FIG. 2 , the clock delay module 11 may include three series-connected voltage control delay cells (voltage control delay cells) 111 to 115 . Taking the voltage-controlled delay unit 111 as an example, the propagation delay of the voltage-controlled delay unit 111 can vary between 0.1 nano-second and 0.5 nano-second according to a control voltage. Therefore, the clock delay module 11 can be controlled by the control voltage to provide a delay time of 0.3 nanoseconds to 1.5 nanoseconds. That is to say, the clock delay module 11 is controlled by the control voltage to provide a delay time of 1.0 nanoseconds, the clock delay module 11 generates the first clock after receiving the reference clock, and sends the first clock after 1.0 nanoseconds pulse.

The phase detection module 13 is used for comparing the reference clock and the first clock to obtain the phase difference between the reference clock and the first clock. In an implementation manner, the phase detection module 13 may include an exclusive-or gate (exclusive-or gate), and two input terminals of the exclusive-or gate are respectively used to receive the reference clock and the first clock. When the logic level of the reference clock is different from the logic level of the first clock, the logic level of the output signal of the XOR gate is high, and when the logic level of the reference clock is different from that of the first clock When the logic potentials are the same, the logic potential of the output signal of the XOR gate is low. Thus, the phase difference between the first clock and the reference clock can be judged and calculated according to the length of the time interval in which the logic level of the output signal is high.

The clock frame selection module 15 generates a control voltage according to the phase difference, and the control voltage is transmitted to the clock delay module 11 through a voltage node coupled to the clock delay module 11 to control the delay time of the clock delay module 11 . In one embodiment, the clock frame selection module 15 may include a charge pump and a loop filter. The charge pump is electrically connected to the phase detection module 13 to determine the length of time for injecting or extracting charge (current) to the loop filter according to the phase difference, and the loop filter accordingly adjusts one of the voltage nodes to be transmitted to the clock The control voltage of the delay module 11.

The control voltage adjustment module 17 is used to adjust the control voltage within a preset voltage range. In one embodiment, when the control voltage is lower than the lower limit of the preset voltage range, the control voltage adjustment module at least increases the control voltage to the upper limit of the preset voltage range. Specifically, in this embodiment, the control voltage adjustment module 17 couples the voltage node used to transmit the control voltage to the clock delay module 11 in the clock frame selection module 15 to a high voltage terminal to control The voltage is boosted to the upper limit of the preset voltage range. In another embodiment, when the control voltage is greater than the upper limit of the preset voltage range, the control voltage adjustment module at least reduces the control voltage to the lower limit of the preset voltage range. Specifically, in this embodiment, the control voltage adjustment module 17 couples the voltage node used to transmit the control voltage to the clock delay module 11 in the clock frame selection module 15 to a low voltage terminal to control The voltage is boosted to the upper limit of the preset voltage range.

In the following, the control voltage adjustment module 17 couples the voltage node used to transmit the control voltage to the clock delay module 11 in the clock frame selection module 15 to a high voltage terminal to increase the control voltage to a preset voltage range. An example of a cap is given to illustrate how it works. Specifically, please refer to FIG. 3 , which is a schematic circuit diagram of a control voltage adjustment module according to an embodiment of the present invention. As shown in FIG. 3 , the control voltage adjustment module 17 may include a switch unit 171 , a comparator 173 , a comparator 175 and a latch 177 . The first terminal 171a of the switch unit 171 is coupled to the high voltage terminal V _DD , and the second terminal 171b of the switch unit 171 is coupled to the aforementioned voltage node for selectively establishing a power path between the control voltage V _ctrl and the high voltage terminal. , so that the control voltage V _ctrl is pulled high. The negative input terminal of the comparator 173 is connected to the aforementioned voltage node, and the positive input terminal of the comparator 173 is connected to a voltage source to receive the first reference voltage V _REFH . The positive input terminal of the comparator 175 is connected to the aforementioned voltage node, and the negative input terminal of the comparator 175 is connected to a voltage source to receive the second reference voltage V _REFL .

The comparator 173 is used to compare the first reference voltage V _REFH with the control voltage V _ctrl . The comparator 175 is used to compare the second reference voltage V _REFL with the control voltage V _ctrl . Thus, two comparison results can be obtained from the comparator 173 and the comparator 175. From these two comparison results, it can be known whether the voltage value of the control voltage V _ctrl is between the voltage value of the first reference voltage V _REFH and the second reference voltage. voltage between the voltage values of V _REFL . That is, if the voltage value of the first reference voltage V _REFH is greater than the voltage value of the second reference voltage V _REFL , the upper limit of the preset voltage range may be the first reference voltage V _REFH and the lower limit may be the second reference voltage voltage V _REFL . More specifically, when the control voltage V _ctrl is greater than the first reference voltage V _REFH , the logic potential of the output voltage of the comparator 173 is a low voltage, and at the same time, because the control voltage V _ctrl is greater than the second reference voltage V _REFL , the comparator 175 The output voltage logic potential is a high voltage. When the control voltage V _ctrl is between the first reference voltage V _REFH and the second reference voltage V _REFL , the logic potential of the output voltage of the comparator 173 is a high voltage, and the logic potential of the output voltage of the comparator 175 is a high voltage. When the control voltage V _ctrl is less than the second reference voltage V _REFL , the logic potential of the output voltage of the comparator 173 is a high voltage, and the logic potential of the output voltage of the comparator 175 is a low voltage. Therefore, it can be determined whether the control voltage V _ctrl is between the two reference voltages according to the logic potentials of the voltages output by the two comparators.

The input terminal S of the latch (Latch) 177 receives the comparison result of the aforementioned comparator 173, and the input terminal R of the latch 177 receives the comparison result of the aforementioned comparator 175, that is, the logic potentials of the output voltages of the two comparators, And the output terminal Q of the latch 177 is coupled to the control terminal 171c of the switch unit 171 . Thus, the latch 177 selectively controls whether the switch unit 177 is turned on or not according to the comparison result of the aforementioned comparator 173 and the comparison result of the comparator 175 . In a specific embodiment, please refer to FIG. 3 and Table 1 below together, wherein Table 1 is a truth table of input and output of a latch according to an embodiment of the present invention.

S R Q _n+1 0 0 undefined (cannot happen) 0 1 0 1 1 Q _n 1 0 1

Table I

Through the truth table as Table 1, as shown in Figure 3, the input terminal S of the latch 177 is coupled to the output terminal of the comparator 173, and the input terminal R of the latch 177 is coupled to the output of the comparator 175 terminal, the output terminal Q of the latch 177 can also be coupled to the input terminal of an inverter (inverter) 178 , and the output terminal of the inverter 178 can be coupled to the control terminal 171c of the switch unit 171 . If the switch unit 171 _is a P-type metal oxide field effect transistor as shown in _FIG . , so the switch unit 171 is turned on to form a power path between the high voltage terminal V _DD and the voltage node, thereby pulling the voltage value of the control voltage V _ctrl close to the voltage value of the high voltage terminal V _DD . Next, when the voltage value of the control voltage V _ctrl is pulled up to slightly higher than the voltage value of the first reference voltage V _REFH , as shown in Table 1 above, it can be known that the voltage potential of the output terminal Q of the latch 177 will be a low voltage, thereby The logic potential of the output terminal of the inverter 178 will be a high voltage. Therefore, the switch unit 171 will be cut-off, so the power path from the high voltage terminal V _DD to the aforementioned voltage node is interrupted, and the voltage value of the control voltage V _ctrl on the aforementioned voltage node is thus maintained at slightly higher than the first voltage node. A voltage value of the reference voltage V _REFH , so that the entire clock data recovery circuit 1 is reset. Afterwards, when the phase detection module 13 and the clock frame selection module 15 start to adjust the control voltage V _ctrl again according to the reference clock and the first clock, the voltage value of the control voltage V _ctrl will be pulled down, and between the first reference clock between the voltage V _REFH and the second reference voltage V _REFL , according to the truth table in Table 1, since the voltage potential of the output terminal Q of the latch 177 will continue the previous voltage potential, the output of the inverter 178 The voltage potential at the terminal will remain at a high voltage, and therefore the switch unit 171 will not be turned on within this "normal locking range". In another embodiment, the output terminal Q′ (not shown) of the latch 177 can also be directly used to control the aforementioned switch unit 171 .

In an embodiment of the present invention, the control voltage adjustment module 17 may further include an inverter 179 coupled to the output terminal of the inverter 178, a NAND gate 180, a NAND gate 181, an inverter 182, a transistor 183 and a resistor R ₁₇ . One input terminal of the NAND gate 180 is coupled to the output terminal of the inverter 179 to receive the lock indication signal V _LOCK , and the other input terminal is coupled to a mode signal mode1. One input terminal of the NAND gate 181 is coupled to the output terminal of the NAND gate 180 , and the other input terminal is coupled to a mode signal mode2 . The input terminal of the inverter 182 is coupled to the output terminal of the NAND gate 181 , and the output terminal of the inverter 182 is coupled to the control terminal of the transistor 183 . One terminal of the transistor 183 is coupled to the ground terminal G _ND , and the resistor R ₁₇ is coupled between the other terminal of the transistor 183 and the high voltage terminal V _DD , thereby outputting the lock signal LOCK. When the clock data recovery circuit 1 is locked, the lock signal LOCK can be adjusted according to the lock indication signal V _LOCK , the mode signal mode1 and the mode signal mode2, so as to request an external device to send a reference clock that is easier to lock.

In yet another embodiment of the present invention, as shown in FIG. 3 , the control voltage adjustment module 17 may further include a temperature compensation unit 185 for providing the first reference voltage V _REFH and the second reference voltage V _REFL . More specifically, in this embodiment, the first reference voltage V _REFH and the second reference voltage V _REFL are not fixed values, but will change with temperature. In one implementation, the temperature compensation unit 185 is a bandgap reference circuit (bandgap reference), and the relationship between the output voltage and temperature can be a linear curve or a quadratic curve. In another implementation, the temperature compensation unit 185 may include a temperature sensing element, a control circuit, a digital-to-analog converter, and a storage element. The temperature sensing element, the storage element and the digital-to-analog converter are all electrically connected to the control circuit. The temperature sensing element is used for sensing the temperature of the environment where the clock data recovery circuit is located. A comparison table of the relationship between the first reference voltage V _REFH and the temperature and a comparison table of the relationship between the second reference voltage V _REFL and the temperature may be stored in the storage element. The two comparison tables can be designed and stored in advance by the designer of the clock data recovery circuit according to the actual measurement results.

After the control circuit receives the temperature sensed by the temperature sensing element, it finds the corresponding voltage value of the first reference voltage V _REFH and the voltage value of the second reference voltage V _REFL from the storage element, and then the control circuit controls the digital The analog converter outputs a first reference voltage V _REFH and a second reference voltage V _REFL . In this embodiment, since the first reference voltage V _REFH and the second reference voltage V _REFL will change with temperature, the preset voltage range will also change with temperature. In such a clock data recovery circuit, in a high temperature or low temperature environment, the preset voltage range will be correspondingly changed, so as to be more suitable for a high temperature environment or a low temperature environment.

For another clock data recovery circuit disclosed according to an embodiment of the present invention, please refer to FIG. 4 , which is a functional block diagram of a clock data recovery circuit according to an embodiment of the present invention. As shown in FIG. 4 , the clock data recovery circuit 4 may include an oscillation module 41 , a phase frequency detection module 43 , a clock frame selection module 45 and a control voltage adjustment module 47 . The phase frequency detection module 43 is coupled to the oscillation module 41 , the clock frame selection module 45 is coupled to the phase frequency detection module 43 and the oscillation module 41 , and the control voltage adjustment module 47 is coupled to the clock frame selection module 45 and the oscillation module 41 .

The oscillation module 41 is controlled by the control voltage to generate the second clock. Specifically, the oscillation module 41 may be a voltage-controlled oscillator (voltage control oscillator, VCO). The technical details about the voltage-controlled oscillator (VCO) are omitted here.

The phase frequency detection module 43 is used for comparing the phase difference and the frequency difference between a reference clock and a second clock. In a general practice, a frequency divider (frequency divider) may also be coupled between the output terminal of the oscillation module 41 and the phase frequency detection module 43 to divide the frequency of the second clock, and the phase frequency detection module 43 compares The implementation method of the phase difference and frequency difference between the frequency-divided clock and the reference clock is roughly similar to that of the aforementioned phase detection module 13 , and will not be repeated here.

The clock frame selection module 45 generates the aforementioned control voltage according to the phase difference and the frequency difference. The control voltage adjustment module 47 is used for adjusting the control voltage within a preset voltage range. Wherein when the control voltage is lower than the lower limit of the preset voltage range, the control voltage adjustment module increases the control voltage to the upper limit of the preset voltage range. The implementation methods are respectively similar to the aforementioned clock frame selection module 15 and the aforementioned control voltage adjustment module 17 , so details are not repeated here.

Next, please refer to FIG. 1 , FIG. 3 and FIG. 5 to illustrate the effect of the present invention. FIG. 5 is a timing diagram of signals in a clock data recovery circuit according to an embodiment of the present invention. As shown in FIG. 5, at the first time point _T1 , because the reference clock CLKREF and the first clock CLK1 are disturbed in the system, the phase detection module 13 cannot detect the normal phase difference, thus causing the control voltage The voltage value of V _ctrl drops abnormally from the first time point, and finally at the second time point T ₂ , the voltage value of the control voltage V _ctrl − drops below the voltage value of the second reference voltage V _REFL . Therefore, starting from the second time point _T2 , the output signal of the output terminal Q of the latch 177 in the control voltage adjustment module 17, that is, the logic potential of the "lockout indication signal V _XLOCK " becomes a high voltage, indicating that this At this time, the entire clock data recovery circuit 1 is locked. Therefore, the switch unit 171 in the control voltage adjustment module 17 is turned on, and a power path is formed between the voltage node used to be coupled to the clock delay module 11 in the clock frame selection module 15 and the high voltage terminal V _DD , so It can be seen from FIG. 5 that the voltage value of the control voltage V _ctrl starts to rise from around the second time point T ₂ . At the third time point T3, the voltage value of the control voltage V _ctrl is just greater than the voltage value of the first reference voltage V _REFH , at this time, the logic potential of the lock indication signal V _XLOCK becomes a low voltage, so the switch unit 171 is turned off. , so that the power path from the high voltage terminal V _DD to the voltage node where the control voltage V _ctrl is located is interrupted, that is, the control voltage adjustment module 17 stops "resetting" the control voltage V _ctrl , and the phase detection module 13 and the time The pulse frame selection module 15 re-attempts to adjust the control voltage V _ctrl so that the entire clock data recovery circuit 1 is re-locked.

Through the clock data recovery circuit disclosed in the present invention, the control voltage adjustment module is used to judge whether the control voltage used to control the delay time or the oscillation frequency is lower than the lower limit of the preset voltage range. And when the control voltage is lower than the lower limit of the preset voltage range, the control voltage is increased to the upper limit of the preset voltage range, thereby trying to make the loop achieve locking again.

Although the present invention is disclosed above with the foregoing embodiments, they are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all changes and modifications made belong to the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the appended claims.

Claims (18)

1. a clock-data recovery circuit, comprising:

One clock pulse Postponement module, in order to receive one with reference to clock pulse and to postpone after the time of delay, produces one first clock pulse;

One phase detecting module, couples this clock pulse Postponement module, in order to relatively this with reference to the phase difference between clock pulse and this first clock pulse;

One clock pulse frame modeling piece, couples this phase detecting module and this clock pulse Postponement module, and according to this phase difference, to produce a control voltage, this control voltage is in order to control this time of delay; And

One controls voltage regulator module, couples this clock pulse frame modeling piece and this clock pulse Postponement module, in order to adjust this control voltage in a predeterminated voltage scope.

2. clock-data recovery circuit as claimed in claim 1, wherein between this clock pulse Postponement module and this clock pulse frame modeling piece, definition has a voltage node, this clock pulse frame modeling piece transmits this control voltage to this clock pulse Postponement module through this voltage node, and this control voltage regulator module couples this voltage node.

3. clock-data recovery circuit as claimed in claim 2, wherein this control voltage regulator module is optionally coupled to this voltage node one high voltage end points.

4. clock-data recovery circuit as claimed in claim 3, wherein this control voltage regulator module comprises:

One switch element, has a control end, a first end and one second end, and this first end is coupled to this high voltage end points, and this second end couples this voltage node;

One first comparator, in order to receive and to compare one first reference voltage and this control voltage;

One second comparator, in order to receive and to compare one second reference voltage and this control voltage; And

One latch, couples this control end, this first comparator and this second comparator, receives respectively the comparative result of this first comparator and this second comparator, according to this this switch element of conducting optionally;

Wherein this predeterminated voltage scope on be limited to this first reference voltage, under this predeterminated voltage scope, be limited to this second reference voltage.

5. clock-data recovery circuit as claimed in claim 4, wherein when this control voltage is less than this first reference voltage and this second reference voltage, this this switch element of latch conducting.

6. clock-data recovery circuit as claimed in claim 4, wherein, when this control voltage is greater than this first reference voltage and this second reference voltage, this latch ends this switch element.

7. clock-data recovery circuit as claimed in claim 4, wherein this control voltage regulator module also comprises a temperature compensation unit, this temperature compensation unit is electrically coupled to this first comparator and this second comparator, this temperature compensation unit, in order to according to an ambient temperature, is adjusted this first reference voltage and this second reference voltage.

8. clock-data recovery circuit as claimed in claim 1, wherein prescribes a time limit when this control voltage is less than the lower of this predeterminated voltage scope, and this control voltage regulator module at least promotes this control voltage to the upper limit of this predeterminated voltage scope.

9. clock-data recovery circuit as claimed in claim 1, wherein prescribes a time limit when this control voltage is greater than the upper of this predeterminated voltage scope, and this control voltage regulator module at least reduces this control voltage to the lower limit of this predeterminated voltage scope.

10. a clock-data recovery circuit, comprising:

One oscillation module, is controlled by a control voltage, to produce one second clock pulse;

One phase frequency detection module, couples this oscillation module, in order to compare one with reference to a phase difference and a difference on the frequency between clock pulse and this second clock pulse;

One clock pulse frame modeling piece, couples this phase frequency detection module and this oscillation module, according to this phase difference and this difference on the frequency to produce this control voltage; And

One controls voltage regulator module, couples this clock pulse frame modeling piece and this oscillation module, in order to adjust this control voltage in a predeterminated voltage scope.

11. clock-data recovery circuit as claimed in claim 10, wherein between this oscillation module and this clock pulse frame modeling piece, definition has a voltage node, this clock pulse frame modeling piece transmits this control voltage to this oscillation module through this voltage node, and this control voltage regulator module couples this voltage node.

12. clock-data recovery circuit as claimed in claim 11, wherein this control voltage regulator module is optionally coupled to this voltage node one high voltage end points.

13. clock-data recovery circuit as claimed in claim 12, wherein this control voltage regulator module comprises:

One switch element, has a control end, a first end and one second end, and this first end is coupled to this high voltage end points, and this second end couples this voltage node;

One first comparator, in order to receive and to compare one first reference voltage and this control voltage;

One second comparator, in order to receive and to compare one second reference voltage and this control voltage; And

One latch, couples this control end, this first comparator and this second comparator, receives respectively the comparative result of this first comparator and this second comparator, according to this this switch element of conducting optionally;

Wherein this predeterminated voltage scope on be limited to this first reference voltage, under this predeterminated voltage scope, be limited to this second reference voltage.

14. clock-data recovery circuit as claimed in claim 13, wherein when this control voltage is less than this first reference voltage and this second reference voltage, this this switch element of latch conducting.

15. clock-data recovery circuit as claimed in claim 13, wherein, when this control voltage is greater than this first reference voltage and this second reference voltage, this latch ends this switch element.

16. clock-data recovery circuit as claimed in claim 13, wherein this control voltage regulator module also comprises a temperature compensation unit, this temperature compensation unit is electrically coupled to this first comparator and this second comparator, this temperature compensation unit, in order to according to an ambient temperature, is adjusted this first reference voltage and this second reference voltage.

17. clock-data recovery circuit as claimed in claim 10, wherein prescribe a time limit when this control voltage is less than the lower of this predeterminated voltage scope, and this control voltage regulator module at least promotes this control voltage to the upper limit of this predeterminated voltage scope.

18. clock-data recovery circuit as claimed in claim 10, wherein prescribe a time limit when this control voltage is greater than the upper of this predeterminated voltage scope, and this control voltage regulator module at least reduces this control voltage to the lower limit of this predeterminated voltage scope.