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CN104183653B - junction barrier Schottky diode - Google Patents

junction barrier Schottky diode Download PDF

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Publication number
CN104183653B
CN104183653B CN201410274278.8A CN201410274278A CN104183653B CN 104183653 B CN104183653 B CN 104183653B CN 201410274278 A CN201410274278 A CN 201410274278A CN 104183653 B CN104183653 B CN 104183653B
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doped region
type doped
type
schottky diode
junction barrier
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CN104183653A (en
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洪崇佑
杨清尧
高字成
黄宗义
翁武得
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Richtek Technology Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

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Abstract

一种接面位障萧特基二极管,包含:硅基板,具有上表面,下方具有N型埋层,上表面以及N型埋层之间为N型井;第一P型掺杂区,设置于N型井之中,并由上表面向下延伸;一金属层,覆盖于上表面,并位于第一P型掺杂区的一侧的上方;第二P型掺杂区,设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区的另一侧;以及第一N型掺杂区,设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区的另一侧。

A junction barrier Schottky diode comprises: a silicon substrate having an upper surface, an N-type buried layer below, an N-type well between the upper surface and the N-type buried layer; a first P-type doped region arranged in the N-type well and extending downward from the upper surface; a metal layer covering the upper surface and located above one side of the first P-type doped region; a second P-type doped region arranged in the N-type well, extending downward from the upper surface and located on the other side of the first P-type doped region; and a first N-type doped region arranged in the N-type well, extending downward from the upper surface and located on the other side of the first P-type doped region.

Description

接面位障萧特基二极管Junction barrier Schottky diode

【技术领域】【Technical field】

本发明是关于一种接面位障萧特基二极管(Junction Barrier Schottky Diode,JBS Diode),特别是一种具有较佳的静电放电(Electrostatic Discharge)效果的接面位障萧特基二极管。The present invention relates to a Junction Barrier Schottky Diode (JBS Diode), in particular to a Junction Barrier Schottky Diode with better electrostatic discharge (Electrostatic Discharge) effect.

【背景技术】【Background technique】

图1为一般习用接面位障萧特基二极管100的剖面结构图。接面位障萧特基二极管100包括硅基板110、场氧化层(field oxide)120、场氧化层130、多个P型掺杂区140、金属层150、以及N型掺杂区160。FIG. 1 is a cross-sectional structure diagram of a conventional junction barrier Schottky diode 100 . The junction barrier Schottky diode 100 includes a silicon substrate 110 , a field oxide layer (field oxide) 120 , a field oxide layer 130 , a plurality of P-type doped regions 140 , a metal layer 150 , and an N-type doped region 160 .

硅基板110具有上表面111。硅基板110相对于上表面111的下方具有一N型埋层112(N buried layer,NBL)。硅基板110的上表面111以及N型埋层112之间是为一N型井113(Nwell)。场氧化层120以及场氧化层130分别设置N型井113之中,且由上表面111向下延伸。多个P型掺杂区140位于场氧化层120的一侧,所述多个P型掺杂区140分别设置于N型井113之中,且各个P型掺杂区140由上表面111向下延伸。The silicon substrate 110 has an upper surface 111 . The silicon substrate 110 has an N-type buried layer 112 (N buried layer, NBL) below the upper surface 111 . An N-type well 113 (Nwell) is formed between the upper surface 111 of the silicon substrate 110 and the N-type buried layer 112 . The field oxide layer 120 and the field oxide layer 130 are respectively disposed in the N-type well 113 and extend downward from the upper surface 111 . A plurality of P-type doped regions 140 are located on one side of the field oxide layer 120, and the plurality of P-type doped regions 140 are respectively arranged in the N-type well 113, and each P-type doped region 140 extends from the upper surface 111 to the Extend down.

金属层150覆盖于上表面111,并位于所述多个P型掺杂区140的上方。金属层150亦被电性引出形成所述接面位障萧特基二极管100的正极接点170。N型掺杂区160位于场氧化层120以及场氧化层130之间,且由上表面111向下延伸。N型掺杂区160主要是用以将N型井113之中的电流引出,并形成所述接面位障萧特基二极管100的负极接点180。The metal layer 150 covers the upper surface 111 and is located above the plurality of P-type doped regions 140 . The metal layer 150 is also electrically extracted to form the anode contact 170 of the junction barrier Schottky diode 100 . The N-type doped region 160 is located between the field oxide layer 120 and the field oxide layer 130 and extends downward from the upper surface 111 . The N-type doped region 160 is mainly used to draw out the current in the N-type well 113 and form the cathode contact 180 of the junction barrier Schottky diode 100 .

在图1中,以虚线表示的萧特基二极管组件101,即为接面位障萧特基二极管100的等效示意。又,金属层150的引出形成了正极接点170,N型掺杂区160的引出则形成了负极接点180,金属层150和N型井113之间的接面直接决定了主要特性,而主要电流路径则是发生在N型井113之中。另外,P型掺杂区140以及N型井113之间,又形成了寄生的二极管组件102,如图1中虚线所示。此一寄生的二极管组件102并联于等效的萧特基二极管组件101,但由于萧特基二极管组件101的顺向导通电压小于二极管组件102的顺向导通电压,因此在正常顺向导通的使用上,仍然是以萧特基二极管组件101的特性为主。In FIG. 1 , the Schottky diode assembly 101 represented by a dotted line is an equivalent schematic representation of the junction barrier Schottky diode 100 . Moreover, the extraction of the metal layer 150 forms the positive contact 170, and the extraction of the N-type doped region 160 forms the negative contact 180. The junction between the metal layer 150 and the N-type well 113 directly determines the main characteristics, and the main current The path then takes place in the N-type well 113 . In addition, a parasitic diode element 102 is formed between the P-type doped region 140 and the N-type well 113 , as shown by the dotted line in FIG. 1 . This parasitic diode assembly 102 is connected in parallel with the equivalent Schottky diode assembly 101, but since the forward conduction voltage of the Schottky diode assembly 101 is smaller than the forward conduction voltage of the diode assembly 102, it is used in normal forward conduction Above, the characteristics of the Schottky diode assembly 101 are still the main ones.

然而,一般习用的接面位障萧特基二极管100,在静电放电的能力上较差,尤其是当静电是以负电压的形式发生在接面位障萧特基二极管100时的两端时。习用的解决方式,是在接面位障萧特基二极管100上并联一组静电放电组件,以增强其静电放电能力。然而,静电放电组件的加入,将形成装置尺寸以及成本的增加。However, the commonly used junction barrier Schottky diode 100 is poor in electrostatic discharge capability, especially when static electricity occurs at both ends of the junction barrier Schottky diode 100 in the form of negative voltage. . A conventional solution is to connect a group of ESD components in parallel on the junction barrier Schottky diode 100 to enhance its ESD capability. However, the addition of ESD components will increase the size and cost of the device.

【发明内容】【Content of invention】

为了解决上述问题,本发明主要是提供一种接面位障萧特基二极管,特别是一种具有较佳静电放电效果的接面位障萧特基二极管。In order to solve the above problems, the present invention mainly provides a junction barrier Schottky diode, especially a junction barrier Schottky diode with better electrostatic discharge effect.

本发明提出一种接面位障萧特基二极管,包括硅基板、第一P型掺杂区、金属层、第二P型掺杂区、以及第一N型掺杂区。硅基板具有上表面,硅基板相对于上表面的下方具有N型埋层,硅基板的上表面以及N型埋层之间是为N型井,且由上表面向下延伸。第一P型掺杂区设置于N型井之中,并由上表面向下延伸。金属层覆盖于上表面,并位于第一P型掺杂区的一侧的上方。第二P型掺杂区设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区的另一侧。第一N型掺杂区设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区的另一侧。The invention provides a junction barrier Schottky diode, which includes a silicon substrate, a first P-type doped region, a metal layer, a second P-type doped region, and a first N-type doped region. The silicon substrate has an upper surface. The silicon substrate has an N-type buried layer below the upper surface. An N-type well is formed between the upper surface of the silicon substrate and the N-type buried layer and extends downward from the upper surface. The first P-type doped region is arranged in the N-type well and extends downward from the upper surface. The metal layer covers the upper surface and is located above one side of the first P-type doped region. The second P-type doped region is arranged in the N-type well, extends downward from the upper surface, and is located on the other side of the first P-type doped region. The first N-type doped region is arranged in the N-type well, extends downward from the upper surface, and is located on the other side of the first P-type doped region.

本发明一实施例中,更包括多个第三P型掺杂区,设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区的一侧,且位于金属层的下方。In one embodiment of the present invention, it further includes a plurality of third P-type doped regions, which are arranged in the N-type well, extend downward from the upper surface, and are located on one side of the first P-type doped region, and are located on the metal below the layer.

本发明一实施例中,更包括多个第一场氧化层,设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区的一侧,且位于金属层的下方。In one embodiment of the present invention, it further includes a plurality of first field oxide layers, which are arranged in the N-type well, extend downward from the upper surface, and are located on one side of the first P-type doped region, and are located on the side of the metal layer. below.

本发明一实施例中,更包括一第二场氧化层,设置于N型井之中,由上表面向下延伸,并位于第一P型掺杂区以及第一N型掺杂区之间。In one embodiment of the present invention, a second field oxide layer is further included, disposed in the N-type well, extending downward from the upper surface, and located between the first P-type doped region and the first N-type doped region .

本发明一实施例中,其中第一N型掺杂区位于第二P型掺杂区以及第一P型掺杂区之间。In an embodiment of the present invention, the first N-type doped region is located between the second P-type doped region and the first P-type doped region.

本发明一实施例中,其中第二P型掺杂区位于第一N型掺杂区以及第一P型掺杂区之间。In an embodiment of the present invention, the second P-type doped region is located between the first N-type doped region and the first P-type doped region.

本发明一实施例中,其中第一N型掺杂区相邻于第二P型掺杂区。In an embodiment of the present invention, the first N-type doped region is adjacent to the second P-type doped region.

本发明一实施例中,其中更包括一P型淡掺杂区,位于第二P型掺杂区的下方。In one embodiment of the present invention, it further includes a P-type lightly doped region, located below the second P-type doped region.

本发明一实施例中,其中更包括:第二N型掺杂区,设置于N型井之中,由上表面向下延伸,且第二P型掺杂区位于第一N型掺杂区以及第二N型掺杂区之间。In one embodiment of the present invention, it further includes: a second N-type doped region, disposed in the N-type well, extending downward from the upper surface, and the second P-type doped region is located in the first N-type doped region and between the second N-type doped regions.

本发明一实施例中,其中第一N型掺杂区、第二P型掺杂区以及第二N型掺杂区两两相邻。In an embodiment of the present invention, the first N-type doped region, the second P-type doped region, and the second N-type doped region are adjacent to each other.

本发明一实施例中,更包括:第三P型掺杂区,设置于N型井之中,由上表面向下延伸,且第一N型掺杂区位于第二P型掺杂区以及第三P型掺杂区之间。In an embodiment of the present invention, it further includes: a third P-type doped region, disposed in the N-type well, extending downward from the upper surface, and the first N-type doped region is located in the second P-type doped region and between the third P-type doped regions.

本发明一实施例中,其中第二P型掺杂区、第一N型掺杂区以及第三P型掺杂区两两相邻。In an embodiment of the present invention, the second P-type doped region, the first N-type doped region and the third P-type doped region are adjacent to each other.

本发明的功效在于,本发明所揭露的接面位障萧特基二极管,利用其结构中寄生的PNP型双极性接面晶体管组件,可以在接面位障萧特基二极管遭遇逆向的静电冲击时,增强其疏导静电电荷的能力,因此加强了接面位障萧特基二极管逆向的静电放电能力。The effect of the present invention is that the junction barrier Schottky diode disclosed in the present invention can utilize the parasitic PNP bipolar junction transistor component in its structure to encounter reverse static electricity when the junction barrier Schottky diode When it is impacted, its ability to conduct electrostatic charges is enhanced, so the reverse electrostatic discharge ability of the junction barrier Schottky diode is enhanced.

有关本创作的特征、实作与功效,兹配合图式作最佳实施例详细说明如下。Regarding the characteristics, implementation and effects of this creation, the best embodiment is described in detail as follows in conjunction with the drawings.

【附图说明】【Description of drawings】

图1:习用接面位障萧特基二极管的剖面结构图。Figure 1: The cross-sectional structure diagram of a conventional junction barrier Schottky diode.

图2:本发明接面位障萧特基二极管所揭露第一实施例的剖面结构图。FIG. 2 is a cross-sectional structure diagram of the disclosed first embodiment of the junction barrier Schottky diode of the present invention.

图3:本发明接面位障萧特基二极管所揭露第二实施例的剖面结构图。FIG. 3 is a cross-sectional structure diagram of the disclosed second embodiment of the junction barrier Schottky diode of the present invention.

图4:本发明接面位障萧特基二极管所揭露第三实施例的剖面结构图。FIG. 4 is a cross-sectional structure diagram of the disclosed third embodiment of the junction barrier Schottky diode of the present invention.

图5:本发明接面位障萧特基二极管所揭露第四实施例的剖面结构图。FIG. 5 is a cross-sectional structure diagram of the disclosed fourth embodiment of the junction barrier Schottky diode of the present invention.

图6:本发明接面位障萧特基二极管与习用技术的电流-电压关系图以及逆偏漏电流曲线图。Fig. 6: The current-voltage relationship diagram and the reverse bias leakage current curve diagram of the junction barrier Schottky diode of the present invention and the conventional technology.

主要组件符号说明:Description of main component symbols:

100、200、300、400、500 接面位障萧特基二极管 140 P型掺杂区100, 200, 300, 400, 500 Junction barrier Schottky diode 140 P-type doped region

150、250 金属层150, 250 metal layers

101、201 等效的萧特基二极管组件 160 N型掺杂区101, 201 Equivalent Schottky diode components 160 N-type doped region

170、270 正极接点170, 270 positive contacts

102 寄生的二极管组件 180、280 负极接点102 Parasitic Diode Assembly 180, 280 Negative Contact

110、210 硅基板 202 寄生的PNP型双极性接面晶体管110, 210 Silicon substrate 202 Parasitic PNP bipolar junction transistor

111、211 上表面 220 第二场氧化层111, 211 Upper surface 220 Second field oxide layer

112、212 N型埋层 230 第三场氧化层112, 212 N-type buried layer 230 Third field oxide layer

113、213 N型井 240 第一P型掺杂区113, 213 N-type well 240 First P-type doped region

120、130 场氧化层 245 逆偏漏电流抑制结构(第三P型掺杂区、第一场氧化层)120, 130 Field oxide layer 245 Reverse bias leakage current suppression structure (third P-type doped region, first field oxide layer)

266 第二N型掺杂区266 Second N-type doped region

260 第一N型掺杂区 268 第三P型掺杂区260 The first N-type doped region 268 The third P-type doped region

262 第二P型掺杂区 610、620、630、640、650、660 曲线262 Curves of the second P-type doped region 610, 620, 630, 640, 650, 660

264 P型淡掺杂区264 P-type lightly doped region

【具体实施方式】【detailed description】

图2为本发明接面位障萧特基二极管200所揭露第一实施例的剖面结构图。本发明接面位障萧特基二极管200是利用半导体制程所实现的组件。接面位障萧特基二极管200包括硅基板210、第一P型掺杂区240、金属层250、第二P型掺杂区262、以及第一N型掺杂区260。FIG. 2 is a cross-sectional structure diagram of the disclosed first embodiment of the junction barrier Schottky diode 200 of the present invention. The junction barrier Schottky diode 200 of the present invention is a component realized by semiconductor manufacturing process. The junction barrier Schottky diode 200 includes a silicon substrate 210 , a first P-type doped region 240 , a metal layer 250 , a second P-type doped region 262 , and a first N-type doped region 260 .

硅基板210具有上表面211。硅基板210相对于上表面211的下方具有一N型埋层212。硅基板210的上表面211以及N型埋层212之间是为一N型井213。N型埋层212是用以减少上方组件之间的漏电流,使得组件的排列上可以更紧密,缩小整体面积。The silicon substrate 210 has an upper surface 211 . The silicon substrate 210 has an N-type buried layer 212 below the upper surface 211 . An N-type well 213 is formed between the upper surface 211 of the silicon substrate 210 and the N-type buried layer 212 . The N-type buried layer 212 is used to reduce the leakage current between the upper components, so that the components can be arranged more closely and the overall area can be reduced.

第一P型掺杂区240设置于N型井213之中,并由上表面211向下延伸。金属层250覆盖于上表面211,并位于第一P型掺杂区240的一侧的上方。金属层250和N型井213之间的接面,即形成了接面位障萧特基二极管200的金属-半导体(metal-semiconductor)接面,直接决定了接面位障萧特基二极管200的主要特性,金属层250亦被电性引出形成接面位障萧特基二极管200的正极接点270。第二P型掺杂区262设置于N型井213之中,由上表面211向下延伸,并位于第一P型掺杂区240的另一侧。第一N型掺杂区260设置于N型井213之中,由上表面211向下延伸,并位于第一P型掺杂区240的另一侧。The first P-type doped region 240 is disposed in the N-type well 213 and extends downward from the upper surface 211 . The metal layer 250 covers the upper surface 211 and is located above one side of the first P-type doped region 240 . The junction between the metal layer 250 and the N-type well 213, that is, the metal-semiconductor (metal-semiconductor) junction that forms the junction barrier Schottky diode 200, directly determines the junction barrier Schottky diode 200. The main characteristic of the metal layer 250 is also electrically drawn out to form the anode contact 270 of the junction barrier Schottky diode 200 . The second P-type doped region 262 is disposed in the N-type well 213 , extends downward from the upper surface 211 , and is located on the other side of the first P-type doped region 240 . The first N-type doped region 260 is disposed in the N-type well 213 , extends downward from the upper surface 211 , and is located on the other side of the first P-type doped region 240 .

在图2所示的实施例之中,第一N型掺杂区260位于第二P型掺杂区262以及第一P型掺杂区240之间,但值得注意的是,本发明所揭露的接面位障萧特基二极管200的结构并不以此为限。In the embodiment shown in FIG. 2, the first N-type doped region 260 is located between the second P-type doped region 262 and the first P-type doped region 240. The structure of the junction barrier Schottky diode 200 is not limited thereto.

在图2中,以虚线表示的萧特基二极管组件201,即为接面位障萧特基二极管200的等效示意组件。又,金属层250的引出形成了正极接点270,第一N型掺杂区260的引出则形成了负极接点280,金属层250和N型井213之间的接面直接决定了主要特性,而主要电流路径则是发生在N型井213之中。另外,第二P型掺杂区262、N型井213、以及第一P型掺杂区240的结构又形成了寄生的PNP型双极性接面晶体管(bipolar junction transistor,BJT)组件202,如图2中虚线所示。其中N型井213的电位是利用第一N型掺杂区260引出而决定。此一寄生的晶体管组件202的射极(emitter)和基极(base)并联于等效的萧特基二极管组件201,但由于萧特基二极管组件201的顺向导通电压小于晶体管组件202的射极和基极之间的顺向导通电压,因此在正常顺向导通的使用上,仍然是以萧特基二极管组件201的特性为主。In FIG. 2 , the Schottky diode component 201 indicated by a dotted line is an equivalent schematic component of the junction barrier Schottky diode 200 . Moreover, the extraction of the metal layer 250 forms the positive contact 270, and the extraction of the first N-type doped region 260 forms the negative contact 280. The junction between the metal layer 250 and the N-type well 213 directly determines the main characteristics, and The main current path occurs in the N-well 213 . In addition, the structure of the second P-type doped region 262, the N-type well 213, and the first P-type doped region 240 forms a parasitic PNP-type bipolar junction transistor (bipolar junction transistor, BJT) component 202, As shown by the dotted line in Figure 2. The potential of the N-type well 213 is determined by drawing out the first N-type doped region 260 . The emitter (emitter) and base (base) of this parasitic transistor assembly 202 are connected in parallel with the equivalent Schottky diode assembly 201, but because the forward conduction voltage of the Schottky diode assembly 201 is smaller than the emitter of the transistor assembly 202 The forward conduction voltage between the pole and the base, therefore, the characteristics of the Schottky diode assembly 201 are still the main factors in the use of normal forward conduction.

然而,当接面位障萧特基二极管200遭遇逆向的静电冲击时,接面位障萧特基二极管200的正负接点之间首先会形成逆偏的电流,此一逆偏的电流主要是由负极接点280进入,并流经第一N型掺杂区260、N型井213、金属层250,最后由正极接点270流出。当此一逆偏的电流增加到一定的量,使得其在N型井213中所造成的压降够大,导致晶体管组件202的射极和基极之间形成导通时,晶体管组件202亦即导通,且晶体管的主要通道,亦即第二P型掺杂区262与第一P型掺杂区240之间,形成了较强的导通电流能力,故而增强了疏导静电电荷的能力。换言之,寄生的晶体管组件202的存在,加强了接面位障萧特基二极管200逆向的静电放电能力。However, when the junction barrier Schottky diode 200 encounters a reverse electrostatic impact, a reverse-biased current will first be formed between the positive and negative contacts of the junction barrier Schottky diode 200, and this reverse-biased current is mainly It enters from the negative contact 280 , flows through the first N-type doped region 260 , the N-type well 213 , the metal layer 250 , and finally flows out from the positive contact 270 . When this reverse-biased current increases to a certain amount, so that the voltage drop caused in the N-type well 213 is large enough to cause conduction between the emitter and the base of the transistor component 202, the transistor component 202 is also That is, it is turned on, and the main channel of the transistor, that is, between the second P-type doped region 262 and the first P-type doped region 240, forms a strong conduction current capability, thus enhancing the ability to conduct electrostatic charges . In other words, the presence of the parasitic transistor component 202 enhances the reverse ESD capability of the junction barrier Schottky diode 200 .

进一步说明,本发明所揭露的接面位障萧特基二极管200之中,可以更进一步包括多个逆偏漏电流抑制结构245,设置于N型井213之中,由上表面211向下延伸,并位于第一P型掺杂区240的一侧,且位于金属层250的下方。逆偏漏电流抑制结构245可以是多个P型掺杂区(例如定义为多个第三P型掺杂区),或是多个场氧化层(例如定义为多个第一场氧化层)的结构,其中场氧化层的结构亦包含先进制程(0.35微米制程之后)中的浅沟槽隔离(Shallow Trench Isolation,STI)结构。在各个逆偏漏电流抑制结构245之间,以及逆偏漏电流抑制结构245和第一P型掺杂区240之间的N型井213的区域,形成了接面位障萧特基二极管200的主要电流路径。设置所述多个逆偏漏电流抑制结构245的结构,可以减少接面位障萧特基二极管200在逆向偏压时,正负接点之间漏电流的量。To further illustrate, the junction barrier Schottky diode 200 disclosed in the present invention may further include a plurality of reverse bias leakage current suppression structures 245 disposed in the N-type well 213 and extending downward from the upper surface 211 , and located on one side of the first P-type doped region 240 , and located below the metal layer 250 . The reverse bias leakage current suppression structure 245 can be a plurality of P-type doped regions (for example, defined as a plurality of third P-type doped regions), or a plurality of field oxide layers (for example, defined as a plurality of first field oxide layers) The structure of the field oxide layer also includes the shallow trench isolation (Shallow Trench Isolation, STI) structure in the advanced process (after the 0.35 micron process). Between each reverse bias leakage current suppression structure 245, and in the region of the N-type well 213 between the reverse bias leakage current suppression structure 245 and the first P-type doped region 240, a junction barrier Schottky diode 200 is formed. main current path. The arrangement of the plurality of reverse bias leakage current suppression structures 245 can reduce the amount of leakage current between the positive and negative contacts of the junction barrier Schottky diode 200 when it is reverse biased.

再者,如图2所示,接面位障萧特基二极管200的结构中,可以更包括第二场氧化层220,设置于N型井213之中,由上表面211向下延伸,并位于第一P型掺杂区240以及第一N型掺杂区260之间。第二场氧化层220是为以半导体制程配合接面位障萧特基二极管200的制作时,通常会形成的结构,因此可以作为接面位障萧特基二极管200的结构特征之一。但值得注意的是,第二场氧化层220并非为一必要的结构。此外,接面位障萧特基二极管200更可以进一步包括第三场氧化层230,位于接面位障萧特基二极管200结构的最外层,以作为与其他组件的区隔。Moreover, as shown in FIG. 2, the structure of the junction barrier Schottky diode 200 may further include a second field oxide layer 220, which is disposed in the N-type well 213, extends downward from the upper surface 211, and Located between the first P-type doped region 240 and the first N-type doped region 260 . The second field oxide layer 220 is a structure that is usually formed when the junction barrier Schottky diode 200 is manufactured with semiconductor manufacturing process, so it can be used as one of the structural features of the junction barrier Schottky diode 200 . But it should be noted that the second field oxide layer 220 is not a necessary structure. In addition, the junction barrier Schottky diode 200 may further include a third field oxide layer 230 located at the outermost layer of the junction barrier Schottky diode 200 to separate it from other components.

如图2所示,在本发明又一实施例中,第一N型掺杂区260相邻于第二P型掺杂区262,此为较佳的实施方式,可以使得接面位障萧特基二极管200的面积较小,以节省硬件成本。然而相邻的方式并非必要的排列方式,第一N型掺杂区260以及第二P型掺杂区262之间可以间隔一特定距离,而并不影响本发明所揭露的接面位障萧特基二极管200的主要特性。As shown in FIG. 2, in another embodiment of the present invention, the first N-type doped region 260 is adjacent to the second P-type doped region 262. This is a preferred implementation mode, which can make the junction barrier The area of the terky diode 200 is small to save hardware cost. However, the adjacent arrangement is not a necessary arrangement, and a specific distance can be spaced between the first N-type doped region 260 and the second P-type doped region 262 without affecting the junction barrier disclosed in the present invention. The main characteristics of the terky diode 200.

再者,如图2所示,在本发明又一实施例中,可以更进一步包括P型淡掺杂区264,位于第二P型掺杂区262的下方。P型淡掺杂区264具有相较于第一P型掺杂区240更淡的P型掺杂浓度,因此加强了寄生的晶体管组件202的贝他(β,beta)增益,亦即晶体管组件202具有更强的电流导通效果,也因此增强了本发明所揭露的接面位障萧特基二极管200逆向的静电放电能力。Moreover, as shown in FIG. 2 , in yet another embodiment of the present invention, a P-type lightly doped region 264 may be further included, located below the second P-type doped region 262 . The P-type lightly doped region 264 has a lighter P-type doping concentration than the first P-type doped region 240, thus enhancing the beta (β, beta) gain of the parasitic transistor component 202, that is, the transistor component 202 has a stronger current conduction effect, and thus enhances the reverse electrostatic discharge capability of the junction barrier Schottky diode 200 disclosed in the present invention.

图3为本发明接面位障萧特基二极管300所揭露第二实施例的剖面结构图。本发明接面位障萧特基二极管300与第一实施例的接面位障萧特基二极管200的不同之处在于,第一实施例的接面位障萧特基二极管200,其第一N型掺杂区260位于第二P型掺杂区262以及第一P型掺杂区240之间,而第二实施例的接面位障萧特基二极管300,其第二P型掺杂区262位于第一N型掺杂区260以及第一P型掺杂区240之间。接面位障萧特基二极管300所形成的结构,使得第一N型掺杂区260较为远离第一P型掺杂区240,如此当接面位障萧特基二极管300发生逆向偏压并形成逆偏的电流时,在同样的电流值下,将造成N型井213中更大的压降,而使得接面位障萧特基二极管300的寄生晶体管组件(如图2中的组件202)更容易被导通,因此具有更佳的逆向静电放电能力。FIG. 3 is a cross-sectional structural view of a second embodiment of a junction barrier Schottky diode 300 disclosed in the present invention. The junction barrier Schottky diode 300 of the present invention differs from the junction barrier Schottky diode 200 of the first embodiment in that the junction barrier Schottky diode 200 of the first embodiment has a first The N-type doped region 260 is located between the second P-type doped region 262 and the first P-type doped region 240, and the junction barrier Schottky diode 300 of the second embodiment, its second P-type doped The region 262 is located between the first N-type doped region 260 and the first P-type doped region 240 . The structure formed by the junction barrier Schottky diode 300 makes the first N-type doped region 260 far away from the first P-type doped region 240, so that when the junction barrier Schottky diode 300 is reverse-biased and When a reverse biased current is formed, at the same current value, a larger voltage drop in the N-type well 213 will be caused, so that the parasitic transistor component of the junction barrier Schottky diode 300 (such as the component 202 in FIG. 2 ) is easier to be turned on, so it has better reverse electrostatic discharge capability.

另外,如图3所示,本发明接面位障萧特基二极管300的第一N型掺杂区260相邻于第二P型掺杂区262,此为较佳的实施方式,但并不以此为限,可参考第一实施例中的相关说明,在此不另赘述。再者,接面位障萧特基二极管300的又一实施例中,可以更进一步包括P型淡掺杂区264,位于第二P型掺杂区262的下方。In addition, as shown in FIG. 3, the first N-type doped region 260 of the junction barrier Schottky diode 300 of the present invention is adjacent to the second P-type doped region 262. This is a preferred implementation mode, but it does not It is not limited thereto, and reference may be made to relevant descriptions in the first embodiment, which will not be repeated here. Furthermore, in yet another embodiment of the junction barrier Schottky diode 300 , it may further include a P-type lightly doped region 264 located below the second P-type doped region 262 .

图4为本发明接面位障萧特基二极管400所揭露第三实施例的剖面结构图。与第一实施例的接面位障萧特基二极管200的不同之处在于,接面位障萧特基二极管400更包括了第二N型掺杂区266,设置于N型井213之中,由上表面211向下延伸,且第二P型掺杂区262位于第一N型掺杂区260以及所述第二N型掺杂区266之间。此为一结构上的变形,其组件功效可以参考第一实施例的说明,在此不另赘述。FIG. 4 is a cross-sectional structural view of a third embodiment of a junction barrier Schottky diode 400 disclosed in the present invention. The difference from the junction barrier Schottky diode 200 of the first embodiment is that the junction barrier Schottky diode 400 further includes a second N-type doped region 266 disposed in the N-type well 213 , extending downward from the upper surface 211 , and the second P-type doped region 262 is located between the first N-type doped region 260 and the second N-type doped region 266 . This is a structural modification, and the function of its components can refer to the description of the first embodiment, and will not be repeated here.

另外,如图4所示,在本发明所揭露的接面位障萧特基二极管400的又一实施例中,其中第一N型掺杂区260、第二P型掺杂区262、以及第二N型掺杂区266是以两两相邻的方式紧密排列,此为较佳的实施方式,但并不以此为限,可参考第一实施例中的相关说明,在此不另赘述。In addition, as shown in FIG. 4, in another embodiment of the junction barrier Schottky diode 400 disclosed in the present invention, the first N-type doped region 260, the second P-type doped region 262, and The second N-type doped regions 266 are closely arranged in pairs adjacent to each other. This is a preferred implementation mode, but it is not limited thereto. Reference may be made to the relevant descriptions in the first embodiment, and no further description is made here. repeat.

图5为本发明接面位障萧特基二极管500所揭露第四实施例的剖面结构图。与第一实施例的接面位障萧特基二极管200的不同之处在于,接面位障萧特基二极管500更包括了第三P型掺杂区268,设置于N型井213之中,由上表面211向下延伸,且第一N型掺杂区260位于第二P型掺杂区262以及第三P型掺杂区268之间。此为一结构上的变形,其组件功效可以参考第一实施例的说明,在此不另赘述。FIG. 5 is a cross-sectional structural diagram of a fourth embodiment of a junction barrier Schottky diode 500 disclosed in the present invention. The difference from the junction barrier Schottky diode 200 of the first embodiment is that the junction barrier Schottky diode 500 further includes a third P-type doped region 268 disposed in the N-type well 213 , extending downward from the upper surface 211 , and the first N-type doped region 260 is located between the second P-type doped region 262 and the third P-type doped region 268 . This is a structural modification, and the function of its components can refer to the description of the first embodiment, and will not be repeated here.

另外,如图5所示,在本发明接面位障萧特基二极管500的又一实施例中,其中第二P型掺杂区262、第一N型掺杂区260以及第三P型掺杂区268是以两两相邻的方式紧密排列,此为较佳的实施方式,但并不以此为限,可参考第一实施例中的相关说明,在此不另赘述。In addition, as shown in FIG. 5, in another embodiment of the junction barrier Schottky diode 500 of the present invention, the second P-type doped region 262, the first N-type doped region 260 and the third P-type doped region The doped regions 268 are closely arranged in a manner of adjacent to each other, which is a preferred implementation manner, but not limited thereto. Reference may be made to relevant descriptions in the first embodiment, and details will not be repeated here.

图6为本发明接面位障萧特基二极管与习用技术的电流-电压关系图以及逆偏漏电流曲线图。其中本发明所揭露者是以第一实施例的接面位障萧特基二极管200作为量测对象,并且再分为「不包含P型淡掺杂区264」(图中方形标识)以及「包含P型淡掺杂区264」(图中三角形标识)两种类别。习用技术者则以图1所揭露的接面位障萧特基二极管100作为量测对象(图中菱形标识)。其中曲线610、620、630为逆向电流对于逆偏电压的关系图,其横轴应对应于下方轴,即「逆偏电压」;而曲线630、640、650则为每次以某一逆偏电压量测完成之后,再以一般应用上的逆偏电压(例如5伏特)量测其逆偏漏电流,其横轴应对应于上方轴,即「逆偏漏电流」。由图6中可发现,三种结构的接面位障萧特基二极管,在施加过大的逆偏电压造成其损坏之前,三者的逆偏漏电流的数量级相差不多,约在1微安培左右,因此在正常应用之下,其组件特性应该是相去不远。再者,当对应特定的逆偏电压,例如65伏特时,可以发现习用技术所实现的接面位障萧特基二极管,其导通的逆向电流最小,也就是说,其疏导逆向静电压电荷的能力最差,静电放电能力最弱。其次则是「不包含P型淡掺杂区264」的接面位障萧特基二极管的结构,最大的则是「包含P型淡掺杂区264」的接面位障萧特基二极管的结构,此正好印证前述「P型淡掺杂区264具有相较于第一P型掺杂区240更淡的P型掺杂浓度,因此加强了寄生的晶体管组件202的贝他(β,beta)增益,亦即晶体管组件202具有更强的电流导通效果,也因此增强了本发明所揭露的接面位障萧特基二极管200逆向的静电放电能力」的说法。FIG. 6 is a current-voltage relationship diagram and a reverse bias leakage current curve diagram of the junction barrier Schottky diode of the present invention and the conventional technology. Wherein the disclosure of the present invention takes the junction barrier Schottky diode 200 of the first embodiment as the measurement object, and further divides it into "not including the P-type lightly doped region 264" (square mark in the figure) and " It includes two types of P-type lightly doped regions 264" (marked by triangles in the figure). Those skilled in the art use the junction barrier Schottky diode 100 disclosed in FIG. 1 as the measurement object (marked with a rhombus in the figure). Among them, the curves 610, 620, and 630 are the relationship diagrams of the reverse current and the reverse bias voltage, and the horizontal axis should correspond to the lower axis, that is, "reverse bias voltage"; while the curves 630, 640, and 650 are the After the voltage measurement is completed, measure the reverse-bias leakage current with the reverse-bias voltage (for example, 5 volts) used in general applications. The horizontal axis should correspond to the upper axis, that is, "reverse-bias leakage current". From Figure 6, it can be found that the junction barrier Schottky diodes of the three structures, before excessive reverse bias voltage is applied to cause damage, the order of magnitude of the reverse bias leakage current of the three is similar, about 1 microampere So under normal application, its component characteristics should be not far from each other. Furthermore, when corresponding to a specific reverse bias voltage, such as 65 volts, it can be found that the junction barrier Schottky diode realized by conventional technology has the smallest conduction reverse current, that is to say, it can discharge the reverse electrostatic charge The ability of the worst, electrostatic discharge ability is the weakest. The second is the structure of the junction barrier Schottky diode "not including the P-type lightly doped region 264", and the largest is the structure of the junction barrier Schottky diode "including the P-type lightly doped region 264". structure, which just confirms the aforementioned "P-type lightly doped region 264 has a lighter P-type doping concentration than the first P-type doped region 240, thus strengthening the beta (β, beta) of the parasitic transistor component 202 ) gain, that is, the transistor component 202 has a stronger current conduction effect, and thus enhances the reverse electrostatic discharge capability of the junction barrier Schottky diode 200 disclosed in the present invention”.

虽然本发明的实施例揭露如上所述,然并非用以限定本发明,任何熟习相关技艺者,在不脱离本发明的精神和范围内,举凡依本发明申请范围所述的形状、构造、特征及数量当可做些许的变更,因此本发明的专利保护范围须视本说明书所附的申请专利范围所界定者为准。Although the embodiments of the present invention are disclosed as above, they are not intended to limit the present invention. Anyone skilled in the relevant art can use the shapes, structures, and features described in the application scope of the present invention without departing from the spirit and scope of the present invention. and quantity can be slightly changed, so the scope of patent protection of the present invention must be defined by the scope of patent application attached to this specification.

Claims (9)

1.一种接面位障萧特基二极管,其特征在于,所述接面位障萧特基二极管包含:1. a junction barrier Schottky diode, characterized in that the junction barrier Schottky diode comprises: 一硅基板,具有一上表面,所述硅基板相对于所述上表面的下方具有一N型埋层,所述硅基板的所述上表面以及所述N型埋层之间是为一N型井;A silicon substrate has an upper surface, the silicon substrate has an N-type buried layer below the upper surface, and an N-type buried layer is located between the upper surface of the silicon substrate and the N-type buried layer. type well; 一第一P型掺杂区,设置于所述N型井之中,并由所述上表面向下延伸;a first P-type doped region, disposed in the N-type well, and extending downward from the upper surface; 一金属层,覆盖于所述上表面,并位于所述第一P型掺杂区的一侧的上方;a metal layer covering the upper surface and located above one side of the first P-type doped region; 一第二P型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区的另一侧;以及a second P-type doped region, disposed in the N-type well, extending downward from the upper surface, and located on the other side of the first P-type doped region; and 一第一N型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区的另一侧;A first N-type doped region, disposed in the N-type well, extending downward from the upper surface, and located on the other side of the first P-type doped region; 其中所述第一N型掺杂区位于所述第二P型掺杂区以及所述第一P型掺杂区之间;Wherein the first N-type doped region is located between the second P-type doped region and the first P-type doped region; 其中所述接面位障萧特基二极管更包括一第二N型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,且所述第二P型掺杂区位于所述第一N型掺杂区以及所述第二N型掺杂区之间。Wherein the junction barrier Schottky diode further includes a second N-type doped region, disposed in the N-type well, extending downward from the upper surface, and the second P-type doped region The region is located between the first N-type doped region and the second N-type doped region. 2.如权利要求1所述的接面位障萧特基二极管,其特征在于,所述接面位障萧特基二极管更包括多个第三P型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区的一侧,且位于所述金属层的下方。2. The junction barrier Schottky diode as claimed in claim 1, characterized in that, the junction barrier Schottky diode further comprises a plurality of third P-type doped regions arranged in the N-type The well extends downward from the upper surface, is located on one side of the first P-type doped region, and is located below the metal layer. 3.如权利要求1所述的接面位障萧特基二极管,其特征在于,所述接面位障萧特基二极管更包括多个第一场氧化层,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区的一侧,且位于所述金属层的下方。3. The junction barrier Schottky diode according to claim 1, wherein the junction barrier Schottky diode further comprises a plurality of first field oxide layers disposed between the N-type wells , extending downward from the upper surface, and located on one side of the first P-type doped region, and located below the metal layer. 4.如权利要求1所述的接面位障萧特基二极管,其特征在于,所述接面位障萧特基二极管更包括一第二场氧化层,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区以及所述第一N型掺杂区之间。4. The junction barrier Schottky diode according to claim 1, wherein the junction barrier Schottky diode further comprises a second field oxide layer disposed in the N-type well , extending downward from the upper surface and located between the first P-type doped region and the first N-type doped region. 5.如权利要求1所述的接面位障萧特基二极管,其特征在于,其中所述第一N型掺杂区相邻于所述第二P型掺杂区。5. The junction barrier Schottky diode of claim 1, wherein the first N-type doped region is adjacent to the second P-type doped region. 6.如权利要求1至5中任一项所述的接面位障萧特基二极管,其特征在于,所述接面位障萧特基二极管更包括一P型淡掺杂区,位于所述第二P型掺杂区的下方。6. The junction barrier Schottky diode according to any one of claims 1 to 5, characterized in that, the junction barrier Schottky diode further comprises a P-type lightly doped region located at the Below the second P-type doped region. 7.如权利要求1所述的接面位障萧特基二极管,其特征在于,其中所述第一N型掺杂区、所述第二P型掺杂区以及所述第二N型掺杂区两两相邻。7. The junction barrier Schottky diode according to claim 1, wherein the first N-type doped region, the second P-type doped region and the second N-type doped region Miscellaneous areas are adjacent to each other. 8.一种接面位障萧特基二极管,其特征在于,所述接面位障萧特基二极管包含:8. A junction barrier Schottky diode, characterized in that the junction barrier Schottky diode comprises: 一硅基板,具有一上表面,所述硅基板相对于所述上表面的下方具有一N型埋层,所述硅基板的所述上表面以及所述N型埋层之间是为一N型井;A silicon substrate has an upper surface, the silicon substrate has an N-type buried layer below the upper surface, and an N-type buried layer is located between the upper surface of the silicon substrate and the N-type buried layer. type well; 一第一P型掺杂区,设置于所述N型井之中,并由所述上表面向下延伸;a first P-type doped region, disposed in the N-type well, and extending downward from the upper surface; 一金属层,覆盖于所述上表面,并位于所述第一P型掺杂区的一侧的上方;a metal layer covering the upper surface and located above one side of the first P-type doped region; 一第二P型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区的另一侧;以及a second P-type doped region, disposed in the N-type well, extending downward from the upper surface, and located on the other side of the first P-type doped region; and 一第一N型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,并位于所述第一P型掺杂区的另一侧;A first N-type doped region, disposed in the N-type well, extending downward from the upper surface, and located on the other side of the first P-type doped region; 其中所述第二P型掺杂区位于所述第一N型掺杂区以及所述第一P型掺杂区之间;Wherein the second P-type doped region is located between the first N-type doped region and the first P-type doped region; 其中所述接面位障萧特基二极管更包括一第三P型掺杂区,设置于所述N型井之中,由所述上表面向下延伸,且所述第一N型掺杂区位于所述第二P型掺杂区以及所述第三P型掺杂区之间。Wherein the junction barrier Schottky diode further includes a third P-type doped region, disposed in the N-type well, extending downward from the upper surface, and the first N-type doped region The region is located between the second P-type doped region and the third P-type doped region. 9.如权利要求8所述的接面位障萧特基二极管,其特征在于,其中所述第二P型掺杂区、所述第一N型掺杂区以及所述第三P型掺杂区两两相邻。9. The junction barrier Schottky diode according to claim 8, wherein the second P-type doped region, the first N-type doped region and the third P-type doped region Miscellaneous areas are adjacent to each other.
CN201410274278.8A 2014-06-19 2014-06-19 junction barrier Schottky diode Expired - Fee Related CN104183653B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612567A (en) * 1996-05-13 1997-03-18 North Carolina State University Schottky barrier rectifiers and methods of forming same
CN1855549A (en) * 2005-03-30 2006-11-01 三洋电机株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612567A (en) * 1996-05-13 1997-03-18 North Carolina State University Schottky barrier rectifiers and methods of forming same
CN1855549A (en) * 2005-03-30 2006-11-01 三洋电机株式会社 Semiconductor device

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