CN104183595A - Gate dielectric layer protection - Google Patents
Gate dielectric layer protection Download PDFInfo
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- CN104183595A CN104183595A CN201310189992.2A CN201310189992A CN104183595A CN 104183595 A CN104183595 A CN 104183595A CN 201310189992 A CN201310189992 A CN 201310189992A CN 104183595 A CN104183595 A CN 104183595A
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Abstract
The invention discloses gate dielectric layer protection. A gate dielectric layer protection circuit is used to be coupled onto a risk transistor for realizing gate dielectric layer protection. The protection circuit is started to enable voltage VDIFF across two ends of the gate dielectric layer to be reduced to be lower than breakdown voltage VBD. When an electrostatic discharge event is detected, the protection circuit is started. The protection circuit provides protection or electrostatic discharge bias to enable VDIFF to be reduced to be lower than VBD.
Description
Technical field
The invention relates to a kind of gate dielectric protection.
Background technology
High pressure gathers and betides static discharge (electrostatic discharge; ESD) integrated circuit (integrated circuit during event; IC) input and output (input/output; I/O) pad.This high pressure gathers and can cause the gate dielectric of input stage transistor to damage.For example,, if the grid of this input stage transistor to underlayer voltage is greater than the puncture voltage (V of this gate dielectric
bD), may make this transistor produce defect.
The conventional art of protection gate dielectric comprises that use clamp circuit (clamping circuit) is to limit the voltage at these gate dielectric two ends.But, conventional art is not very effective to the protection of the gate dielectric of more recent technology.Its reason is that the trigger voltage of this clamp circuit is greater than the puncture voltage V of this gate dielectric
bD.For example, while opening (switch on) this clamp circuit, the voltage at these gate dielectric two ends has been greater than V
bD.
Therefore be desirable to provide gate dielectric protection, fully to avoid the voltage at these gate dielectric two ends higher than V
bD.
Summary of the invention
The method that embodiments of the invention are usually directed to semiconductor device and form device.In one embodiment, disclose a kind of device.This device comprises transistor, and it has the grid being positioned on substrate.This grid comprises the gate electrode that is positioned at gate dielectric top.This device also comprises and is coupled to this transistorized gate dielectric protection module.This gate dielectric protection module provides protection biasing (bias) when starting, with by the voltage difference (V between this grid and substrate
dIFF) be brought down below the puncture voltage (V of this gate dielectric
bD).
In another embodiment, provide a kind of method that forms device.The method comprises formation transistor, and this transistor has the grid being positioned on substrate.This grid comprises the gate electrode that is positioned at gate dielectric top.The method also comprises that formation is coupled to this transistorized gate dielectric protection module.This gate dielectric protection module provides protection biasing when starting, with by the voltage difference (V between this grid and substrate
dIFF) be brought down below the puncture voltage (V of this gate dielectric
bD).
In another embodiment, disclose a kind of method of protecting gate dielectric.The method comprises provides risk transistor (transistor at risk).Formation is coupled to the transistorized protection module of this risk.Start this protection module so that protection biasing to be provided, thereby by the voltage difference (V between the transistorized grid of this risk and substrate
dIFF) be brought down below the puncture voltage (V of the transistorized gate dielectric of this risk
bD).
After explanation and accompanying drawing below reference, above-mentioned and other advantage of disclosed embodiment and feature will become clearer here.And, should be appreciated that the feature of different embodiment described here is not repelled mutually, but can do various combinations and arrangement.
Accompanying drawing explanation
In accompanying drawing, similarly Reference numeral represents the same components in different views conventionally.In addition, those accompanying drawings might not be drawn in proportion, and it focuses on illustrating principle of the present invention.In the following description, with reference to accompanying drawing, different embodiments of the invention are described, wherein:
Fig. 1 shows the calcspar of part of the embodiment of a device;
Fig. 2 a to Fig. 2 b shows the embodiment of gate dielectric protection module; And
Fig. 3 a to Fig. 3 d shows the different embodiment of esd protection circuit.
Embodiment
Embodiments of the invention are usually directed to semiconductor device.In one embodiment, those devices comprise protection module.For example, during esd event, start this protection module and exempt from this esd event damage with the transistorized gate dielectric of protection risk.For example, those devices can be the semiconductor device of any type, for example integrated circuit (IC).Those integrated circuits can be contained in for example electronic product, computer, mobile phone and personal digital assistant (personal digital assistant; PDA) in or therewith, use.Those devices also can be contained in the product of other type.
The part of the embodiment of Fig. 1 display unit 100.As shown in the figure, this part comprises internal circuit or unit 120.This unit is coupled between first and second power path 102,104.This first power path can be V
dD(operating voltage) and this second power path can be V
sS(ground connection).Also can use the power path of other configuration.This unit is coupled to the weld pad 110 of this device.In one embodiment, this weld pad is I/O pad.This I/O receives I/O signal.For example, this I/O signal can be input signal or two-way signaling.Also can use the weld pad of other type.
In one embodiment, this unit comprises inverter, and it has coupled in series first and second transistor 130,140 between those power paths.Also can use the unit of other type.Those transistors can be metal-oxide semiconductor (metal oxide semiconductor; MOS) transistor.In one embodiment, this first transistor is that p-type transistor and this transistor seconds are N-shaped transistor.The first terminal of this first transistor is coupled to this first power path, and the second terminal of this first transistor is coupled to the second terminal of this transistor seconds.The first terminal of this transistor seconds is coupled to this second power path.The body that the body of this first transistor (body) is coupled to this first power path and this transistor seconds is coupled to this second power path.
The input 134 of this inverter is coupled to those transistorized grids jointly.The output 136 of this inverter is coupled to those transistorized the second terminals jointly.In one embodiment, by this inverter configuration, be receiver.For example, this weld pad is coupled to the input of this inverter.This output is coupled to other internal circuit (not shown).This inverter also can have other configuration.
Esd event can betide this weld pad.This esd event for example can be and is provided in the ESD of this weld pad or trigger stimulates (trigger stimulus) for example result of ESD or energy pulse.Also can use the triggering of other type that causes esd event to stimulate.This ESD stimulates can be not intended to or unexpectedly be provided in this weld pad.For example, or this ESD stimulates can have a mind to be provided in this weld pad, in the situation that ESD tests.
This esd event makes the transistor of this unit in desperate situation.For example, this esd event can damage the transistorized gate dielectric of this risk, thereby makes this unit produce defect.In one embodiment, this esd event makes the transistor seconds of this inverter in desperate situation.For example, this esd event makes this N-shaped MOS transistor in desperate situation.In other cases, this ESD can make the transistor of other type in desperate situation.
In one embodiment, provide gate dielectric protection module 150.This protection module comprises the protection output 156 that is coupled to this unit.In one embodiment, this protection output is coupled to the transistorized body of this risk.The in the situation that of inverter, this protection output is coupled to the body of transistor seconds.For example, this protection output is coupled to the transistorized body of this N-shaped.
In one embodiment, this protection module produces invalid guard signal (inactive protection signal) in this protection output under normal condition (without esd event).This invalid guard signal can work under this normal condition this unit.For example, this invalid guard signal does not affect the normal bias voltage that puts on the transistorized body of this risk.In one embodiment, this invalid guard signal provides normal bias voltage for the transistorized body of this risk.In one embodiment, this invalid guard signal provides the normal bias of 0V or ground connection.Also can provide other normal bias voltage.For example, this normal bias voltage can be depending on the transistorized type of risk.
The in the situation that of esd event, this protection module produces effective guard signal (active protection signal).This effective guard signal provides ESD biasing to the transistorized body of this risk.This ESD biasing reduces the voltage difference (V between the transistorized grid of this risk and substrate
dIFF).For example, this ESD biasing reduces the V between the transistorized grid of this risk and body
dIFF.In one embodiment, this ESD biasing sufficient to guarantee V
dIFFbe less than the puncture voltage (V of the transistorized gate dielectric of this risk
bD).In one embodiment, V
dIFFlower than V
bDat least 5% to 10%.For example,, if V
bDbe about 3.7V, V
dIFFshould be lower than 3.5V.
In one embodiment, this ESD biasing increases underlayer voltage (V
sUB) or this transistorized body.Increase V
sUBmake V
dIFFlower than V
bD.For example, this ESD biasing is about 0.5V to 1V.Other ESD bias voltage biasing V also can be provided
sUB.
As mentioned above, this risk transistor is N-shaped transistor.In other embodiments, this risk transistor can be p-type transistor.For p-type transistor, normal bias is V
dD.For example, this ESD biasing can be lower than V
dDabout 0.5V to 1V.In one embodiment, this protection module is used for the drop-down 0.5V to 1V of the transistorized n trap potential of p-type.Also can use normal bias and the ESD biasing of other type.
In one embodiment, this protection module comprises ESD sensing circuit 170 and biasing circuit 160.This ESD sensing circuit comprises sensing output 176, and it is coupled to the biasing input 164 of this biasing circuit.This biasing circuit comprises biasing output 166, and in one embodiment, biasing output 166 is this protection output.Also can use biasing output and the protection output of other configuration.This protection output provides signal, in order to the transistorized body of this risk of setovering.
The function of this ESD sensing circuit is in order to the generation of sensing esd event.Under normal condition (without esd event), this ESD sensing circuit produces invalid esd event signal in this sensing output.In one embodiment, this invalid esd event signal is logical one signal.On the other hand, when sensing esd event, this ESD sensing circuit produces effective esd event signal in this sensing output.In one embodiment, this effective esd event signal is logic zero signal.Also can use the effective and invalid esd event signal of other type.
This biasing circuit provides ESD biasing to described substrate when starting, to reduce V
dIFF.For example, the biasing circuit of this startup provides ESD biasing to this transistorized body, to reduce V
dIFF.This biasing circuit does not affect the normal work of this unit when stopping using.For example, this inactive biasing circuit provides normal bias to the transistorized body of this risk.
In one embodiment, the invalid esd event signal in this biasing input makes this biasing circuit invalid.This causes this biasing circuit to produce invalid offset signal in this biasing output.This invalid offset signal is provided in this protection output.In one embodiment, this invalid offset signal does not affect the normal bias voltage that puts on the transistorized body of this risk.In one embodiment, this invalid offset signal is logic zero signal or ground connection.This invalid offset signal provides 0V biasing to the transistorized body of this risk.Also can use the invalid offset signal of other type.
Effectively this biasing circuit of esd event signal enabling, produces effective offset signal with the output of setovering in this.In one embodiment, this effective offset signal is provided in this protection output.In one embodiment, this effective offset signal is for this ESD biasing, to reduce V
dIFF.In one embodiment, this ESD biasing is provided in to the transistorized body of this risk.V during this ESD biasing sufficient to guarantee esd event
dIFFlower than V
bD.For example, this ESD biasing can approximate greatly V
dD.Also can provide other ESD bias voltage with biasing V
sUB.
This part of this device also can comprise esd protection circuit (not shown).This esd protection circuit is coupled to this weld pad.Can use various types of esd protection circuits.In certain embodiments, this esd protection circuit can be coupled to those power paths (V for example
dDand V
sS) and weld pad.In other embodiments, this esd protection circuit can be coupled to this second power path (V for example
sS).When esd event occurs, this esd protection circuit provides the current path to ground connection from this weld pad, with the ESD electric current that dissipates.
As mentioned above, this unit comprises a risk transistor.But, should be appreciated that this unit can comprise a more than risk transistor.And, should be appreciated that at this and have in the transistorized device of risk and can there is other unit.Risk transistor has ESD biasing.In one embodiment, can use a biasing circuit for each risk transistor.Those biasing circuits can be shared a common sensing circuit.The transistorized ESD biasing of risk can be identical.Different ESD biasings also can be provided for dissimilar transistor.Also can use biasing and sensing circuit and the ESD biasing of other configuration.
Fig. 2 a shows the embodiment of gate dielectric protection module 150.This protection module comprises protection output 156.In one embodiment, this protection output is coupled to the transistorized body of risk (not shown).For example, this protection output can be coupled to the transistorized body of N-shaped of an inverter, as shown in Figure 1.
In one embodiment, this protection module comprises ESD sensing circuit 170 and biasing circuit 160.In one embodiment, this ESD sensing circuit and biasing circuit coupled in parallel are between first and second power path 102,104.This first power path can be V
dD(operating voltage) and this second power path can be V
sS(ground connection).Also can use the power path of other configuration.This ESD sensing circuit comprises sensing output 176, and it is coupled to the biasing input 164 of this biasing circuit.This biasing circuit comprises biasing output 166, and in one embodiment, biasing output 166 is this protection output.Also can use biasing output and the protection output of other configuration.This protection output provides signal with the transistorized body of this risk of setovering.
The function of this ESD sensing circuit is in order to the generation of sensing esd event.In one embodiment, this sensing circuit comprises the resistor assembly (R of coupled in series between this first and second power path
s) 273 and capacitance component (C
s) 277.This first power path is coupled to R
sand C
sbe coupled to this second power path.In one embodiment, R
sthe first terminal be coupled to this first power path and C
sthe first terminal be coupled to this second power path.R
sand C
sthe second terminal be coupled to each other, form common node 275 or node N
1.Sensing output 176 is coupled to node N
1.Select the RC timeconstantτ of this sensing circuit with sensing esd event.For example, this RC time constant should sensing ESD electric current.In one embodiment, τ is about 1.0-2.0 μ s.τ also can be other value.
In one embodiment, this biasing circuit comprises the first transistor 220 and the transistor seconds 230 of coupled in series between those power paths.This first transistor is p-type MOS transistor (MP
b) and this transistor seconds be N-shaped MOS transistor (MN
b).The first terminal of this first transistor is coupled to this first power path, and the second terminal of this first transistor is coupled to the second terminal of this transistor seconds.The first terminal of this transistor seconds is coupled to this second power path.The body that the body of this first transistor is coupled to this first power path and this transistor seconds is coupled to this second power path.
Those transistorized grids are coupled to biasing input 164 jointly.This biasing input is coupled to the sensing output of this sensing circuit.Biasing output 166 is coupled to this first and second transistorized the second terminal jointly.In one embodiment, this biasing is exported to become or be coupled to this protection module and is exported.
Under normal condition (without esd event), this sensing circuit produces invalid esd event signal in this sensing output.In one embodiment, C
snon-conductive under normal condition.This causes node N
1for example, in logical one or the high potential (current potential of this first power path or be about V
dD).N
1this logical one signal at place is as the invalid esd event signal of this sensing output.This invalid esd event signal is provided in this biasing input.This logical one signal makes MP
bclose (switch off), MN
bopen, thereby this biasing is for example exported, in logical zero or electronegative potential (current potential or the V of this second power path
sS).This logic zero signal is invalid offset signal.This logic zero signal is the transistorized normal bias of this risk, does not affect its work.
When sensing esd event, this sensing circuit produces effective esd event signal in this sensing output.In one embodiment, when esd event occurs, electric current flows through C
s.This causes node N
1for example, in logical zero or the electronegative potential (current potential of this second power path or be about V
sS).N
1this logic zero signal at place is as effective esd event signal of this sensing output.This effective esd event signal is provided in this biasing input.This logic zero signal makes MP
bunlatching, MN
bclose.Along with MP
bopen and MN
bclose, make this biasing output be coupled to this first power path, thereby produce logical one or high potential (for example current potential or the V of this first power path in this biasing output
dD) signal.This logical one signal is effective offset signal, and it provides ESD biasing to the transistorized body of this risk.
This ESD biasing reduces V
dIFF.In one embodiment, this ESD biasing is by increasing V
sUBand reduction V
dIFF.For example, work as MP
bduring unlatching, electric current enters the transistorized body of this risk from this first power rail linear flow.This electric current increases the transistorized V of this risk
sUB.In one embodiment, the current value that flows into the transistorized body of this risk is about 1mA.Also can provide other current value.
Fig. 2 b shows another embodiment of gate dielectric protection module 150.Module described in the similar Fig. 2 a of this protection module.Therefore, common assembly may not remake and describe or describe in detail.As shown in the figure, in protection output 156, provide resistance (R
ext) 240.This resistance can for example be formed by polysilicon.Also can use the resistance of other type.In one embodiment, R
extbe coupled between this protection output and this second power path.For example, R
extbe coupled to this protection output and V
sSbetween.In one embodiment, this protection output is coupled to the transistorized body of risk (not shown).For example, this protection output can be coupled to the transistorized body of N-shaped of inverter, as shown in Figure 1.
Under normal condition, MP
bclose and MN
bopen, make this biasing be output as logical zero.Because this biasing is output as logical zero, so no current flows through R
ext.Due to R
exttwo ends absence of voltage, the normal bias that therefore puts on the transistorized body of this risk is unaffected.On the other hand, when this biasing is output as logical one, the electric current R that flows through
ext.This is at R
exttwo ends produce voltage.This R
extthe voltage at two ends increases V
sUBthereby, reduce V
dIFF.This R
extthe magnitude of voltage at two ends depends on current value and resistance R
extsize.This R
extthe voltage at two ends is by V
dIFFbe down to fully lower than V
bD.In one embodiment, this R
extthe voltage at two ends is about 0.5 to 1V.From MP
bthe electric current of this biasing output be about 1mA.Therefore, R
extbe about 10 to 50k Ω.Also can provide other electric current and resistance.
The part of the embodiment of Fig. 3 a to Fig. 3 d display unit 300.As shown in the figure, this part comprises internal circuit or unit 120.This unit is coupled between first and second power path 102,104.This first power path can be V
dD(operating voltage) and this second power path can be V
sS(ground connection).This unit is coupled to the weld pad 110 of this device.This weld pad for example can be the I/O pad of I/O signal.
In one embodiment, this unit comprises inverter, and it has coupled in series first and second transistor 130,140 between those power paths.Also can use the unit of other type.This first transistor is that p-type transistor and this transistor seconds are N-shaped transistor.The first terminal of this first transistor is coupled to this first power path, and the second terminal of this first transistor is coupled to the second terminal of this transistor seconds.The first terminal of this transistor seconds is coupled to this second power path.The body that the body of this first transistor is coupled to this first power path and this transistor seconds is coupled to this second power path.The input 134 of this inverter is coupled to those transistorized grids jointly.The output 326 of this inverter is coupled to those transistorized the second terminals jointly.
As shown in the figure, this weld pad is coupled to the input of this inverter.This output is coupled to the internal circuit (not shown) of this device.In other embodiments, this weld pad is coupled to the output of this inverter.The input of this inverter is coupled to the internal circuit (not shown) of this device.
In one embodiment, the body of this transistor seconds is coupled to the output of gate dielectric protection module, as described in Fig. 1 and Fig. 2 a to Fig. 2 b.When detecting esd event, starting this protection module provides ESD biasing with the body to this transistor seconds.This reduces V
dIFFto guarantee that it is lower than V
bD.
In one embodiment, provide esd protection circuit 390.This esd protection circuit is coupled to this weld pad.Can use dissimilar esd protection circuit.In certain embodiments, this esd protection circuit can be coupled to those power paths (V for example
dDand V
sS) and weld pad.In other embodiments, this esd protection circuit can be coupled to this second power path (V for example
sS).When esd event occurs, this esd protection circuit provides the electric current pad to ground connection from this weld pad, with the ESD electric current that dissipates.
As shown in Figure 3 a, this esd protection circuit comprises the N-shaped MOS transistor MN of grounded-grid
p350, its drain terminal D
pbe coupled to this weld pad, source S
pand grid G
pjointly be coupled to V
sS.Transistor MN
pin substrate, form parasitic bipolar junction transistor (bipolar junction transistor; BJT).This BJT is NPN BJT, by D
p, substrate (P trap) and S
pknot (junction) form.D for example
p-substrate interface forms the first p-n junction and the S of this NPN BJT
p-substrate forms the second p-n junction of this NPN BJT.
Under normal operating conditions (for example, without esd event), because first and second p-n junction of this BJT is reverse biased, so this earth grid is guaranteed MN
pclose.The signal of this weld pad is not subject to MN
pthe impact of closing, thus this unit can be worked under normal condition.Esd event increases D
p(V
dP) voltage, electric current is flow through, thereby increases substrate electric potential (for example base stage of parasitic BJT or V
b).Work as V
bwhen enough high, parasitic BJT opens.For example, work as V
bsurpass trigger voltage V
tPtime, MN
popen.It causes MN
pavalanche breakdown, thus form from this weld pad to V
sScurrent path 316 with dissipation ESD electric current.
Fig. 3 b shows another embodiment of esd protection circuit 390.The similar esd protection circuit as described in Fig. 3 a of this protective circuit.Therefore, similarly assembly may not described or describe in detail.This esd protection circuit comprises that coupled in parallel is in this weld pad 110 and the second power path or ground connection (V
sS) between first grid ground connection N-shaped MOS transistor (MN
p) 350 and second grid ground connection N-shaped MOS transistor (MN
s) 360.
In one embodiment, MN
pcomprise the drain terminal D that is coupled to this weld pad
pand be jointly coupled to V
sSsource S
pand grid G
p.Similarly, MN
sdrain terminal D
pbe coupled to this weld pad, source S
sand grid G
sjointly be coupled to V
sS.Resistance R
sec370 are coupled to MN
pand MN
sdrain terminal between.This resistance for example can be formed by polysilicon.In one embodiment, this resistance is formed by silication silicon not.
Under normal operating conditions (for example, without esd event), those earth grids are guaranteed MN
pand MN
sclose.This is because first and second p-n junction of BJT is reverse biased.Due to MN
pand MN
sclose, the signal of this weld pad is unaffected, thereby can make this cell operation under normal condition.
In the situation that there is esd event, D
pvoltage (V
dP) and D
svoltage (V
dS) increase, electric current is flow through, thereby increase substrate electric potential (for example base stage of parasitic BJT or V
bPand V
bS).Work as V
bPand V
bSwhen enough high, parasitic those BJT open.For example, work as V
bPand V
bSsurpass MN
pand MN
strigger voltage V
ttime, those transistors are opened.It causes those transistor avalanche breakdown, forms from this weld pad to V
sSfirst and second current path 316 and 318 with dissipation ESD electric current.In this second current path, flow through R
secelectric current produce voltage drop V
rsec.This voltage drop by the transistorized input voltage clamper of this risk in V
rsec.
Please refer to Fig. 3 c, it shows the alternate embodiment of esd protection circuit 390.This esd protection circuit is coupled to weld pad 110 and first and second power path 102,104.This esd protection circuit comprises by the first diode (D
1) the 320 and second diode (D
2) 330 diode pairs 314 that form.This first diode (D
1) the 320 and second diode (D
2) 330 coupled in series are between those power paths.In one embodiment, D
1negative electrode C
1be coupled to this first power path (V
dD) and D
2anode A
2be coupled to this second power path (V
sS).D
1anode A
1and D
2negative electrode C
2jointly be coupled to this weld pad.This esd protection circuit is for example the esd protection circuit based on path.
In one embodiment, provide clamp circuit 375.This clamp circuit is coupled between this first and second power path.Under normal condition, this clamp circuit is invalid.When being started by esd event, between those power paths, form current path.This clamp current can be controlled by ESD circuits for triggering.For example, these circuits for triggering produce invalid triggering output under normal condition, and when esd event occurs, produce effective trigger output signal.
In one embodiment, this clamp circuit comprises clamp transistor, for example N-shaped MOS transistor.When esd event occurs, by circuits for triggering, start or open this clamp transistor.Open this clamp transistor and form current path between those power paths.For example, these circuits for triggering can be the sensing circuit of this protection module, as described in Fig. 2 a to Fig. 2 b.Also can provide the circuits for triggering of other type.
Under normal operating conditions, those diodes are reverse biased.In addition, this clamp circuit is invalid.Due to those diode reverse biased, the signal of this weld pad is unaffected, thereby this unit can be operated under normal condition.
In one embodiment, esd event makes D
1or D
2forward bias, is formed to the wherein current path of a power path of those power paths.For negative pulse esd event, D
2forward bias and D
1reverse bias.It is formed to V
sScurrent path 327, with the ESD electric current that dissipates.For positive pulse esd event, D
2reverse bias and D
1forward bias.In addition, because this clamp circuit during esd event is activated, therefore between those power paths, form the current path through this clamp circuit.Form through V like this
dDto V
sScurrent path 326, with the ESD electric current that dissipates.
Fig. 3 d shows another embodiment of esd protection circuit 390.The esd protection circuit based on path of the similar Fig. 3 c of this esd protection circuit.Therefore, common assembly may not described or describe in detail.This esd protection circuit is coupled to this first and second power path 102,104 and weld pad 110.In one embodiment, this esd protection circuit comprises first and second diode pair 314,316.This first and second diode pair coupled in parallel is between this first and second power path.This first and second diode pair is also coupled to this weld pad 110.
In one embodiment, this first diode pair has the first diode (D of coupled in series between those power paths
1) the 320 and second diode (D
2) 330.D
1negative electrode C
1be coupled to this first power path (V
dD) and D
2anode A
2be coupled to this second power path (V
sS).D
1anode A
1and D
2negative electrode C
2jointly be coupled to this weld pad.Similarly, this second diode pair has the first diode (D of coupled in series between those power paths
3) the 340 and second diode (D
4) 350.D
3negative electrode C
3be coupled to this first power path (V
dD) and D
4anode A
4be coupled to this second power path (V
sS).D
3anode A
3and D
4negative electrode C
4jointly be coupled to this weld pad.Resistance (R
sec) 370 be coupled to D
1and D
2common terminal and D
3and D
4common terminal between.This resistance for example can be formed by polysilicon.In one embodiment, this resistance can be formed by non-silication silicon.
In one embodiment, provide clamp circuit 375.This clamp circuit is coupled between this first and second power path.Under normal condition, this clamp circuit is invalid.When this clamper is started by esd event, between those power paths, form current path.This clamp circuit can be controlled by ESD circuits for triggering.For example, these circuits for triggering produce invalid triggering output under normal condition, and when esd event occurs, produce effective trigger output signal.
Under normal operating conditions, the diode of this esd protection circuit is reverse biased.In addition, this clamp circuit is invalid.Because those diodes are reverse biased, the signal of this weld pad is unaffected, thereby can make this cell operation under normal condition.
In one embodiment, esd event makes D
1and D
3or D
2and D
4forward bias, is formed to the wherein current path of a power path of those power paths.For negative pulse esd event, D
2and D
4forward bias and D
1and D
3reverse bias.It is formed to V
sScurrent path 327 and 329 with dissipation ESD electric current.For positive pulse esd event, D
2and D
4reverse bias and D
1and D
3forward bias.And, because this clamp circuit during esd event is activated, therefore between those power paths, form the current path through this clamp circuit.Form through V like this
dDto V
sSfirst and second current path 326,328, with the ESD electric current that dissipates.In this second current path, R flows through
secelectric current produce voltage drop V
rsec.This voltage drop by the transistorized input voltage clamper of this risk in V
rsec.
The present invention can other concrete form implements and does not deviate from spirit of the present invention or essential characteristic.Therefore, above-described embodiment is only illustrative, and unrestricted the present invention.Scope of the present invention is represented by claims, but not above-mentioned explanation is all intended to be contained in this in the meaning being equal to of claim and the whole changes in scope.
Claims (20)
1. a device, comprising:
Transistor, has the grid being positioned on substrate, and this grid comprises the gate electrode that is positioned at gate dielectric top;
Gate dielectric protection module, is coupled to this transistor, and wherein, this gate dielectric protection module provides protection biasing when starting, with by the voltage difference V between this grid and substrate
dIFFbe brought down below the puncture voltage V of this gate dielectric
bD.
2. device as claimed in claim 1, wherein:
This transistor comprises the transistor body that is arranged in this substrate; And
This gate dielectric protection module is coupled to this transistor body.
3. device as claimed in claim 2, wherein, this gate dielectric protection module provides this protection biasing to this transistor body, to increase underlayer voltage V
sUBthereby, by V
dIFFbe brought down below V
bDat least 5%.
4. device as claimed in claim 1, wherein, this gate dielectric protection module provides this protection biasing, to increase underlayer voltage V
sUBthereby, by V
dIFFbe brought down below V
bD.
5. device as claimed in claim 1, wherein, this gate dielectric protection module provides this protection biasing, with by V
dIFFbe brought down below V
bDat least 5%.
6. device as claimed in claim 1, wherein, this gate protection module comprises:
Sensing circuit, with detection electrostatic electric discharge event; And
Biasing circuit, is coupled to this transistor,
Wherein, when detecting electrostatic discharge event, this sensing circuit starts this biasing circuit, so that this protection biasing to be provided.
7. device as claimed in claim 6, wherein, this sensing circuit comprises:
Sensing resistor, and sense capacitance coupled in series is between first and second path, and wherein, this sensing resistor is coupled to this first path and this sense capacitance is coupled to this second path; And
Sensing circuit output, be coupled to this biasing circuit, this sensing circuit output is located between the common terminal of this sensing resistor and sense capacitance, wherein, when not detecting electrostatic discharge event, this sensing circuit produces invalid sensing output signal in this sensing circuit output, and when detecting electrostatic discharge event, this sensing circuit produces effective sensing output signal to start this biasing circuit.
8. device as claimed in claim 7, wherein, this biasing circuit comprises:
First and second transistor, coupled in series is between this first and second path, and the first terminal that the first terminal of this first transistor is coupled to this first path and this transistor seconds is coupled to this second path;
Biasing input, is coupled to this first and second transistorized grid; And
Biasing output, is coupled to this first and second transistorized common the second terminal.
9. device as claimed in claim 8, wherein:
This first path is high power path;
This second path is ground connection path;
This first bias transistor is p-type transistor;
This second bias transistor is N-shaped transistor; And
When starting this protective circuit, open this first bias transistor and close this second bias transistor, so that electric current flows to this biasing output from this first path through this first transistor.
10. device as claimed in claim 9, wherein, this transistorized body of this current direction of this biasing output, to produce this protection biasing, thus reduction V
dIFF.
11. devices as claimed in claim 9, comprising:
Biasing output resistance, is coupled to this biasing output and this second path, and wherein, this electric current of this biasing output this resistance of flowing through, setovers to produce this protection, thus reduction V
dIFF.
12. devices as claimed in claim 6, wherein:
This transistor is the part that is coupled to the I/O unit of I/O pad;
This I/O unit comprises I/O transistor, and this this transistor series of I/O transistor AND gate is coupled between first and second path, and the transistorized the first terminal of this I/O is coupled to this first path and this transistorized the first terminal is coupled to this second path;
The input of I/O unit couples this I/O pad to this I/O transistor and this transistorized grid; And
The output of I/O unit is coupled to this I/O transistor and this transistorized common the second terminal.
13. devices as claimed in claim 12, wherein:
This I/O transistor is p-type transistor;
This transistor is N-shaped transistor;
This first path is high power path; And
This second path is ground connection path.
14. devices as claimed in claim 6, comprise the ESD protection circuit based on path, and it is coupled to this transistor.
15. devices as claimed in claim 6, comprise the ESD protection circuit based on weld pad, and it is coupled to this transistor.
16. 1 kinds of methods that form device, comprising:
Form transistor, it has the grid being positioned on substrate, and this grid comprises the gate electrode that is positioned at gate dielectric top; And
Formation is coupled to this transistorized gate dielectric protection module, and wherein, this gate dielectric protection module provides protection biasing when starting, with by the voltage difference V between this grid and substrate
dIFFbe brought down below the puncture voltage V of this gate dielectric
bD.
17. methods as claimed in claim 16, wherein, this transistor comprises the transistor body that is arranged in this substrate; And comprise and couple this gate dielectric protection module to this transistor body.
18. methods as claimed in claim 17, wherein, this gate dielectric protection module provides this protection biasing to this transistor body, to increase underlayer voltage V
sUBthereby, by V
dIFFbe brought down below V
bDat least 5%.
19. methods as claimed in claim 16, wherein, this gate dielectric protection module provides this protection biasing, to increase underlayer voltage V
sUBthereby, by V
dIFFbe brought down below V
bD.
20. 1 kinds of methods of protecting gate dielectric, comprising:
Risk transistor is provided;
Provide and be coupled to the transistorized protection module of this risk;
Start this protection module so that protection biasing to be provided, thereby by the voltage difference V between the transistorized grid of this risk and substrate
dIFFbe brought down below the puncture voltage V of the transistorized gate dielectric of this risk
bD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310189992.2A CN104183595B (en) | 2013-05-21 | 2013-05-21 | Gate dielectric layer protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310189992.2A CN104183595B (en) | 2013-05-21 | 2013-05-21 | Gate dielectric layer protection |
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| Publication Number | Publication Date |
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| CN104183595B CN104183595B (en) | 2017-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310189992.2A Expired - Fee Related CN104183595B (en) | 2013-05-21 | 2013-05-21 | Gate dielectric layer protection |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297580A (en) * | 1999-01-19 | 2001-05-30 | 精工爱普生株式会社 | Circuit for protection against static electricity, and semiconductor integrated circuit using same |
| US6411480B1 (en) * | 1999-03-01 | 2002-06-25 | International Business Machines Corporation | Substrate pumped ESD network with trench structure |
| US6873017B2 (en) * | 2003-05-14 | 2005-03-29 | Fairchild Semiconductor Corporation | ESD protection for semiconductor products |
| US7579881B2 (en) * | 2007-11-14 | 2009-08-25 | Infineon Technologies Ag | Write driver circuit |
| US7719813B2 (en) * | 2005-10-20 | 2010-05-18 | United Microelectronics Corp. | Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith |
-
2013
- 2013-05-21 CN CN201310189992.2A patent/CN104183595B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297580A (en) * | 1999-01-19 | 2001-05-30 | 精工爱普生株式会社 | Circuit for protection against static electricity, and semiconductor integrated circuit using same |
| US6411480B1 (en) * | 1999-03-01 | 2002-06-25 | International Business Machines Corporation | Substrate pumped ESD network with trench structure |
| US6873017B2 (en) * | 2003-05-14 | 2005-03-29 | Fairchild Semiconductor Corporation | ESD protection for semiconductor products |
| US7719813B2 (en) * | 2005-10-20 | 2010-05-18 | United Microelectronics Corp. | Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith |
| US7579881B2 (en) * | 2007-11-14 | 2009-08-25 | Infineon Technologies Ag | Write driver circuit |
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| CN104183595B (en) | 2017-05-24 |
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