CN104183575A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104183575A CN104183575A CN201310190073.7A CN201310190073A CN104183575A CN 104183575 A CN104183575 A CN 104183575A CN 201310190073 A CN201310190073 A CN 201310190073A CN 104183575 A CN104183575 A CN 104183575A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 157
- 239000002184 metal Substances 0.000 claims abstract description 157
- 238000000034 method Methods 0.000 claims abstract description 113
- 239000000463 material Substances 0.000 claims abstract description 95
- 239000004020 conductor Substances 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 33
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 483
- 238000000059 patterning Methods 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000011241 protective layer Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 238000002360 preparation method Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
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- 230000008021 deposition Effects 0.000 abstract description 18
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- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
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- 238000002230 thermal chemical vapour deposition Methods 0.000 description 4
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910004541 SiN Inorganic materials 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor device and a manufacturing method thereof. The device comprises a semiconductor substrate, a first dielectric layer and a second dielectric layer located on the semiconductor substrate, a high-resistance conductive material layer located at the interface between the first dielectric layer and the second dielectric layer, and a metal interconnection structure connected onto the high-resistance conductive material layer. A TiN resistor is selected to replace a polysilicon resistor in the prior art, and the TiN is a good selection from the aspects of resistivity and material performance. Through deposition, photoetching, etching and other simple technology methods, the TiN resistor is introduced in the semiconductor device, and various difficulties exsiting in the prior art can be well solved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
To not provided to the situation of semiconductor device by the protection component of the interference such as static for the protection of internal circuit; it is generally the resistive element that is provided for Limited Current between protection component and internal circuit; thereby prevent that overcurrent from flowing to internal circuit; the polysilicon resistance (Poly resistor) that resistive element is made up of polysilicon conventionally; or the diffusion resistance being formed by diffusion layer (diffusion resistor); in the situation that using diffused layer resistance; can be integrated with the element of protection, to reduce area occupied.
Manufacture field at integrated circuit, along with constantly dwindling of MOS transistor, it is various because the second-order effect that the physics limit of device is brought is inevitable, the scaled difficulty that becomes of characteristic size of device, easily there is the electric leakage problem from grid to substrate in MOS transistor device and circuit thereof the field of manufacturing wherein.The solution of current technique is the method that adopts high-K gate material and metal gate.
Along with the extensive use of high-K gate material and metal gate technique, performance of semiconductor device is greatly improved, but because hafnium used in high-K gate material and metal gate process is owing to having low resistance coefficient, can not be used as resistance, same non-self-aligned silicide diffusion (Non-salicide diffusion) can not be used as diffusion resistance owing to having too high resistivity (higher resistivity).
In the preparation technology of semiconductor device, in the process node particularly constantly dwindling at device size, the problems referred to above become a difficult problem of needing solution badly.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the first dielectric layer and the second dielectric layer in described Semiconductor substrate;
High resistance conductive material layer, the interface between described the first dielectric layer and the second dielectric layer;
And be connected to the metal interconnect structure of described high resistance conductive material layer.
As preferably, the sheet resistance of described high resistance conductive material layer is 200-1000mohm/sq.
As preferably, described high resistance conductive material layer is TiN or TaN.
As preferably, described metal interconnect structure comprises the first metal throuth hole V0 that is arranged in described the first dielectric layer and the second metal valley M1 that is arranged in described the second dielectric layer.
As preferably, described metal interconnect structure comprises the first metal valley M0 that is arranged in described the second dielectric layer.
As preferably, described metal interconnect structure is connected described high resistance conductive material layer with contact hole CCT by the first metal valley M0 with the active area in described Semiconductor substrate.
As preferably, described the first metal valley M0 is positioned on the described high resistance conductive material layer of part.
As preferably, described the second metal valley M1 is positioned on the described high resistance conductive material layer of part.
As preferably, also comprise the metal gates that is arranged in described the first dielectric layer.
As preferably, described device also comprises the TiN cover layer that is positioned at described metal gates top, and described TiN cover layer and described TiN resistance form in same operation.
The present invention also provides a kind of preparation method of semiconductor device, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, deposit the first dielectric layer;
On described the first dielectric layer, form high resistance conductive material layer;
On described the first dielectric layer and described high resistance conductive material layer, deposit the second dielectric layer;
Form the metal interconnect structure being electrically connected with described high resistance conductive material layer.
As preferably, the sheet resistance of described high resistance conductive material layer is 200-1000mohm/sq.
As preferably, described high resistance conductive material layer is TIN or TaN.
As preferably, described method is also included in the step that forms the first metal valley M0 and contact hole CCT in described Semiconductor substrate, and described metal interconnect structure is connected described high resistance conductive material layer with contact hole CCT by the first metal valley M0 with the active area in described Semiconductor substrate.
As preferably, the method that forms described high resistance conductive material layer is:
In described Semiconductor substrate, form etching stopping layer;
On described etching stopping layer, deposit described the first dielectric layer;
On described the first dielectric layer, deposit high resistance electric conducting material;
TiN material layer described in patterning, to remove the described high resistance electric conducting material of part, forms described high resistance conductive material layer.
As preferably, the method for high resistance electric conducting material is described in patterning:
On described high resistance electric conducting material, form mask layer, described mask layer is the combination of photoresist or photoresist and sacrificial material layer, bottom anti-reflection layer;
Mask layer described in patterning;
Taking described mask layer as high resistance electric conducting material described in mask etch;
Remove described mask layer.
As preferably, the method that forms described metal interconnect structure comprises the following steps:
On described the second dielectric layer, deposit protective layer, memory layer and hard mask layer;
Etching stopping layer, described the first dielectric layer, described the second dielectric layer described in patterning, in described the first dielectric layer, form through hole, to expose described the first metal valley M0, in described the second dielectric layer, form groove, with high resistance conductive material layer described in exposed portions serve;
Select electric conducting material to fill described through hole and described groove, form respectively the first metal throuth hole V0 and the second metal valley M1, to form electrical connection;
Remove described protective layer, memory layer and hard mask layer.
As preferably, the silicon nitride material that described etching stopping layer is carbon containing or SiN layer;
Described the first dielectric layer is oxide skin(coating) or low-K material layer;
Described the second dielectric layer is low-K material layer;
Described protective layer is oxide skin(coating);
Described memory layer is TiN layer;
Described sacrificial material layer is oxide skin(coating).
As preferably, described method comprises:
In described the first dielectric layer, form metal gate structure;
On described the first dielectric layer, deposit high resistance electric conducting material and sacrificial material layer;
High resistance electric conducting material and described sacrificial material layer described in patterning form high resistance electric conducting material cover layer on described metal gate structure, form high resistance conductive material layer simultaneously;
Deposit described the second dielectric layer, and form the first metal valley M0 in described the second dielectric layer, wherein said the first metal valley M0 is positioned on the described high resistance conductive material layer of part.
As preferably, the method that forms described metal interconnect structure is:
On described the second dielectric layer, deposit hard mask layer, the second sacrificial material layer;
The second sacrificial material layer and described hard mask layer described in patterning;
Taking described hard mask layer as the second dielectric layer described in mask etch, to form groove in described the second dielectric layer, high resistance conductive material layer described in exposed portions serve;
Select electric conducting material to fill described groove, to form described the first metal valley M0.
As preferably, described hard mask layer is TiN material layer.
As preferably, described method is further comprising the steps of:
Form stressor layers in described metal gate structure both sides;
In the technique that forms metal interconnect structure, in described stressor layers, form electrical connection, comprise following sub-step:
On described the second dielectric layer, deposit hard mask layer, the second sacrificial material layer;
Hard mask layer described in patterning, to form contact hole in described hard mask layer, described contact hole is positioned at described stressor layers top;
Hard mask layer described in patterning, to form groove in described hard mask layer, described groove is positioned at described metal gate structure top;
With the second dielectric layer described in described hard mask layer etching, to form contact hole and groove in described the second dielectric layer, expose described stressor layers and described metal gate structure;
Deposits conductive material, fills described contact hole and groove, to form contact hole CCT and described electrical connection.
As preferably, before forming described contact hole CCT, be also included in the step that forms self-aligned silicide in described stressor layers.
In the present invention, select TiN resistance to substitute polysilicon resistance in prior art, all extraordinary selection from resistivity and material property TiN, the present invention is by the simple process such as deposition, photoetching, etching, in semiconductor device, introduce TiN resistance, well solved various difficult problems that exist in prior art.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-h is the generalized section that the first execution mode of the present invention is prepared described semiconductor device;
Fig. 2 a-d is the generalized section that the second execution mode of the present invention is prepared described semiconductor device;
Fig. 3 a-m is the generalized section that the third execution mode of the present invention is prepared described semiconductor device;
Fig. 4 is the process chart of preparing described semiconductor device in one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed description be proposed in following description, so that the method for monitoring probe mark size of the present invention to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skill in the art.
The invention provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the first dielectric layer and the second dielectric layer in described Semiconductor substrate;
High resistance conductive material layer, the interface between described the first dielectric layer and the second dielectric layer;
And be connected to the metal interconnect structure of described high resistance conductive material layer.
Wherein, the sheet resistance of described high resistance conductive material layer is 200-1000mohm/sq, and described high resistance conductive material layer is TiN or TaN particularly.
The conductive material layer of high resistance described in the following examples all describes as an example of TiN example in the present invention, but it should be noted that and be not limited to described TiN material, the high resistance conductive material layer that sheet resistance is 200-1000mohm/sq all can be for the present invention.
As preferably, described metal interconnect structure comprises the first metal throuth hole V0 that is arranged in described the first dielectric layer and the second metal valley M1 that is arranged in described the second dielectric layer, described the second metal valley M1 is positioned on the described TiN resistance of part, and described metal interconnect structure is connected described TiN resistance with contact hole CCT by the first metal valley M0 with the active area in described Semiconductor substrate.
Or described metal interconnect structure comprises the first metal valley M0 that is arranged in described the second dielectric layer, described the first metal valley M0 is positioned on the described TiN resistance of part, described device also comprises the TiN cover layer that is positioned at described metal gates top, and described TiN cover layer and described TiN resistance form in same operation.
Below the processing method in an embodiment of the present invention is described further:
First with reference to Fig. 1 a-1h, the first execution mode of the present invention is described in detail:
First, as shown in Figure 1a, first provide Semiconductor substrate, in described Semiconductor substrate, form metal gate structure, and form electrical connection on described metal gate structure;
Below this process is described further, in an embodiment of the present invention, first Semiconductor substrate is provided, and described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
In described Semiconductor substrate, can be formed with doped region and/or isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
In described Semiconductor substrate, form metal gate structure, the formation method of described metal gates can be that first grid technique (gate first) or rear grid technique (gate last) are not limited to a certain method, select rear grid technique to prepare described metal gate structure in order to improve the performance of device in one embodiment of this invention, but be not limited only to the method, particularly:
In described Semiconductor substrate, form dummy gate, first in described Semiconductor substrate, form gate oxide level, as preferably, described oxide skin(coating) is SiO
2layer, described SiO
2layer forms by rapid thermal oxidation process (RTO), and its thickness is 8-50 dust, but is not limited to this thickness.
Then deposition of gate material layer in described gate oxide level, described grid material (, has from every cubic centimetre about 1 × 10 including but not limited to polysilicon and the polysilicon-Ge alloy material of silicon, polysilicon, doping
18to about 1 × 10
22the doping content of individual foreign atom) and polysilicon metal silicide (polycide) material (polysilicon/metal silicide laminated material of doping).
Similarly, also can adopt any one formation previous materials of several methods.Limiting examples comprises self-aligned metal silicate method.Conventionally, described grid material comprises having the polycrystalline silicon material of thickness from about 50 dusts to the doping of about 2000 dusts.
The formation method of described polysilicon gate material can be selected low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions that form described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100～200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700～750 degrees Celsius; Reaction chamber internal pressure can be 250～350mTorr, as 300mTorr; In described reacting gas, also can comprise buffer gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5～20 liters/min (slm), as 8slm, 10slm or 15slm.
Then described gate material layers is carried out to etching, to obtain dummy gate, particularly, in an embodiment of the present invention, first in described gate material layers, form the photoresist layer of patterning, described photoresist layer has defined the shape of described dummy gate and the size of critical size, taking described photoresist layer as gate material layers described in mask etch and gate oxide level, form dummy gate, then remove described photoresist layer, the removal method of described photoresist layer can be selected oxidation ashing method, can also select additive method conventional in this area, do not repeat them here.
On described dummy gate, form skew sidewall, particularly, the material layer of conformal deposited on described substrate (conformal deposition) skew sidewall, to form the identical or roughly the same cover layer of thickness on described dummy gate, remove in etching after the material layer of the skew sidewall on substrate and dummy gate horizontal plane, form skew sidewall, skew sidewall is selected oxide, preferential oxidation silicon, described oxide forms by the method for ald (ALD).
After forming described skew sidewall, carry out the step that LDD injects, the method for described formation LDD can be ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will form, and the device forming is nmos device, and the foreign ion mixing in LDD injection technology is a kind of or combination in phosphorus, arsenic, antimony, bismuth; If the device forming is PMOS device, the foreign ion injecting is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.
Then at described grid both sides source-drain area growth stress layer, in CMOS transistor, conventionally on nmos pass transistor, form the stressor layers with tension stress, on PMOS transistor, form the stressor layers with compression, the performance of cmos device can by by described action of pulling stress in NMOS, action of compressive stress improves in PMOS.In prior art, in nmos pass transistor, conventionally select SiC as tension stress layer, in PMOS transistor, conventionally select SiGe as compressive stress layer.
As preferably, the described SiC that grows is during as tension stress layer, can epitaxial growth on described substrate, after Implantation, forming lifting source leaks, in the time forming described SiGe layer, conventionally in described substrate, form groove, then in described groove, deposition forms SiGe layer.More preferably, in described substrate, form " ∑ " connected in star.
Then on described dummy gate, form clearance wall, described grid gap wall can be SiO
2, in SiN, SiOCN a kind of or they constitute.Optimize execution mode for one as the present embodiment, described grid gap wall is that silica, silicon nitride form jointly, and concrete technology is: in Semiconductor substrate, form silicon oxide layer, silicon nitride layer, then adopt engraving method to form grid gap wall.The thickness of described grid gap wall is 5-50nm.
In described Semiconductor substrate, deposit contact etch stop layer (CESL), described contact etch stop layer (CESL) can comprise one or more in SiCN, SiN, SiC, SiOF, SiON, in one embodiment of this invention, preferably on described substrate, form layer of sin, then on described SiN, continue deposition one deck SiC, to form described contact etch stop layer, wherein said contact etch stop layer is not limited to above-mentioned a kind of combination.
Remove described dummy gate, select in the present invention dry etching or wet etching to remove described dummy gate, deposit the steps such as high k dielectric layer, metal gates forming in being also included in groove after described groove.
Particularly, in described groove, form gate dielectric, preferably high k dielectric layer forms described gate dielectric, for example, be used in Hf0
2middlely introduce the elements such as Si, Al, N, La, Ta and optimize hafnium that the ratio of each element obtains etc.
The method that forms described high k dielectric layer can be physical gas-phase deposition or atom layer deposition process.In an embodiment of the present invention, form HfAlON gate dielectric in groove, its thickness is 15 to 60 dusts.
Finally form metal gates, described metal gates forms by the multiple film storehouses of deposition, and described film comprises workfunction layers, barrier layer and conductive layer.Described barrier layer comprises TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or above-mentioned combination.Described deposited barrier layer method limiting examples comprises chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD).
Then on described metal gate structure and stressor layers SiGe layer, form electrical connection, particularly, on described metal gate structure, form the first metal layer M0, on described stressor layers SiGe layer, form contact hole CCT, to form electrical connection, the formation method of described the first metal layer M0 and described contact hole CCT is: on described metal gate structure, deposit successively the first interlayer dielectric layer, stop-layer and the second interlayer dielectric layer, then dielectric layer described in patterning, in described the first interlayer dielectric layer, form contact hole, the second interlayer dielectric layer described in patterning, form groove, by double patterning to form groove and contact hole, then select electric conducting material to fill described groove and contact hole, on described metal gate structure, form the first metal layer M0, on described SiGe layer, form contact hole CCT.
Wherein, electric conducting material can pass through low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and ald (ALD) or the formation of other advanced deposition technique.Preferably, electric conducting material is tungsten material.In another embodiment, electric conducting material can be cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and the electric conducting material that contains tungsten or its combination.
As preferably, in one embodiment, in order to reduce contact resistance, before filling described electric conducting material, also further comprise and form self-aligned silicide formation technique (salicide), particularly, at semiconductor substrate surface jet-plating metallization layer, for example nickel metal layer, then annealing (RTA) technique is rapidly heated, make metal level become metal silicide layer with the partial reaction that grid and regions and source/drain contact, complete self-alignment metal silicide technique (salicide).
The formation in metal silicified layer (silicide) region, first depositing metal layers, it can comprise the material of nickel (nickel), cobalt (cobalt) and platinum (platinum) or its combination.Then heated substrate, causes metal level and the silicon layer generation silicification under it, metal silication layer region thereby formation.Then use erodable metal level, but the etchant in unlikely attack metal disilicide layer region, so that unreacted metal level is removed.
After forming the first metal layer M0, carry out a planarisation step, can realize surperficial planarization with flattening method conventional in field of semiconductor manufacture.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
With reference to Fig. 1 b, deposition etch stop-layer 101, the first dielectric layer 102 and TiN material layer 103 in described Semiconductor substrate;
Particularly, in an embodiment of the present invention, first in described Semiconductor substrate, deposit contact etch stop layer (CESL), described contact etch stop layer (CESL) can comprise one or more in SiCN, SiN, SiC, SiOF, SiON, NDC, its thickness is 100-300 dust, in one embodiment of this invention, preferably on described substrate, form layer of sin, its thickness is 220 dusts, to form described contact etch stop layer, wherein said contact etch stop layer is only exemplary.
Then deposit the first dielectric layer 102 at described etching stopping layer 101, described the first dielectric layer 102 is for can be silicon oxide layer, comprise the material layer that has doping or unadulterated silica that utilizes thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process to form, silex glass (USG), phosphorosilicate glass (PSG) or the boron-phosphorosilicate glass (BPSG) of for example undoped.In addition, the first dielectric layer 102 can also be low K or ultralow K dielectric material.The thickness of described the first dielectric layer 102 is 300-500 dust, is preferably 380-420 dust.
Then depositing TiN material layer 103 on described the first dielectric layer 102, wherein, described TiN material layer 103.
With reference to Fig. 1 c, on described TiN material layer 103, form the mask layer 104 of patterning, the mask layer 104 of wherein said patterning has defined size and the position of described TiN resistance, the mask layer of described patterning is photoresist layer in the present invention, be preferably DUO248 material layer, particularly, on described TiN material layer 103, form DUO248 material layer, then carry out photoetching, form the mask layer 104 of patterning.
With reference to Fig. 1 d, patterning TiN material layer 103, particularly, taking the mask layer 104 of described patterning as TiN material layer 103 described in mask etch, stops on described the first dielectric layer 102, to form the pattern of TiN resistance on described the first dielectric layer 102.
In an embodiment, select TiN material layer 103 described in wet etching, in order to improve the etching selectivity of described TiN material layer 103 and described the first dielectric layer 102, select NH in the present invention
4oH:H
2o
2: H
2tiN material layer 103 described in the etching solution etching of O=1:1-2:3-8, can etching the first dielectric layer 102 in the time removing TiN material layer 103 shown in part, as preferably, selects NH
4oH:H
2o
2: H
2the etching solution of O=1:1:5 carries out etching, further improves etching selectivity, improves etch effect.
With reference to Fig. 1 e, remove the mask layer 104 of described patterning, select in the present invention ashing method to remove described patterned mask layer 104, but be not limited to this example, those skilled in the art can select conventional method to realize described object, do not repeat them here.
With reference to Fig. 1 f; deposit the second dielectric layer 105, protective layer 106, memory layer 107 and hard mask layer 108; particularly; in described Semiconductor substrate, deposit the second dielectric layer 105; to cover described TiN resistance; wherein said the second dielectric layer 105 is low K or ultralow K material layer; its thickness is 1000-2000 dust; the preparation method of described the second dielectric layer 105 has following two kinds: one is plasma chemical vapor deposition (CVD); another kind is whirl coating (Spin-On Deposition, SOD).Preferred spin coated (SOD) method in the present invention, nano-porous film prepared by spin coated (SOD) method has the advantages such as structure is controlled, good stability, and there is withstand voltage height, the clearance filling capability that the adhesiveness having had with silicon is become reconciled, better with the compatibility of semiconductor integrated circuit chip technique.
As further preferred, forming after described porous low-k materials, can also further carry out suitable plasma treatment to described porous low-k materials, described plasma treatment not only can play the effect of cleaning, and can produce many dangling bonds and improve its chemism on the surface of described material, and plasma surface treatment can make the open pore closure of low k film surface of preparation, reduce water absorption, prevent copper scattering and extraneous pollution.
On described the second dielectric layer 105, continue deposition protective layer 106, described protective layer is oxide skin(coating), and the TiN resistance that is arranged in below to protect is not damaged at etching process, has in the present invention preferred SiO
2material layer, its thickness is 100-300 dust, its formation method can be selected this area common method, does not repeat them here.
Deposition memory layer 107 on described protective layer 106; described memory layer 107 is preferably TiN layer; its thickness is 200-500 dust; on described memory layer 107, deposit hard mask layer 108; described hard mask layer 108 is preferably oxide skin(coating); its thickness is 50-500 dust, at of the present invention one preferred SiO in execution mode particularly
2material layer is as hard mask layer, its deposition process can be chemical vapour deposition technique (CVD), as the one in low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD).
With reference to Fig. 1 g, form metal interconnect structure, described metal interconnect structure comprises the second metal level M1 and the first metal throuth hole V0, described metal interconnection structure is formed described TiN resistance to be connected with the active area in device with contact hole CCT by the first metal layer M0;
Particularly, first on described hard mask layer 108, deposit the first patterned mask layer (not shown), taking described the first patterned mask layer as hard mask layer described in mask etch 108, to open described hard mask layer 108, in described hard mask layer 108, form groove, described etching process is selected dry etching or wet etching, and in an embodiment, described wet etching is selected hydrofluoric acid and ammonium fluoride (HF/NH
4f) cushioning liquid being formed carrys out the hard mask layer of etch silicon dioxide, or selects CF
4or CHF
3etchant gas described in hard mask layer 108, above-mentioned example is only schematically, is not limited to described method.
Form groove in described hard mask layer 108 after, remove described the first patterned mask layer, on described hard mask layer 108, deposit the second patterned mask layer, carry out etching taking described the second patterned mask layer as mask, be etched to described etching stopping layer 101, to open described etching stopping layer 101, form through hole, expose described the first metal layer M0, in this etching process, can select dry etching or wet etching, those skilled in the art can select engraving method conventional in dual-damascene technics.
Then remove described the second patterned mask layer, particularly, can remove by ashing method, then taking described hard mask layer 108 as the second dielectric layer 105 described in mask etch, protective layer 106, memory layer 107, to form groove, TiN resistance described in exposed portions serve simultaneously, select the second dielectric layer 105 at engraving method described in this process, protective layer 106, memory layer 107 has the high method of selecting etching ratio with described TiN resistance and carries out etching, be not damaged at the resistance of TiN described in this etching process ensureing, in execution mode, select wet etching particularly of the present invention one, described wet etching is selected hydrofluoric acid and ammonium fluoride (HF/NH
4f) cushioning liquid being formed comes the second dielectric layer 105 described in etching, protective layer 106, memory layer 107, after forming described groove, removes described hard mask layer 108, can select the method removal of machinery planarization.
With reference to Fig. 1 h, filled conductive material in described groove or through hole, to form the second metal level M1 and the first metal throuth hole V0, realize electrical connection, and carry out planarization, particularly, described electric conducting material can pass through low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and ald (ALD) or the formation of other advanced deposition technique in the present invention.Preferably, electric conducting material is tungsten material.In another embodiment, electric conducting material can be cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and the electric conducting material that contains tungsten or its combination.
Can realize surperficial planarization with flattening method conventional in field of semiconductor manufacture.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
After filled conductive material, form the first metal throuth hole V0 and the second metal level M1, formed and be electrically connected with described metal gate structure by the first metal throuth hole V0 and the second metal level M1, described TiN resistance is connected with the active area in semiconductor device by the second metal level M1.
Below in conjunction with 2a-2c, the second execution mode of the present invention is further described, first Semiconductor substrate is provided, in described Semiconductor substrate, form metal gate structure and stressor layers SiGe layer, and form and be electrically connected on described metal gate structure and stressor layers SiGe layer, then deposition etch stop-layer 101, the first dielectric layer 102 and TiN material layer 103, obtain figure shown in Fig. 1 b, described formation method can be with reference to the conventional additive method of the formation method in the first execution mode or this area, with reference to Fig. 2 a sacrificial material layer 109 on described TiN material layer 103, described sacrificial material layer 109 can be selected the conventional oxide in this area as sacrificial oxide layer, then in described sacrificial material layer 109, deposit bottom anti-reflection layer 110(BARC) and photoresist layer 104 ˊ, as shown in Fig. 2 b-c, wherein said photoresist layer 104 ˊ select conventional photoresist layer, and carry out patterning, then open described bottom anti-reflection layer 110 and sacrificial material layer 109 taking described photoresist layer 104 ˊ as mask etch, then taking described bottom anti-reflection layer 110 and sacrificial material layer 109 as TiN material layer 103 described in mask etch, as shown in Figure 2 d, stop on described the first dielectric layer 102, on described the first dielectric layer 102, form TiN resistance, finally remove described bottom anti-reflection layer 110(BARC), photoresist layer 104 ˊ and sacrificial material layer 109, obtain the pattern as shown in Fig. 1 e, its processing step below can be selected the method in the first execution mode, but do not limit to and described method.
Below in conjunction with Fig. 3 a-m, the third execution mode of the present invention is described further:
With reference to Fig. 3 a, first Semiconductor substrate is provided, in described Semiconductor substrate, form the first dielectric layer and the metal gate structure and the stressor layers SiGe layer that are arranged in described the first dielectric layer, obtain structure as shown in Figure 3 a, the formation method of wherein said metal gate structure and stressor layers SiGe layer can be with reference to the formation method in the first execution mode, and those skilled in the art can also select formation method conventional in this area to be not limited to a certain.
With reference to Fig. 3 b, depositing TiN material layer 103, sacrificial material layer 109, be preferably oxide in sacrificial material layer 109 described in a specific embodiment of the present invention, for example silicon dioxide, but be not limited to silicon dioxide, then in described sacrificial material layer 109, form mask layer, for example, first in described sacrificial material layer 109, form bottom anti-reflection layer (BARC) 110 and photoresist layer 104 ˊ, then photoresist layer 104 ˊ described in patterning.
With reference to Fig. 3 c, TiN material layer 103 described in patterning, sacrificial material layer 109, to form TiN cover layer on described metal gate structure, on described the first dielectric layer, form TiN resistance simultaneously, particularly, open described sacrificial material layer 109 and bottom anti-reflection layer (BARC) 110 taking described photoresist layer as mask etch, then taking described sacrificial material layer 109 and bottom anti-reflection layer (BARC) 110 as TiN material layer 103 described in mask etch, retain the TiN material layer 103 on described metal gate structure, be used to form TiN cover layer, retain the part TiN material layer 103 that is positioned at metal gate structure one side simultaneously, be used to form TiN resistance, then described bottom anti-reflection layer (BARC) 110 and photoresist layer 104 ˊ are removed in ashing, described ashing removal method is selected this area common method, do not repeat them here.
Described TiN resistance and described TiN cover layer form in same operation; realize (all-in-one etch) by a step etching; in wherein said TiN cover layer, sacrificial material layer is as protective layer; the metal gate structure that protection is positioned at below is not damaged; can also serve as in addition the protective layer of metal gate structure; in the time of self-aligned silicide; prevent described metal level and the reaction of described metal gate structure; in addition; the tectal increase that can't cause resistance of described TiN; therefore described TiN cover layer can improve the performance of device, simplifies technique simultaneously.
With reference to Fig. 3 d, deposition the second dielectric layer 105, to cover described TiN cover layer and TiN resistance, then carries out planarization, and material, thickness and the formation method of described the second dielectric layer 105 all can be with reference to the first execution mode.As preferably, wherein said the second dielectric layer 105 is oxide, and its thickness is 1000-2000 dust.
With reference to Fig. 3 e, deposition hard mask layer 114, the second sacrificial material layer 109 ˊ and mask lamination, wherein said mask lamination comprises ODL115 and siliceous bottom anti-reflection layer (SiARC) 116 and photoresist layer 104 ˊ of deposition successively, then photoresist described in patterning, wherein on described TiN cover layer and TiN resistance, form the figure that critical size is greater than described TiN cover layer and TiN resistance, then taking described photoresist 104 ˊ as opening described siliceous bottom anti-reflection layer (SiARC) 116 described in mask etch, ODL115 and the second sacrificial material layer 109 ˊ, then with described siliceous bottom anti-reflection layer (SiARC) 116, ODL115 and the second sacrificial material layer 109 ˊ are hard mask layer 114 described in mask etch.
As preferably, described hard mask layer 114 is selected TiN material in the present invention, and its thickness is 300-500 dust.
With reference to Fig. 3 f, remove described ODL115 and siliceous bottom anti-reflection layer (SiARC) 116 and photoresist layer 104 ˊ, removal method can be selected this area common method, is not limited to a certain middle method, does not repeat them here.
With reference to Fig. 3 g, in described Semiconductor substrate, form mask lamination, described mask lamination comprises ODL, siliceous bottom anti-reflection layer (SiARC) and the photoresist layer of deposition successively, photoresist layer described in patterning, in photoresist layer, form groove, described groove is positioned at described metal gate structure and TiN resistance top, on described metal gate structure, the critical size of groove and metal gate structure is the same, and groove one end of described TiN resistance top is concordant with described TiN resistance, its critical size is less than described TiN resistance, as shown in Fig. 3 g.
With reference to Fig. 3 h, open described ODL, siliceous bottom anti-reflection layer (SiARC) and the second sacrificial material layer 109 ˊ taking described photoresist layer as mask etch, then taking described siliceous bottom anti-reflection layer (SiARC) and the second sacrificial material layer 109 ˊ as hard mask layer 114(TiN hard mask layer described in mask etch), then described ODL, siliceous bottom anti-reflection layer (SiARC) and photoresist layer are removed in ashing.
With reference to Fig. 3 i, deposition ODL, siliceous bottom anti-reflection layer (SiARC) and photoresist layer, photoresist layer described in patterning, forms groove, and described groove is positioned at the top of described stressor layers SiGe layer, and its number is corresponding with described stressor layers SiGe layer with critical size.
With reference to Fig. 3 j, taking described photoresist layer as siliceous bottom anti-reflection layer (SiARC) described in mask etch, open described siliceous bottom anti-reflection layer (SiARC), taking described photoresist layer and siliceous bottom anti-reflection layer (SiARC) as ODL described in mask etch, form contact hole region, then remove described photoresist, siliceous bottom anti-reflection layer (SiARC) as mask etch the second dielectric layer 105 to the degree of depth of expection taking described siliceous bottom anti-reflection layer (SiARC) and described ODL, removal method is preferably ashing method.
With reference to Fig. 3 k, remove described ODL, to expose described hard mask layer 114(TiN hard mask layer), then taking described hard mask layer 114(TiN hard mask layer) be mask etch formation groove and through hole, expose TiN cover layer and stressor layers SiGe layer on described metal gate structure, TiN resistance described in exposed portions serve simultaneously, as shown in Fig. 3 l.
With reference to Fig. 3 m, select electric conducting material to fill described groove and through hole, to form the first metal layer M0 and contact hole CCT, form electrical connection, particularly, preferentially select in the present invention metal W as electric conducting material, filling after metal W and further carry out planarisation step.
As preferably, before forming described contact hole CCT, in order to reduce contact resistance, also further comprise and form the step of autoregistration to silicide, the formation method of described self-aligned silicide is: in semiconductor substrate surface jet-plating metallization layer, for example nickel metal layer, then annealing (RTA) technique is rapidly heated, make metal level become metal silicide layer with the partial reaction that grid and regions and source/drain contact, complete self-alignment metal silicide technique (salicide).
The formation in metal silicified layer (silicide) region.First depositing metal layers, it can comprise the material of nickel (nickel), cobalt (cobalt) and platinum (platinum) or its combination.Then heated substrate, causes metal level and the silicon layer generation silicification under it, metal silication layer region thereby formation.Then use erodable metal level, but the etchant in unlikely attack metal disilicide layer region, so that unreacted metal level is removed.
As further preferred, described metal level is NiPt metal level.
After forming described the first metal layer and described contact hole CCT, be also further included in the step that forms through hole and the second metal level on described the first metal layer, to form the structure of dual damascene, the method that forms described the second metal level and through hole can be selected the conventional method in this area, does not repeat them here.
Fig. 4 is the process chart of preparing described semiconductor device in one embodiment of the invention, comprises the following steps particularly:
Step 201 provides Semiconductor substrate;
Step 202 deposits the first dielectric layer in described Semiconductor substrate;
Step 203 forms TiN resistance on described the first dielectric layer;
Step 204 deposits the second dielectric layer on described the first dielectric layer and described TiN resistance;
Step 205 forms the metal interconnect structure being electrically connected with described TiN resistance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (23)
1. a semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the first dielectric layer and the second dielectric layer in described Semiconductor substrate;
High resistance conductive material layer, the interface between described the first dielectric layer and the second dielectric layer;
And be connected to the metal interconnect structure of described high resistance conductive material layer.
2. device according to claim 1, is characterized in that, the sheet resistance of described high resistance conductive material layer is 200-1000mohm/sq.
3. device according to claim 1 and 2, is characterized in that, described high resistance conductive material layer is TiN or TaN.
4. device according to claim 1, is characterized in that, described metal interconnect structure comprises the first metal throuth hole V0 that is arranged in described the first dielectric layer and the second metal valley M1 that is arranged in described the second dielectric layer.
5. device according to claim 1, is characterized in that, described metal interconnect structure comprises the first metal valley M0 that is arranged in described the second dielectric layer.
6. device according to claim 4, is characterized in that, described metal interconnect structure is connected described high resistance conductive material layer with contact hole CCT by the first metal valley M0 with the active area in described Semiconductor substrate.
7. device according to claim 5, is characterized in that, described the first metal valley M0 is positioned on the described high resistance conductive material layer of part.
8. device according to claim 4, is characterized in that, described the second metal valley M1 is positioned on the described high resistance conductive material layer of part.
9. device according to claim 5, is characterized in that, also comprises the metal gates that is arranged in described the first dielectric layer.
10. device according to claim 9, is characterized in that, described device also comprises the TiN cover layer that is positioned at described metal gates top, and described TiN cover layer and described TiN resistance form in same operation.
The preparation method of 11. 1 kinds of semiconductor device, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, deposit the first dielectric layer;
On described the first dielectric layer, form high resistance conductive material layer;
On described the first dielectric layer and described high resistance conductive material layer, deposit the second dielectric layer;
Form the metal interconnect structure being electrically connected with described high resistance conductive material layer.
12. methods according to claim 11, is characterized in that, the sheet resistance of described high resistance conductive material layer is 200-1000mohm/sq.
13. methods according to claim 11, is characterized in that, described high resistance conductive material layer is TIN or TaN.
14. methods according to claim 11, it is characterized in that, described method is also included in the step that forms the first metal valley M0 and contact hole CCT in described Semiconductor substrate, and described metal interconnect structure is connected described high resistance conductive material layer with contact hole CCT by the first metal valley M0 with the active area in described Semiconductor substrate.
15. methods according to claim 14, is characterized in that, the method that forms described high resistance conductive material layer is:
In described Semiconductor substrate, form etching stopping layer;
On described etching stopping layer, deposit described the first dielectric layer;
On described the first dielectric layer, deposit high resistance electric conducting material;
TiN material layer described in patterning, to remove the described high resistance electric conducting material of part, forms described high resistance conductive material layer.
16. methods according to claim 15, is characterized in that, the method for high resistance electric conducting material is described in patterning:
On described high resistance electric conducting material, form mask layer, described mask layer is the combination of photoresist or photoresist and sacrificial material layer, bottom anti-reflection layer;
Mask layer described in patterning;
Taking described mask layer as high resistance electric conducting material described in mask etch;
Remove described mask layer.
17. methods according to claim 15, is characterized in that, the method that forms described metal interconnect structure comprises the following steps:
On described the second dielectric layer, deposit protective layer, memory layer and hard mask layer;
Etching stopping layer, described the first dielectric layer, described the second dielectric layer described in patterning, in described the first dielectric layer, form through hole, to expose described the first metal valley M0, in described the second dielectric layer, form groove, with high resistance conductive material layer described in exposed portions serve;
Select electric conducting material to fill described through hole and described groove, form respectively the first metal throuth hole V0 and the second metal valley M1, to form electrical connection;
Remove described protective layer, memory layer and hard mask layer.
18. methods according to claim 17, is characterized in that,
Described etching stopping layer is silicon nitride material or the SiN layer of carbon containing;
Described the first dielectric layer is oxide skin(coating) or low-K material layer;
Described the second dielectric layer is low-K material layer;
Described protective layer is oxide skin(coating);
Described memory layer is TiN layer;
Described sacrificial material layer is oxide skin(coating).
19. methods according to claim 11, is characterized in that, described method comprises:
In described the first dielectric layer, form metal gate structure;
On described the first dielectric layer, deposit high resistance electric conducting material and sacrificial material layer;
High resistance electric conducting material and described sacrificial material layer described in patterning form high resistance electric conducting material cover layer on described metal gate structure, form high resistance conductive material layer simultaneously;
Deposit described the second dielectric layer, and form the first metal valley M0 in described the second dielectric layer, wherein said the first metal valley M0 is positioned on the described high resistance conductive material layer of part.
20. methods according to claim 19, is characterized in that, the method that forms described metal interconnect structure is:
On described the second dielectric layer, deposit hard mask layer, the second sacrificial material layer;
The second sacrificial material layer and described hard mask layer described in patterning;
Taking described hard mask layer as the second dielectric layer described in mask etch, to form groove in described the second dielectric layer, high resistance conductive material layer described in exposed portions serve;
Select electric conducting material to fill described groove, to form described the first metal valley M0.
21. methods according to claim 19, is characterized in that, described hard mask layer is TiN material layer.
22. methods according to claim 19, is characterized in that, described method is further comprising the steps of:
Form stressor layers in described metal gate structure both sides;
In the technique that forms metal interconnect structure, in described stressor layers, form electrical connection, comprise following sub-step:
On described the second dielectric layer, deposit hard mask layer, the second sacrificial material layer;
Hard mask layer described in patterning, to form contact hole in described hard mask layer, described contact hole is positioned at described stressor layers top;
Hard mask layer described in patterning, to form groove in described hard mask layer, described groove is positioned at described metal gate structure top;
With the second dielectric layer described in described hard mask layer etching, to form contact hole and groove in described the second dielectric layer, expose described stressor layers and described metal gate structure;
Deposits conductive material, fills described contact hole and groove, to form contact hole CCT and described electrical connection.
23. methods according to claim 22, is characterized in that, before forming described contact hole CCT, are also included in the step that forms self-aligned silicide in described stressor layers.
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| CN108461482A (en) * | 2017-02-17 | 2018-08-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| US10366988B2 (en) | 2015-08-14 | 2019-07-30 | International Business Machines Corporation | Selective contact etch for unmerged epitaxial source/drain regions |
| CN110957257A (en) * | 2018-09-26 | 2020-04-03 | 台湾积体电路制造股份有限公司 | Semiconductor-on-insulator substrate, method of forming the same, and integrated circuit |
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| CN114613562A (en) * | 2020-12-09 | 2022-06-10 | 上海类比半导体技术有限公司 | Precision resistor structure with dummy fill |
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