CN104183563B - Bonding structure of semiconductor device - Google Patents
Bonding structure of semiconductor device Download PDFInfo
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- CN104183563B CN104183563B CN201310200384.7A CN201310200384A CN104183563B CN 104183563 B CN104183563 B CN 104183563B CN 201310200384 A CN201310200384 A CN 201310200384A CN 104183563 B CN104183563 B CN 104183563B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
The invention relates to a bonding structure of a semiconductor device. The bonding structure comprises a first conductive layer, a second dielectric layer, a first conductive via, a third dielectric layer, a second conductive layer, a protection layer, and an opening. The first conductive layer having a first superficial area is arranged in a first dielectric layer. The second dielectric layer is arranged on the first dielectric layer and the first conductive layer. The first conductive via having a second superficial area is arranged in the second dielectric layer. The third dielectric layer is arranged on the second dielectric layer and the first conductive via. The second conductive layer having a third superficial area is arranged in the third dielectric layer. The protection layer is arranged on the second conductive layer and the third dielectric layer. And the opening is arranged inside the protection layer and parts of the opening are exposed out of the second conductive layer. The proportion of the first superficial area to the second superficial area to the third superficial area is between 0.29:0.28:1 and 0.43:0.42:1. According to the invention, the provided bonding structure has the excellent structural strength; and the damage caused by process factors like testing and packaging and the like when the dimension of the semiconductor device is changed into the miniature one can be prevented. The service life and the reliability of the semiconductor device containing the bonding structure can be guaranteed.
Description
Technical field
The present invention with regard to semiconductor device, and especially with regard to a kind of bonding pad structure of semiconductor device.
Background technology
In general, the making of semiconductor device be on a wafer by deposition in order and the multiple insulation of patterning,
The film layer of conductive and quasiconductor and formed.Generally, the numerous film layers for being formed at the top of semiconductor device are constituted
For the bonding pad structure (bonding structure) that electrical connection is located at the lower section active area in wafer and element,
And then can carry out such as the test related process of probe test (probe testing) for this bonding pad structure among successive process
Or the encapsulation related process of routing engagement (wire bonding).
However, with the micro of manufacture of semiconductor, just need to be improved for bonding pad structure, so that it is carrying out probe
The test encapsulation related process such as test (probing test) or routing engagement (wire bonding) still has certain when implementing
Structural strength, to guarantee the service life and reliability of semiconductor device.
The content of the invention
In view of this, the invention provides a kind of bonding pad structure of semiconductor device, it has preferably structural strength, can
Still will not cause to damage because of the processing procedure factor such as test and encapsulation when the size more micro of semiconductor device, and then can ensure that
Life-span and reliability including the semiconductor device of bonding pad structure.
One embodiment of foundation, a kind of bonding pad structure of semiconductor device of the present invention, including：One first conductive layer, is arranged
In the inside of one first dielectric layer, wherein, first conductive layer is accumulated with a first surface；One second dielectric layer, is arranged at this
On first dielectric layer and first conductive layer；One first conductive interlayer thing, is arranged at the inside of second dielectric layer, and positioned at this
On first conductive layer, wherein, the first conductive interlayer thing is accumulated with a second surface；One the 3rd dielectric layer, be arranged at this second
On dielectric layer and the first conductive interlayer thing；One second conductive layer, is arranged at the inside of the 3rd dielectric layer, and positioned at this first
On conductive interlayer thing, wherein：Second conductive layer has one the 3rd surface area；One protective layer, be arranged at second conductive layer with
On 3rd dielectric layer；And one opening, be arranged in the protective layer, with part expose second conductive layer, wherein this first
Conductive layer and the center of first conductive interlayer thing aligned in general second conductive layer and arrange, and first surface product, should
Second surface is accumulated to be had between 0.29 and the 3rd surface area between:0.28:1~0.43:0.42:1 ratio.
In a preferred embodiment, second conductive layer is a tabular profile of tetragon, the first conductive interlayer
Thing is octagonal tabular profile with first conductive layer.
In a preferred embodiment, the material of first dielectric layer, second dielectric layer and the 3rd dielectric layer includes
Silicon oxide, silicon nitride or low dielectric constant dielectric materials.
In a preferred embodiment, the material of the protective layer includes pi or silicon nitride.
In a preferred embodiment, the material of first conductive layer, second conductive layer and the first conductive interlayer thing
Including tungsten, aluminum or copper.
In a preferred embodiment, also include：
A pair the 3rd conductive layers, are respectively arranged at the inside of first dielectric layer and positioned at the relative of first conductive layer
Side；And
Multiple second conductive interlayer things, are respectively arranged at the inside of second dielectric layer and positioned at the first conductive interlayer thing
Opposite side and be located on those the 3rd conductive layers, the plurality of second conductive conductive layer of interlayer thing electrical connection the 3rd with this
Two conductive layers, those the 3rd conductive layers are strip profile and have one the 4th surface area respectively, those the second conduction interlayer things
A pair of regularly arranged array things of Jing are formed, those array things have a total surface area, the 4th surface area and the 3rd surface
Have between 0.06 between product:1~0.28:1 ratio, has between 0.001 between the total surface area and the 3rd surface area:
1~0.002:1 ratio.
In a preferred embodiment, those the 3rd conductive layers include tungsten, aluminum with the material of those the second conductive interlayer things
Or copper.
In a preferred embodiment, also include：
One the 4th dielectric layer, under first dielectric layer；
Multiple second conductive interlayer things, are arranged in the 4th dielectric layer simultaneously material contact first conductive layer.
In a preferred embodiment, the thickness of the 4th dielectric layer is respectively greater than first dielectric layer, the second dielectric layer
With the thickness of the 3rd dielectric layer.
In a preferred embodiment, the material of the 4th dielectric layer includes that silicon oxide, silicon nitride or low-k are situated between
Electric material, the material of those the second conductive interlayer things includes tungsten, aluminum or copper.
The characteristics of bonding pad structure of the semiconductor device of the present invention and advantage are：The bonding pad structure of the semiconductor device has
Preferably structural strength, still will not can make because of test when the size more micro of semiconductor device with the processing procedure factor such as encapsulating
Into damage, and then can ensure that life-span and the reliability of semiconductor device including bonding pad structure.
Description of the drawings
Fig. 1 illustrates the profile according to a bonding pad structure of one embodiment of the invention.
Fig. 2 is the top view of the bonding pad structure one illustrated according to Fig. 1.
Fig. 3 is the top view in another portion of a bonding pad structure illustrated according to Fig. 1.
Fig. 4 illustrates the profile according to the bonding pad structure of one embodiment of the invention.
Fig. 5 is the top view of the bonding pad structure one that one embodiment of the invention is illustrated according to Fig. 4.
Fig. 6 is the top view in another portion of bonding pad structure that one embodiment of the invention is illustrated according to Fig. 4.
Fig. 7 illustrates the profile according to the bonding pad structure of another embodiment of the present invention.
Component symbol explanation
100 ... semiconductor structure 102 ... dielectric layers
The conductive interlayer things of 104a, 104b, 104c ... conductive layer 106a, 106b ...
110 ... protective layers 112 ... are open
120 ... slight crack 200 ... bonding pad structures
400 ... semiconductor device 500 ... semiconductor structures
502 ... dielectric layer 504a, 504b, 504c, 504d ... conductive layers
Conductive interlayer thing 510 ... the protective layer of 506a, 506b, 506c ...
512 ... 600,600 ' ... bonding pad structures of opening
800 ... semiconductor devices
Specific embodiment
It is that above-mentioned purpose, feature and the advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and match somebody with somebody
Appended accompanying drawing is closed, is described in detail as follows.
Fig. 1 illustrates the profile of the bonding pad structure according to the semiconductor device 400 of one embodiment of the invention.Refer to
Fig. 1, semiconductor device 400 mainly includes semiconductor structure 100, the multiple dielectrics being sequentially formed on semiconductor structure 100
Layer 102, respectively be located at this little dielectric layer 102 in multiple conductive layers (conductive layers) 104a, conductive layer 104b,
Conductive layer 104c and multiple conductive interlayer thing (conductive vias) 106a, conduction interlayer thing 106b and being arranged at most goes up
A protective layer (passivation layer) 110 on square dielectric layer 102.Wherein, in an embodiment, semiconductor structure 100
Including the semiconductor substrate (not shown) of such as silicon material, and on this semiconductor substrate and/or within formed just like electric brilliant
Multiple active members (active elements) of body, diode, and the such as multiple passive devices of resistance, electric capacity, inductance
(passive elements) and such as wire, conductive contact thing, the multiple conducting element (conductive of conductive interlayer thing
Elements), and then the IC (integrated circuits, do not show) with specific function is constituted.So
And, based on the purpose of simplified illustration, this semiconductor substrate and being formed thereon/its in aforementioned components only adopt in Fig. 1
With depicted in the semiconductor structure 100 of a tool flat surface, and not shows in detail semiconductor substrate and related elements is detailed
It is thin that situation is set.
In addition, this little dielectric layer 102 being formed on semiconductor structure 100 and setting this little conductive layer in the inner
104a, conductive layer 104b, conductive layer 104c then constitute semiconductor device with conductive interlayer thing 106a, conduction interlayer thing 106b
A bonding pad structure 200 in 400, the IC that this bonding pad structure 200 can be electrically connected in semiconductor device 400 (does not show
Show).In addition, an opening 112 is formed with protective layer 110, and this 112 part of opening exposes the dielectric for being arranged at the top
One of a conductive layer 104c in layer 102, and the part of the 112 conductive layer 104c for being exposed that are open then as follow-up test or
A connection pad (bonding pad) applied in the related process such as encapsulation.
Furthermore, the inner conducting layer 104b of the multiple dielectric layers 102 and conductive layer 104a being respectively formed in below conductive layer 104c
Also can be used with conducting element as support component, structurally to support conductive layer 104c and electrical connection above it to lead
IC in electric layer 104c and semiconductor device 400.And be respectively arranged at this little conductive layer 104a, conductive layer 104b and lead
Conductive interlayer thing 106a in multiple dielectric layers 102 between electric layer 104c and conduction interlayer thing 106b then do interior company's element it
With linking with entity and electrically this little conductive layer 104a, conductive layer 104b and conductive layer 104c.
In an embodiment, protective layer 110 may include such as pi, the insulation material of the anti-aqueous vapor property of silicon nitride tool
Material, and dielectric layer 102 may include such as silicon dioxide, spin-coating glass (SOG), silicon nitride, low-k (dielectric constant is less than 3)
The dielectric materials such as dielectric material, and conductive layer 104a, conductive layer 104b, conductive layer 104c and conductive interlayer thing 106a, conductive Jie
Layer thing 106b then may include such as tungsten, aluminum, copper conductive material.
Fig. 2 is the top view of the bonding pad structure one that semiconductor device is illustrated according to Fig. 1.Referring to Fig. 1 and figure
2, conductive layer 104b have the tabular profile and a surface area A1 (not shown)s such as tetragon, and now shown in Fig. 1
Conductive layer 104c on regarding sight (not shown) also have and the tabular profile of conductive layer 104b identicals one and surface area.Separately
Outward, on regarding the (not shown) of sight, multiple conductive layer 104a as shown in fig. 1 then have the length separated by dielectric layer 102
Strip-like appearance, and with a total surface area (not shown).The total surface area of conductive layer 104a is less than conductive layer 104b and 104c's
Surface area A1.
Fig. 3 is the top view in another portion of a bonding pad structure that semiconductor device is illustrated according to Fig. 1.Referring to Fig. 1 and
Fig. 3, the multiple conductive interlayer thing 106b between conductive layer 104c and conductive layer 104b are substantially according to a such as hexagonal polygon
Form and be arranged at the multiple conductive columns things in dielectric layer 102, and this little conduction interlayer thing 106b has altogether a total surface
Product A2 (not shown)s, it is less than the surface area A1 of conductive layer 104b and conductive layer 104c.Have between this little surface area A2 and A1
Between about 0.002:1~0.003:1 proportionate relationship (A2:A1).
After the semiconductor device 400 shown in Fig. 1-Fig. 3 is formed, bonding pad structure 200 that can be in semiconductor device 400
Implement such as the follow-up survey of probe test (probing test) or routing engagement (wire bonding) at interior conductive layer 104c
The related process (all not showing) such as examination and encapsulation.However, after the related process such as above-mentioned follow-up test and encapsulation is implemented, Chang Yu
As found to have to split in the dielectric layer 102 in the Optical devices inspection of ultramicroscope between conductive layer 104c and conductive layer 104b
The generation of trace (cracks) 120.The generation of above-mentioned slight crack 120 is due to the follow-up test such as such as probe test or routing engagement and envelope
Caused by transfer scenario applied in the related process such as dress in the stress of conductive layer 104c, and so slight crack 120 is likely to
The dielectric layer being further created on due to the transfer of stress between the conductive layer 104b and conductive layer 104a of lower layer
In 102.If the scope of this little slight crack 120 is excessive with quantity, its neighbouring conductive interlayer thing 106b will be probably damaged with conductive Jie
Layer thing 106a, and the operation lifetime and reliability of the semiconductor device 400 for affecting to include bonding pad structure 200.In view of this, just need
The bonding pad structure to be directed in semiconductor device is improved, to solving the above-mentioned connection pad knot for betiding semiconductor device 400
Slight crack problem in structure 200.
Fig. 4 illustrates the profile according to the bonding pad structure of another embodiment of the present invention.Refer to Fig. 4, it is shown that including one
The semiconductor device 800 of bonding pad structure 600.Here, semiconductor device 800 mainly includes semiconductor structure 500, sequentially shape
Into the multiple dielectric layers 502 on semiconductor structure 500, respectively be located at this little dielectric layer 502 in multiple conductive layer 504a, lead
Electric layer 504b, conductive layer 504c, conductive layer 504d and conductive interlayer thing 506a, conductive interlayer thing 506b, conductive interlayer thing 506c,
And the protective layer 510 being arranged on the dielectric layer 502 of the top.
In an embodiment, semiconductor structure 500 is same as the semiconductor structure 100 shown in Fig. 1, therefore here is no longer described
Its composition situation.In addition, this little dielectric layer 502 being formed on semiconductor structure 500 and setting this little conductive layer in the inner
504a, conductive layer 504b, conductive layer 504c, conductive layer 504d and conductive interlayer thing 506a, conductive interlayer thing 506b, conductive interlayer
Thing 506c then constitutes the bonding pad structure 600 in semiconductor device 800, and this bonding pad structure 600 can be electrically connected at quasiconductor
IC (not shown) in device 800.In addition, an opening 512 is formed with protective layer 510, and this 512 part of opening
One of the conductive layer 504d being arranged in the dielectric layer 502 of the top is exposed, and is 512 conductive layers for being exposed that are open
The part of 504d is then as the connection pad (bonding pad) applied in the related process such as follow-up test or encapsulation.
Furthermore, be respectively formed in the inner conducting layer 504c of multiple dielectric layers 502, conductive layer 504b below conductive layer 504d with
Conductive layer 504a also can be used as support component with conducting element, with structurally support conductive layer 504d above it and
IC (not illustrating) in electrical connection conductive layer 504d and semiconductor device 800.And it is respectively arranged at this little conductive layer
Conductive interlayer thing 506a in multiple dielectric layers 502 between 504a, conductive layer 504b, conductive layer 504c and conductive layer 504d,
Conductive interlayer thing 506b and conductive interlayer thing 506c then as connecting element in such as conduction interlayer thing, to connect physically and electrically
Tie this little conductive layer 504a, conductive layer 504b, conductive layer 504c and conductive layer 504d.
In an embodiment, protective layer 510, dielectric layer 502, conductive layer 504a, conductive layer 504b, conductive layer 504c, lead
Electric layer 504d and conductive interlayer thing 506a, conductive interlayer thing 506b, the formation material of conductive interlayer thing 506c be then same as
The protective layer 110 in semiconductor device 400 shown in Fig. 1-Fig. 3, dielectric layer 102, conductive layer 104a, conductive layer 104b, conduction
Layer 104c and conductive interlayer thing 106a, the material of conductive interlayer thing 106b, will not be described here.
Fig. 5 is the top view of the bonding pad structure one that the present invention is illustrated according to Fig. 4.Refer to Fig. 5, conductive layer 504b with
The setting situation of conductive layer 504c is then different from the conductive layer 104b in the semiconductor device 400 of Fig. 1-Fig. 2.Conductive layer 504c has
There is the substantially octagonal tabular profile including four oblique angles, and with a surface area A3 (not shown)s, and in conductive layer
A conductive layer 504b is then respectively arranged with the two opposite sides side of 504c.Conductive layer 504b has as outside a rectangular strip
Shape, and with a surface area A4.And the conductive layer 504d above conductive layer 504b and conductive layer 504c is formed at (with dotted line table
Show) the conductive layer 104c that is then still same as shown in Figure 1-Figure 3, it has a tabular profile of approximate quadrangle, thus tool
It is a big surface area A1 (not illustrating) to have compared with conductive layer 504c and conductive layer 504b, and wherein conductive layer 504c aligned in general is in leading
The center of electric layer 504d and arrange, and conductive layer 504b is then substantially aligned with the two opposite sides side of conductive layer 504d and sets
Put.In an embodiment, have between 0.29 between this little surface area A1, A3, A4:0.06:1~0.43:0.28:1 ratio
Example (A3:A4:A1).In addition, on depending on (not the illustrating) of sight, this little conductive layer 504a then has what is separated by dielectric layer 502
Strip profile, and with a total surface area (not shown).The total surface area of this little conductive layer 504a is less than conductive layer 504d's
Surface area A1.
Fig. 6 is the top view in another portion of bonding pad structure that the present invention is illustrated according to Fig. 4.Referring to Fig. 4 and Fig. 6,
This, different from the enforcement of the conductive interlayer thing 106b between conductive layer 104c and conductive layer 104b shown in previous Fig. 1-Fig. 3
Situation, in the present embodiment, then sets within the dielectric layer 502 between conductive layer 504d and conductive layer 504b, conductive layer 504c
Multiple conductive interlayer thing 506b are equipped with conductive interlayer thing 506c.Here, conductive layer 504d is same as aforesaid conductive layer 104c
And with surface area A1, it is still a conductive columns thing that conductive interlayer thing 506b is same as aforesaid conductive interlayer thing 106b, and its
Substantially to arrange and being arranged in dielectric layer 502 according to an array thing (array) form of a mxn, and this conductive interlayer thing
An array thing that 506b is formed then is generally located at the lower section of two symmetrical sides of the conductive layer 504d above it and is generally located at
The top of one of conductive layer 504b below, and then electrically linked conductive layer 504d and conductive layer 504b.This little conduction
An array thing that interlayer thing 506b is formed has total surface area A5, and it is less than the surface area A1 of conductive layer 504d, and therebetween
With between about 0.001:1~0.002:1 ratio (A5:A1).
In addition, on regarding sight, conductive interlayer thing 506c has the substantially octagonal tabular for including four oblique angles
Profile, and with a surface area A6, its aligned in general thereon square conductive layer 504d and arrange, and its surface area A6 is less than it
Top conductive layer 504d surface area A1 and less than the surface area A3 of conductive layer 504c below, and this little surface area A3,
Have between about 0.29 between A6 and A1:0.28:1~0.43:0.42:1 proportionate relationship (A3:A6:A1).Similar in appearance to conductive layer
The setting situation of 504c, also aligned in general sets conductive interlayer thing 506c in conductive layer 504d with the center of conductive layer 504c
Put.
After the semiconductor device 800 shown in Fig. 4-Fig. 6 is formed, such as probe can be implemented at bonding pad structure 600 in the inner
The related process (all not illustrating) such as the follow-up test and encapsulation of test or routing engagement.Conductive interlayer thing in due to the present embodiment
The summation of 506b and the surface area A5 and surface area A6 of conductive interlayer thing 506c conduction more as shown in Figure 1-Figure 3 in embodiment
Total surface area A2 of interlayer thing 106b is higher by about 94-21 times, and the set location of conductive interlayer thing 506c is located at most of test
External force with encapsulation etc. in related process puts on the underface of a core of conductive layer 504d, and conduction interlayer thing
506b is more conducive to put on the level of the applied stress at conductive layer 504d with four oblique angles part included by conductive layer 504c
With the loss in vertical direction.Therefore by the use of bonding pad structure 600 as Figure 4-Figure 6, in follow-up test and encapsulation
After implementing Deng related process, can't be between conductive layer 504d and conductive layer 504c and conductive layer 504b and conductive layer
The generation of slight crack 120 as shown in Figure 1 is caused in dielectric layer 502 between 504c and conductive layer 504b and conductive layer 504a, such as
This just can keep out the undesirable stress due to the conductive layer 504d of the side of being applied thereto in the related process such as follow-up test and encapsulation
Transfer scenario, and then the operation lifetime and reliability of the semiconductor device 800 for guaranteeing to include this bonding pad structure 600.
Fig. 7 illustrates the profile according to the bonding pad structure of another embodiment of the present invention.Semiconductor device as shown in Figure 7
800 is by obtained by the semiconductor device 800 changed as Figure 4-Figure 6.Here, representing phase with identical label in Fig. 7
Isomorphic product, and based on simplified purpose, only describe below at the difference between two embodiments.
Refer to Fig. 7, the broadly similar of bonding pad structure 600 ' in bonding pad structure 600 as Figure 4-Figure 6, except Yu Benshi
Apply the thickness that conductive interlayer thing 506a and its neighbouring dielectric layer 502 are increased in example.Conductive interlayer thing in the present embodiment
The thickness of 506a and its neighbouring dielectric layer 502 can be more as Figure 4-Figure 6 conductive interlayer thing 506a and its neighbouring dielectric
The thickness of layer 502 is more thickened.So conduction interlayer thing 506a and neighbouring dielectric layer 502 thicken situation also contribute to
Keep off further downward with the stress for the conductive layer 504d of the side of being applied thereto in related process such as encapsulating due to follow-up test
Vertical transitions situation.Thus, just can ensure that the operation lifetime and reliability of the semiconductor device 800 including this bonding pad structure 600 '
Degree.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any to be familiar with this
Technical staff, without departing from the spirit and scope of the present invention, when can change and retouch, therefore protection scope of the present invention is worked as
Define depending on right and be defined.
Claims (10)
1. a kind of bonding pad structure of semiconductor device, it is characterised in that include：
One first conductive layer, is arranged at the inside of one first dielectric layer, wherein, first conductive layer is accumulated with a first surface；
One second dielectric layer, is arranged on first dielectric layer and first conductive layer；
One first conductive interlayer thing, is arranged at the inside of second dielectric layer, and on first conductive layer, wherein, this
One conductive interlayer thing is accumulated with a second surface；
One the 3rd dielectric layer, is arranged on second dielectric layer and the first conductive interlayer thing；
One second conductive layer, is arranged at the inside of the 3rd dielectric layer, and on the first conductive interlayer thing, wherein, this
Two conductive layers have one the 3rd surface area；
One protective layer, is arranged on second conductive layer and the 3rd dielectric layer；And
One opening, is arranged in the protective layer, partly exposes second conductive layer, and wherein first conductive layer is first conductive with this
Interlayer thing is directed at the center of second conductive layer and arranges, the first surface product, the second surface product and the 3rd surface area
Between have between 0.29:0.28:1~0.43:0.42:1 ratio.
2. the bonding pad structure of semiconductor device as claimed in claim 1, it is characterised in that second conductive layer is tetragon
One tabular profile, the first conductive interlayer thing is octagonal tabular profile with first conductive layer.
3. the bonding pad structure of semiconductor device as claimed in claim 1, it is characterised in that first dielectric layer, this second is situated between
Electric layer includes silicon oxide, silicon nitride or low dielectric constant dielectric materials with the material of the 3rd dielectric layer.
4. the bonding pad structure of semiconductor device as claimed in claim 1, it is characterised in that the material of the protective layer includes poly- Asia
Amide or silicon nitride.
5. the bonding pad structure of semiconductor device as claimed in claim 1, it is characterised in that first conductive layer, this second leads
Electric layer includes tungsten, aluminum or copper with the material of the first conductive interlayer thing.
6. the bonding pad structure of semiconductor device as claimed in claim 1, it is characterised in that also include：
A pair the 3rd conductive layers, are respectively arranged at the inside of first dielectric layer and positioned at the opposite side of first conductive layer；With
And
Multiple second conductive interlayer things, are respectively arranged at the inside of second dielectric layer and positioned at the phase of the first conductive interlayer thing
Offside is simultaneously located on those the 3rd conductive layers, and the plurality of second conductive conductive layer of interlayer thing electrical connection the 3rd second is led with this
Electric layer, those the 3rd conductive layers are strip profile and have one the 4th surface area respectively, and those second conductive interlayer things are formed
A pair of Jing regularly arranged array things, those array things have a total surface area, the 4th surface area and the 3rd surface area it
Between have between 0.06:1~0.28:1 ratio, has between 0.001 between the total surface area and the 3rd surface area:1~
0.002:1 ratio.
7. the bonding pad structure of semiconductor device as claimed in claim 6, it is characterised in that those the 3rd conductive layers with those the
The material of two conductive interlayer things includes tungsten, aluminum or copper.
8. the bonding pad structure of semiconductor device as claimed in claim 1, it is characterised in that also include：
One the 4th dielectric layer, under first dielectric layer；
Multiple second conductive interlayer things, are arranged in the 4th dielectric layer simultaneously material contact first conductive layer.
9. the bonding pad structure of semiconductor device as claimed in claim 8, it is characterised in that the thickness difference of the 4th dielectric layer
More than the thickness of first dielectric layer, the second dielectric layer and the 3rd dielectric layer.
10. the bonding pad structure of semiconductor device as claimed in claim 8, it is characterised in that the material bag of the 4th dielectric layer
Silicon oxide, silicon nitride or low dielectric constant dielectric materials are included, the material of those the second conductive interlayer things includes tungsten, aluminum or copper.
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| CN201310200384.7A CN104183563B (en) | 2013-05-27 | 2013-05-27 | Bonding structure of semiconductor device |
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| CN201310200384.7A CN104183563B (en) | 2013-05-27 | 2013-05-27 | Bonding structure of semiconductor device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937893A (en) * | 2009-05-29 | 2011-01-05 | 瑞萨电子株式会社 | Semiconductor device |
| CN102931155A (en) * | 2011-08-09 | 2013-02-13 | 联发科技股份有限公司 | Bump pad structure |
-
2013
- 2013-05-27 CN CN201310200384.7A patent/CN104183563B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937893A (en) * | 2009-05-29 | 2011-01-05 | 瑞萨电子株式会社 | Semiconductor device |
| CN102931155A (en) * | 2011-08-09 | 2013-02-13 | 联发科技股份有限公司 | Bump pad structure |
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