CN104183270B - The processing unit and method of configuration data - Google Patents

Abstract

The processing unit and method of a kind of configuration data.The processing unit is to provide configuration data to a microprocessor, and including a fuse array group and an at least kernel.Fuse array group is arranged on a crystal grain, and including one first fuse array and one second fuse array.Kernel is arranged on crystal grain, fuse array group is coupled, and including an array control, to access first and second fuse array, and according to the content of a configuration data register, handle a first state of the first fuse array and one second state of the second fuse array.

Description

Device and method for processing configuration data

technical field

The present invention relates to a microelectronics, and more particularly to an apparatus and method for providing compressed configuration data to a fuse array of a multi-core device.

Background technique

Integrated circuit technology has grown exponentially over the past 40 years. Especially in the field of microprocessors, starting from 4-bit single-instruction, 10-micron devices, the growth of semiconductor manufacturing technology allows designers to increase the device density inside complex devices. In the pipelined and superscalar (scalar) microprocessors of the 1980s and 1990s, millions of transistors could be placed on a single die. In the ensuing 20 years, 64-bit 32-nanometer devices emerged that housed billions of transistors in a single die with multiple microprocessor cores for processing data.

These early devices need to be initialized with configuration data when starting or resetting the device. For example, many architectures enable devices with at least one selectable frequency and/or voltage. Other architectures require each device to have a serial number and other information that can be read by executing instructions. Registers and control circuits inside other devices require initialization data. Other devices use the configuration data to implement additional circuits when the aforementioned circuits are manufactured with errors or are not within critical limits.

Those skilled in the art are well aware that designers can utilize conventional on-die semiconductor fuse arrays to store and provide initial configuration data. When part of the fuse array has been manufactured, these fuse arrays can be programmed by blowing selected fuses, and the fuse array has thousands of bits of information, which can be read when starting/resetting the device , to initialize and configure the operation of the corresponding device.

As the complexity of the device increases, the amount of configuration data increases accordingly. However, those skilled in the art know well that although the size of transistors shrinks with the semiconductor process, the size of semiconductor fuses integrated on the die increases. This phenomenon affects usable space as well as power loss and thus becomes a problem for designers. Therefore, if a large fuse array is to be fabricated on a die, the die may not provide enough usable space.

In addition, since each core requires a certain number of fuses, this problem is exacerbated when many cores are to be fabricated on a single die.

Therefore, there is a need for an apparatus and method that allows configuration data to be stored and provided in a multi-core device without occupying too much space and consuming too much power in a single die.

In addition, a fuse array mechanism is needed to store and provide more configuration data than conventional techniques in the same or smaller space.

Contents of the invention

The present invention utilizes compressed configuration data for a fuse array in a multi-core device to provide preferred techniques for addressing the above problems and satisfying other problems and disadvantages as well as known limitations. In a possible embodiment, the present invention provides a processing device for providing configuration data to a microprocessor, and includes a fuse array set and at least one core. The fuse array group is disposed on a die and includes a first fuse array and a second fuse array. The core is disposed on the die, coupled to the fuse array group, and includes an array control for accessing the first and second fuse arrays, and processing a first state of the first fuse array according to the content of a configuration data register and a second state of the second fuse array.

The present invention also provides a processing device for providing configuration data to a microprocessor, and includes a fuse array, a random access memory (RAM) and a plurality of cores. The fuse array is arranged on a die and includes a plurality of semiconductor fuses. The semiconductor fuses are programmed according to the compressed configuration data. Random access memory, provided on the die. The inner cores are individually disposed on the die. Each core is coupled to the fuse array and the random access memory, and upon boot/reset operation, each of the cores accesses the fuse array or the random access memory according to the contents of a load data register to know the compression configuration data.

The present invention also provides a processing method for providing configuration data to a microprocessor, and includes arranging a fuse array group on a chip, wherein the fuse array group includes a first fuse array and a second fuse array; disposing at least one core on the die, the core being coupled to the fuse array group; and using an array control of the core, and according to the contents of a configuration data register, accessing and processing a first state of the first fuse array and second fuses A second state of the array.

The present invention provides another processing method for providing configuration data to a microprocessor, including disposing a fuse array on a die, wherein the fuse array includes a plurality of semiconductor fuses, the semiconductor fuses are configured according to a compressed configuration data be programmed; place a random access memory (RAM) on the die; place multiple cores individually on the die, and couple each core to the fuse array and RAM; and at boot/reset In operation, each of the cores accesses the fuse array or random access memory according to the content of a loaded data register for knowing the compressed configuration data.

For industrial applications, the invention may be implemented in microprocessors, which are used in general or special purpose computing devices.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are specifically listed below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic diagram of a conventional microprocessor core with a fuse array.

FIG. 2 is a schematic diagram of the microprocessor core with redundant fuse sets of FIG. 1 .

FIG. 3 is a schematic diagram of providing compressed and decompressed configuration data to a multi-core device according to the present invention.

Fig. 4 is a possible embodiment of a fuse decompression mechanism according to the present invention.

FIG. 5 is a schematic diagram of a possible format of the compressed configuration data of the present invention.

FIG. 6 is a schematic diagram of a possible format of the decompressed microcode insertion configuration data of the present invention.

FIG. 7 is a schematic diagram of a possible format of the decompressed microcode register configuration data of the present invention.

FIG. 8 is a schematic diagram of a possible format of the decompressed cache correction data of the present invention.

FIG. 9 is a schematic diagram of a possible format of decompressed fuse correction data according to the present invention.

Figure 10 is a possible embodiment of the present invention for a multi-core device with configurable redundant fuse arrays.

FIG. 11 is a schematic diagram of a mechanism for quickly loading configuration data into a multi-core device according to the present invention.

FIG. 12 is a possible embodiment of the false positive correction mechanism of the present invention.

【Symbol Description】

100, 200: block; 101: microprocessor core; 102, 201, 336: fuse array; 103: reset logic; 104: reset circuit; 105: reset microcode; 107: control circuit; 108: microcode Register; 109: microcode insertion component: 110: cache correction component; RESET: reset signal; 202, PFB1～PFBN, RFB1～RFBN: fuse group; 203: fuse; 210～211: register; PR1: main register; RR1: redundant register; 212: XOR logic gate; FB3: output; 310: device programmer; 320: compressor; 301, 302: virtual fuse group; 302: virtual fuse; 330: die; 332, 1002, 1102: kernel; 334: cache memory; 401, 1001, 1101, 1201: physical level fuse array; 403: compressed microcode insert fuse; 404: compressed register fuse; 405: compressed cache correction fuse 406: Compressed fuse correction fuse; 408: Insert fuse element; 409: Register fuse element; 410: Cache fuse element; 411: Fuse correction element; 412: Bus; 414: Microcode insert element; 415: Micro code register; 416: cache correction component; 417: reset controller; 420: microprocessor core; 421: decompressor; 500: compressed configuration data; 502: compressed data field; 503: end type field; 504: end fuse field; 600: decompress microcode and insert configuration data; 601: kernel address field; 602: microcode ROM address field; 603: microcode insert data field; 604: decompress data block; 700: Decompress microcode register configuration data; 701: kernel address field; 702: microcode register address field; 703: microcode register data field; 704: decompress data block; 800: decompress cache correction data; 802: Subunit row address field; 803: Replace row address field; 804: Decompress data block; 900: Decompress fuse correction data; 901: End fuse field; 902: Remelt field; 903: Fuse correction field ;1000: multi-core device; 1003, 1103: array control; 1004: configuration data register; 1100: device; 1104: load data register; 1101: physical level fuse array; 1105: non-core RAM; 1200: error confirmation correction mechanism ;1202: ECC code block; 1203: compressed configuration data block; 1224: ECC component; 1226: decompressor; 1220: microprocessor core; 1222: reset controller; CDATA: bus; ADDR: address bus; CODE: code bus; DATA: data bus.

detailed description

An integrated circuit (IC) is a collection of electronic circuits formed on a small size of a semiconductor material, such as silicon. An integrated circuit may also be called a chip, microchip or die.

A central processing unit (CPU) refers to an electronic circuit (i.e., hardware) that executes instructions of a computer program (i.e., a computer application program or an application program) by performing an operation on data, which includes arithmetic operations, logic operations, and Input/output operations.

Microprocessor refers to an electronic device as a central processing unit on a single integrated circuit. A microprocessor receives digital data as input, processes the data according to instructions from a memory, where the memory is provided or not provided on the die, and produces the result of the operation required by the output instructions. A general-purpose microprocessor can be used in desktop, portable or tablet circuits, and can perform calculation, word processing, multimedia display and web browsing. A microprocessor may be placed in an embedded system to control many devices, including equipment, mobile phones, smartphones, and industrial control devices.

A multi-core processor, also known as a multi-core microprocessor, is a microprocessor that has multiple central processing units (cores) formed on the same integrated circuit.

Instruction Set Architecture (ISA) or instruction set refers to the portion of a computer architecture used for programming, including data types, instructions, registers, address modes, memory architecture, interrupt and exception handling, and input/output. An ISA includes the properties of a set of opcodes (ie, machine language instructions) as well as the native commands used by a particular CPU.

An x86 compatible microprocessor refers to a microprocessor capable of executing computer applications, which are programmable according to the x86 ISA.

Microcode refers to multiple microinstructions. A microinstruction (also called a native instruction) is an instruction that is executable by a microprocessor sub-arithmetic unit. In a possible embodiment, the subunits include an integer operation unit, a floating point operation unit, an MMX operation unit, and a load/store operation unit. For example, microinstructions are directly executed by a Reduced Instruction Set (RISC). For multiple instruction set (CISC) microprocessors (eg, x86 compatible microprocessors), x86 instructions are translated into composite microinstructions, and the composite microinstructions are directly executed by the CISC microprocessor.

A fuse is a conductive structure, usually a thin wire, which can be blown by applying a voltage to the thin wire and/or passing a current through the thin wire. Using known fabrication techniques, fuses are deposited at specific locations on a die topology to create programmable fine lines. After fabrication is complete, fuses are blown (or not) to provide programming of a corresponding device on the die.

Please refer to FIG. 1 , a block 100 is a schematic diagram of a current microprocessor core 101 . The microprocessor core 101 has a fuse array 102 for providing configuration data to the microprocessor core 101 . The fuse array 102 has a plurality of semiconductor fuses (not shown). Semiconductor fuses are generally arranged in columns. The fuse array 102 is coupled to the reset logic 103 . The reset logic 103 includes a reset circuit 104 and a reset microcode 105 . The reset logic 103 is coupled to the control circuit 107 , the microcode register 108 , the microcode insertion component 109 and the cache correction component 110 . An external reset signal RESET is coupled to the microprocessor core 101 . The reset logic 103 receives an external reset signal RESET.

Those skilled in the art are well aware that a large number of integrated circuit devices use fuses (also known as links or fuse structures) to provide integrated circuit configuration after the integrated circuit device is fabricated. For example, the microprocessor core 101 of FIG. 1 provides function selection for application in a desktop device or a portable device. Therefore, during manufacture, the fuses in the fuse array 102 may be blown for selecting a device, such as a portable device. Therefore, when the reset signal RESET is enabled, the reset logic 103 reads the state of the specified fuse in the fuse array 102, and the reset circuit 104 (in this example, not the reset microcode 105) enables the corresponding Corresponding control circuit 107. The control circuit 107 disables the components related to the desktop function in the microprocessor core 101 and enables the components related to the portable function in the microprocessor core 101 . Therefore, the microprocessor core 101 is activated and reset as a portable device. In addition, reset logic 103 reads the states of other fuses in fuse array 102, and reset circuit 104 (in this example, not reset microcode 105) enables corresponding cache correction elements 110 for A correction mechanism is provided for at least one cache memory (not shown) of the microprocessor core 101 . Therefore, the microprocessor core 101 is activated and reset as a portable device, and the calibration mechanism of the cache memory of the microprocessor core 101 is also properly set.

The foregoing examples are merely illustrative of the many different uses for fuses within microprocessor core 101 of FIG. 1 . Those skilled in the art are well aware of other uses of fuses, not limited to the configuration of device-specific data (such as serial numbers, unique encryption codes, authorization data of computer internal structures, which can be accessed by users, speed settings, voltage setting), initialize data and insert data. For example, many current devices execute microcode to initialize microcode registers 108 . Microcode register fuses (not shown) in fuse array 102 may provide data for initialization, during a reset operation, by reset logic 103 (reset circuit 104 or reset microcode 105, or reset circuit 104 and reset microcode 105) to read the initialized data, and provide the read initialized data to the microcode register 108. To accomplish this, reset circuit 104 includes hardware elements that provide certain types of configuration data that reset microcode 105 cannot provide. The reset microcode 105 includes a plurality of microinstructions that are located in an internal microcode memory (not shown). When the microprocessor core 101 is reset, the internal microcode memory is executed to perform initialization functions of the microprocessor core 101. These functions include reading the configuration data in the fuse array 102 and providing the read results to multiple components, such as microcode registers 108 and microcode insertion mechanism 109. A special setting of the microprocessor core 101 is to determine whether the configuration data of the fuse array is provided to the various components 107 - 110 of the microprocessor core 101 through the reset microcode 105 . The purpose of the present invention is not to individually initialize integrated circuit devices. Those skilled in the art know that the types of configuration elements 107-110 of the current microprocessor core 101 usually fall into four types. Taking FIG. 1 as an example, namely These are control circuits, microcode registers, microcode insertion mechanisms, and cache correction mechanisms. In addition, those skilled in the art will appreciate that the value of configuration data obviously changes according to the type of data. For example, a 64-bit control circuit 107 may include ASCII data, and the ASCII data is used to specify the serial number of the microprocessor core 101 . Other 64-bit control registers may have 64 different speed settings, and only one speed setting is enabled at a time to control the operating speed of the microprocessor core 101 . In general, the microcode registers 108 may be initialized to be all 0s (ie, a low logic state) or all 1s (ie, a high logic state). The microcode insertion mechanism 109 may include evenly distributed 1s and 0s to indicate the addresses of microcode values to be replaced in a microcode ROM (not shown). The microcode values of these addresses will be replaced. Finally, the cache correction mechanism may include a few setpoints of 1 to indicate that a certain cache sub-bank element (ie, a column or row) needs to be replaced with a specific replacement sub-bank element.

The fuse array 102 provides an excellent function for programming the microprocessor core 101 after a device such as the microprocessor core 101 is manufactured. By blowing certain fuses in the fuse array 102, the microprocessor core 101 can be operated in a corresponding environment. However, those skilled in the art are well aware that the operating environment of the microprocessor core 101 can be changed by programming the fuse array 102 . The microprocessor core 101 may be initialized due to business requirements, such as being initialized from a desktop device to a portable device. Therefore, the designer can place redundant fuses in the fuse array 102 as non-blowing fuses, thereby initializing the configuration of the microprocessor core 101, correcting manufacturing errors, . . . and so on. A fuse array with redundant fuses is illustrated in FIG. 2 .

Please refer to FIG. 2 , a block 200 shows a fuse array 201 in the microprocessor core 101 , which has fuse groups 202 (redundant fuse groups RFB1 -RFBN and first fuses PFB1 -PFBN). The first fuse group PFB1 ˜ PFBN in the fuse array 201 will be blown first, and then the redundant fuse group RFB1 ˜ RFBN will be blown. The redundant fuse groups RFB1 - RFBN and PFB1 - PFBN include a predetermined number of fuses 203 , and the fuses 203 are independent. The number of fuses 203 is related to the specific design of the microprocessor core 101 . For example, in a 64-bit microprocessor core 101 , the number of fuses 203 in the fuse bank 202 may be 64 for the microprocessor core 101 to use configuration data.

The fuse array 201 is coupled to the registers 210 - 211 . Generally speaking, the registers 210 - 211 are set in the reset logic of the microprocessor core 101 . The primary register PR1 is used to read one of the first fuse banks PFB1 - PFBN (assuming it is the fuse bank PFB3 in the block diagram 200 ). The redundancy register RR1 is used to read one of the redundant fuse groups RFB1 - RFBN. The registers 210 and 211 are both coupled to an XOR logic gate 212 . The XOR logic gate 212 provides an output FB3.

In operation, after the microprocessor core 101 is manufactured, the first fuse groups PFB1 ˜ PFBN can be programmed by known techniques to become configuration data that the microprocessor core 101 can use. None of the redundant fuse sets RFB1 ˜ RFBN are blown, and remain in a low logic state. When starting/resetting the microprocessor core 101 , the main register 210 and the redundant register 211 respectively read the states of the first fuse banks PFB1 -PFBN and the redundant fuse banks RFB1 -RFBN. An Exclusive OR (also referred to as “mutually exclusive OR”) logic gate 212 performs an exclusive OR operation on the data stored in the registers 210 and 211 to generate the output FB3. Since all the redundant fuse groups are not blown (that is, they are all in low logic state), the value of the output FB3 is simply the result of the programming of the first fuse group PFB1˜PFBN after manufacture.

Currently, due to design or business requirements, it is required that the information written into the first fuse groups PFB1 -PFBN can be changed. Therefore, in order to change the read information after startup, a programmable operation must be performed to blow the corresponding redundant fuses 203 in the redundant fuse groups RFB1 -RFBN. When a fuse 203 in the selected redundant fuse group RFB1 -RFBN is blown, a corresponding fuse 203 in the first fuse group PFB1 -PFBN is logically matched with it.

The mechanism of Fig. 2 may provide remelting fuse 203 in microprocessor core 101, but those skilled in the art know well, because there is only one group of redundant fuse groups RFB1～RFBN, therefore, redundant fuse groups RFB1～RFBN Each fuse 203 in the fuse can only be remelted once. In order to provide multiple remelting, multiple groups of additional fuse groups 202 and registers 210-211 can be added in the microprocessor core 101.

So far, the fuse array schemes of FIGS. 1 and 2 provide enough flexibility for the microprocessor core and other related devices to allow a limited number of remelting. Manufacturing techniques (eg, 65 and 45 nm processes) can form enough fuses on the die to set a microprocessor core 101 on the die. However, current techniques are still limited by two obvious factors. The first factor is that the trend in the art is to form multiple microprocessor cores 101 in the same die to increase processing performance. These so-called multi-core devices may have 2-16 individual cores 101, each core configured with fuse data in order to turn on/reset the cores 101. Therefore, for a 4-core device, 4 fuse arrays 201 will be used in independent cores, and the data of each core may be different (such as cache calibration data, redundant fuse data, etc.). The second is that those skilled in the art are well aware that the reduction of manufacturing technology (such as 32 nanometers), therefore, the size of the transistor is also reduced, so the size of the fuse increases, so it is necessary to realize a 45-nanometer fuse on a 32-nanometer grain. array.

In view of the above-mentioned limitations and other challenges for device designers, especially designers of multi-core devices, the present invention provides a significant improvement over known device configuration mechanisms, the present invention programs independent cores in a multi-core device, and increases Number of cache corrections and fuse reprogramming (remelting). The present invention will be explained later with reference to FIGS. 3-12 .

FIG. 3 is a schematic diagram of a system 300 of the present invention for compressing and decompressing configuration data of a multi-core device. The multi-core device has multiple cores 332 . The core 332 is disposed on a die 330 . For the convenience of description, Fig. 3 only shows the cores CORE1-CORE4. The cores CORE1 to CORE4 are disposed on the die 330 . In other embodiments, die 330 may have other numbers of cores 332 . In this embodiment, all cores 332 share a single cache memory 334 . Cache memory 334 is also disposed on die 330 . A single programmable fuse array 336 is also provided on die 330 and is used by each core 332 to access fuse array 336 to extract and decompress configuration data during boot/reset operations.

In one embodiment, the core 332 includes a microprocessor core to form a multi-core microprocessor (die) 330 . In other embodiments, the multi-core microprocessor 330 is an x86 compatible multi-core microprocessor. In other embodiments, the cache memory 334 includes a level 2 cache memory coupled to the microprocessor core 332 . In one possible embodiment, fuse array 336 has 8192 (8K) individual fuses (not shown), although other numbers of fuses may be used. In a single core embodiment, only one core 332 is disposed on the die 330 and the core 332 is coupled to the cache memory 334 and the fuse array 336 . Although the features and functions of the multi-core device (die) 330 will be described later, the features of the multi-core device are the same as those of a single core.

System 300 also includes a device programmer 310 . Device programmer 310 includes a compressor 320 . The compressor 320 is coupled to the virtual fuse array 303 . In one possible embodiment, device programmer 310 may include a central processing unit (not shown) for processing configuration data and programming fuse array 336 after die 330 is fabricated using known programming techniques. The CPU may be integrated into a wafer testing facility for testing device die 330 after fabrication. In one possible embodiment, the compressor 320 may have an application program executable on the device programmer 310 , and the virtual fuse array 303 may include the address of a memory that is accessed by the compressor 320 . The virtual fuse array 303 has many virtual fuse groups 301 . Each virtual fuse group 301 has a plurality of virtual fuses 302 . In a possible embodiment, the virtual fuse array 303 has 128 virtual fuse groups 301 , and each virtual fuse group 301 has 64 virtual fuses 302 , therefore, the size of the fuse array 303 is 8Kb.

In operation, as shown in FIG. 1 , configuration information of the device 330 is input into the virtual fuse array 330 during the manufacturing stage. Therefore, the configuration information includes configuration data of the control circuit, initialization data of microcode registers, microcode insertion data, and cache correction data. Also, as mentioned above, different types of configuration data have different values. Virtual fuse array 303 is a logical representation of a fuse array (not shown) with configuration information for each microprocessor core 332 on die 330 and calibration data for each cache memory 334 on die 330 .

After the information is stored in the virtual fuse array 303, the compressor 320 reads the status of the virtual fuses 302 of each virtual fuse group 301, and uses the separate compression algorithms (distinct compression algorithms) corresponding to each data type to perform compression to generate Compress fuse array data. In a possible embodiment, the system data of the control circuit is not compressed, but converted without compression. To compress the microcode register data, a microcode register data compression algorithm may be used for compressing data having a state distribution relative to the microcode register data. To compress the microcode insertion data, a microcode insertion data compression algorithm for efficiently compressing data having a state distribution corresponding to the microcode insertion data may be used. To compress the cache alignment data, a cache alignment data compression algorithm can be used to efficiently compress data with a state distribution corresponding to the cache alignment data.

Next, device programmer 310 programs the uncompressed and compressed fuse array data into physical level fuse array 336 on die 330 .

During a boot/reset operation, each core 332 may access physical level fuse array 336 to extract both uncompressed and compressed fuse array data, and reset circuitry/microcode within each core 332 (not Shown) publishes the uncompressed fuse array data, and decompresses the compressed fuse array data according to the separate decompression algorithm corresponding to each data type, so as to provide the original value originally in the virtual fuse array 303 . The reset circuit/microcode then provides configuration information to the control circuit (not shown), microcode registers (not shown), intervening components (not shown), and cache correction components (not shown).

The fuse array compression system 300 of the present invention enables device designers to reduce the number of fuses in the physical level fuse array 336 and utilize the compressed information during boot/reset operations to configure a multi-core device 330 Certainly.

Referring to FIG. 4, block 400 shows the fuse decompression mechanism of the present invention. A decompression mechanism may be provided in each microprocessor core 332 of FIG. 3 . To clearly illustrate the present invention, FIG. 4 only shows a single core 420 , but each core 332 on the die of FIG. 3 has elements of the core 420 of FIG. 4 . The physical level fuse array 401 is disposed on the die and coupled to the core 420 . The physical level fuse array 401 has compressed microcode insertion fuses 403 , compressed register fuses 404 , compressed cache correction fuses 405 , and compressed fuse correction fuses 406 . The physical level fuse array group 401 may also have uncompressed configuration data (not shown), such as the aforementioned system configuration data and/or Error Checking and Correction (ECC) codes (not shown). The ECC feature according to the present invention will be described later.

The microprocessor core 420 includes a reset controller 417 . The reset controller 417 receives a reset signal REST, and the reset signal REST is used to initialize the core 420 to make the core 420 perform a reset step. The reset controller 417 has a decompressor 421 . The decompressor 421 has an insert fuse element 408 , a register fuse element 409 and a cache fuse element 410 . The decompressor 421 also includes a fuse correction element 411 coupled to the insertion fuse element 408 , the register fuse element 409 and the cache fuse element 410 via a bus 412 . Insert fuse element 408 is coupled to microcode insert element 414 within core 420 . Register fuse element 409 is coupled to microcode register 415 in core 420 . The cache fuse element 410 is coupled to the cache correction element 416 within the core 420 . In one possible embodiment, the cache correction element 416 is disposed on a die with a level 2 (L2) cache memory (not shown). All cores 420 share a cache correction element 416 , such as cache memory 334 of FIG. 3 . In another embodiment, the cache correction element 416 is disposed on a die with a level 1 (L1) cache memory (not shown). In other embodiments, the cache correction element 416 is disposed on a die having a level 1 (L1) and level 2 (L2) cache memory (not shown).

In operation, when the reset signal RESET is asserted, the reset controller 417 reads the state of the fuses 403-406 in the physical level fuse array 401 and provides the state of the compressed system fuses (not shown) to the solution compressor 421 . After the read and provide is complete, the fuse correction component 411 in the decompressor 421 decompresses the compressed fuse correction fuse 406 state to provide data representing at least one fuse address of the fuse array 401 at the physical level, previously The state that has been programmed will be changed. The decompressed data may contain at least one fuse address value. The at least one fuse address (and optional value) is transmitted to the components 408-410 through the bus 412, so that the state of the corresponding fuse is changed before being decompressed.

In a possible embodiment, the insert fuse element 408 includes microcode for decompressing the state of the compressed microcode insert fuse 403 according to a microcode insert decompression algorithm, the microcode insert decompress algorithm corresponding to FIG. 3 The microcode inserts the compression algorithm. In a possible embodiment, the register-fuse element 409 includes microcode to decompress the compressed register-fuse 404 according to a register-fuse decompression algorithm corresponding to the register-fuse compression algorithm described in FIG. 3 . In one possible embodiment, cache-fuse element 410 includes microcode for decompressing compressed cache-correct-fuse 405 according to a cache-correct-fuse decompression algorithm, the cache-correct-fuse decompression algorithm corresponding to FIG. 3 The cache correction fuses the compression algorithm. The fuse correction component 411 provides the address of the fuse through the bus 412, and each of the components 408-410 changes the state of the corresponding fuse according to these addresses, and then decompresses the respective data of the fuse according to the corresponding algorithm. The multi-refuse fuse described in the present invention will be described in detail later, and the refuse step is earlier than the initialization of the decompression action of the elements 408-411. In one possible embodiment, the bus 412 may include known microcode programming mechanisms for transferring data. The present invention also has an integrated decompressor 421, which can identify and decompress configuration data according to the type of configuration data. Therefore, to illustrate the present invention, the decompressor 421 has only elements 408-411, however, as long as the condensation-decompressor 421 can provide the functions of the elements 408-411, the present invention may not require the elements 408-411.

In one possible embodiment, the reset controller 417 initializes the microcode inserted into the fuse element 408 to decompress the compressed microcode inserted into the fuse 403 . The reset controller 417 also initializes the microcode of the register fuse element 409 to decompress the compressed register fuse 404 state. Moreover, the reset controller 417 further initializes the microcode of the cache fuse element 410 to decompress the compressed cache correction fuse 405 . Before decompression, the microcode of the decompressor 421 will first change the state of certain fuses, wherein the changed fuses are the fuses specified by the fuse correction data of the compressed fuse correction fuse 406 .

The reset controller 417, the decompressor 421 and the components 408-411 are used to perform the above functions. Reset controller 417, decompressor 421 and components 408-411 may include logic, circuit, device or microcode, or a combination of logic, circuit, device or microcode, or equivalent components, which can perform the functions and operations described above . These components used to realize the reset controller 417, the decompressor 421 and the components 408-411 may be shared by other circuits, microcodes, etc., which can execute the reset controller 417, the decompressor 421 and the components 408-411 411 or other functions and/or operations of other elements in the kernel 420.

After changing and decompressing the states of the fuses 403 - 406 in the physical fuse array 401 , the decompressed states of the virtual fuses are provided to the microcode insertion component 414 , microcode register 415 and cache correction component 416 . Therefore, the kernel 420 performs the next reset operation.

In other embodiments, the above-mentioned decompression functions do not need to be executed in a specific order when performing the reset operation. For example, the decompression of microcode-inserted data may follow the decompression of microcode register initialization data. Likewise, in other embodiments, in order to meet design requirements, the decompression function may be performed simultaneously.

In addition, the realization of the elements 408-411 of the present invention does not necessarily use the microcode corresponding to the hardware circuit, because in the general microprocessor core 420, it has some elements, and these elements can be more easily initialized by hardware ( such as a scan chain associated with a cache), rather than directly writing microcode. The implementation details of these are at the discretion of the designer. However, in a reset operation prior to initializing the microcode, known techniques utilize hardware circuitry to routinely read cache calibration fuses and enter a cache calibration scan chain. Unless the microcode starts to operate, the cache memory of the core will not be turned on. Therefore, the feature of the present invention is to implement the cache fuse decompressor 410 by using the microcode corresponding to the hardware control circuit. Using microcode to implement the cache fuse element 410 can write cache correction data into a scan chain, and obviously saves hardware components, thus increasing design flexibility and beneficial mechanisms.

Please refer to FIG. 5 , which shows the format of the compressed configuration data 500 of the present invention. The compressor 320 of FIG. 3 compresses the data of the virtual fuse array 330 and programs (ie blows) the compressed configuration data 500 into the physical level fuse array 336 of the multi-core device 330 . As a result of the reset described above, the compressed configuration data 500 is extracted from the physical level fuse array 336 by each core 332 and decompressed by elements 408- 411 corrected. The decompressed and corrected configuration data is then provided to the multiple elements 414 - 416 of the core 420 for initializing the core 420 .

The compressed configuration data 500 has at least one compressed data field (D) 502 , and each configuration data type mentioned above is separated by an end type field (ET) 503 . Programming events (ie, blowouts) are separated by an end blowout field (EB) 504 . The compressed data field 502 associated with each data type is encoded according to a compression algorithm to minimize the number of bits (ie, fuses) used to store the flag pattern associated with each data type. The number of fuses that make up the physical level fuse array 336 for each compressed data field 502 is characteristic of the compression algorithm used for a particular data type. For example, consider a core with 64-bit microcode registers, which must all be initialized to 0 or 1. An optimal compression algorithm may provide 64 compressed data fields 502, each with initialization data for a particular microcode register, depending on data type, the compressed data fields 502 are specified in register number order ( ie 1-64). And each compressed data field 502 has a single fuse. If a corresponding microcode register needs to be initialized to 1, the single fuse is blown. If the corresponding microcode register needs to be initialized to 0, the single fuse is blown. The fuse is not blown.

After the initial programming event, the components 408-410 of the decompressor 421 in the core 420 use the end type field 503 to determine whether their respective compressed data has been placed in the physical level fuse array 336, and the fuse corrects the decompressor 411 The compressed fuse calibration data that has been programmed (ie, blown) after an initialization procedure event is located using End Blow Fuse 504 . For subsequent multi-programming events, the present invention sets a large number of spare fuses in the physical-level fuse array 336, which will be described in detail below.

The above-mentioned compression type formats are used to illustrate the compression and decompression of configuration data in the present invention. However, the compression, separation, and data types and quantities of specific types of data that are compressed into the fuse array 401 shown in FIG. 5 are not intended to limit the present invention. In other embodiments, the present invention can be modified with other numbers, types and formats to obtain different devices and algorithms.

Please refer to FIG. 6 , which shows a possible format of the decompressed microcode insertion configuration data 600 according to the present invention. Under reset operation, each core 420 is utilized to read the compressed microcode insertion configuration data in the physical level fuse array 401 . Then, according to the fuse correction data provided by the bus 412, the compressed microcode insertion configuration data is corrected. Then, the corrected compressed microcode insert configuration data is decompressed by insert fuse decompressor 408 . The result of the decompression procedure inserts configuration data 600 for the decompression microcode. Data 600 includes a plurality 604 of decompressed data blocks. The number of decompressed data blocks 604 corresponds to the number of microcode inserts 414 in the kernel 420 that need to initialize data. Each decompressed data block 604 includes a kernel address field 601 , a microcode memory (ROM) address field 602 and a microcode insertion data field 603 . The lengths of the fields 601-603 are characteristic of the kernel algorithm. During the partial decompression process, the full image of the object data provided by the fuse component 408 is inserted, which is used to initialize the microcode insertion component 414 . In the subsequent decompression of the microcode insertion configuration data 600 , known publishing mechanisms may be used for publishing the data 603 to the respective address kernel and microcode ROM replacement circuits/registers in the microcode insertion component 414 .

Please refer to FIG. 7 , which shows the format of decompressed microcode register configuration data 700 according to the present invention. In a reset operation, by each core 420, the compressed microcode register configuration data in the physical level fuse array 401 is read. The compressed microcode register configuration data is then corrected based on the fuse correction data provided by the bus 412 . Then, the register fuse element 409 decompresses the corrected compressed microcode register configuration data. The result of the decompression procedure is decompressed microcode register configuration data 700 . Data 700 includes a number of decompressed data blocks 704 corresponding to the number of microcode registers 415 in kernel 420 that require initial data. Each decompressed data block 704 has a kernel address field 701 , a microcode register address field 702 and a microcode register data field 703 . The lengths of the fields 701-703 are characteristic of the kernel algorithm. The register fuse element provides a complete image of the target data to initialize microcode registers 415 during a partial decompression process. In the subsequent decompression of the microcode register configuration data 700 , known publishing mechanisms may be used for publishing the data 703 to the respective address cores and microcode registers 415 .

Please refer to FIG. 8 , which shows a possible format of decompressed cache correction data 800 according to the present invention. In the reset operation, the compressed cache correction data of the physical level fuse array 401 is read by each core 420 . Then, the compressed cache correction data is corrected according to the fuse correction data provided by the bus 412 . Next, the cache correction data is decompressed using the cache fuse element 410 . The result of the decompression process is decompressed cache correction data 800 . The multi-core processor 300 uses different cache mechanisms, and the decompressed cache correction data 800 is stored in the shared secondary cache memory 334 . All cores 332 may access the same cache memory 334 to use the same storage space. Thus, the format shown in Figure 8 is according to the algorithm described above. The data 800 includes a plurality of decompressed data blocks 804 , the number of decompressed data blocks 804 corresponds to the number of cache correction elements 416 in the core 420 that need to correct data. Each decompressed data block 804 has a primary unit row address field 802 and a replacement row address field 803 . Those skilled in the art are well aware that when manufacturing a cache memory, redundant rows (or columns) will be formed together in the subunits of the cache memory to replace them with a non-functional row (or column) Functionally redundant rows (or columns) within a particular subunit. Thus, decompressing cache correction data 800 allows non-functional rows to replace functional rows (as shown in FIG. 8 ). In addition, those skilled in the art are well aware that when a redundant sub-unit row needs to be used for replacement, it is known that the fuse of each sub-unit row in the cache correction fuse array mechanism will be blown. Therefore, since a large number of fuses are required (to access all subunits and rows), only a fraction of the subunits can be included, resulting in known cache correction fuses being seldom blown. The present invention is characterized by accessing and compressing addresses of subunit rows, and replacing row addresses for subunit rows that need to be replaced. Thus, minimizing the number of fuses applied to cache correction data. Therefore, the present invention extends the number of subunit rows (or columns) of the cache memory 334 under the limitation of the size of the physical level fuse array and the amount of additionally programmed configuration data, and the cache memory 334 can be corrected. In the embodiment shown in FIG. 8 , associated cores 332 share the L2 cache memory 334 for accessing and providing correction data 802 - 803 to respective cache correction elements 416 . The lengths of the fields 801-803 are characteristic of the kernel algorithm. During part of the decompression process, the cache correction fuse component 410 provides a complete image of the target data used to initialize the cache correction component 416 . After decompressing the cache alignment data 800 , known publishing mechanisms within the responsible kernel 420 may issue the data 802 - 803 to the cache alignment element 416 being accessed.

Please refer to FIG. 9 , which shows a possible format of the decompressed fuse correction data 900 of the present invention. As described above, at reset, the fuse correction element 411 accesses the compressed fuse correction data 406 in the physical level fuse array 401, decompresses the compressed fuse correction data, and provides the decompressed fuse correction data 900 to the rest of the core 420. Elements 408-410. The decompressed fuse calibration data has at least one end blown field (EB) 901 indicating that the programming event in the physical level fuse array 401 has successfully ended. If a programming event occurs subsequently, a re-fuse column (R) 902 will be programmed to indicate at least one subsequent fuse correction column (FC) 903, which indicates that the fuse in the physical fuse array 401 will be blown again . Each fuse calibration field has the address of a specific fuse in the physical level fuse array 401 that is to be set again to a state (ie, blown or not blown). Only the fuses in the Fuse Correction box field 903 will be reset, and each field 903 for a resetting event will be separated by an end blown field 901 . If the remelt field 902 is successfully coded after a specific end blow field 901, according to the corresponding fuse correction field, then at least the fuse may be blown again. Therefore, within the limited size of the fuse array and the data that the array can provide, the present invention can perform multiple settings for the same fuse.

For additional features on a multi-core die, the present invention shares physical-level fuse arrays with compressed configuration data for practical performance and power gains. In addition, those skilled in the art are well aware that the current semiconductor fuse structure often has some disadvantages, one of which is "growback". Long back is exactly the inversion of programming procedure, as a fuse is blown after a period of time, connects again, just returns to an unprogrammed state (being not blown) from a programming state (being blown).

One of the many advantages of the present invention, in order to control long loops and other challenges, is to provide a redundant, unconfigured physical level fuse array. Therefore, Figure 11 provides a configurable redundant fuse bank mechanism.

Please refer to FIG. 10 , which shows a possible embodiment of a physical-level fuse array 1001 of a multi-core device 1000 according to the present invention. The multi-core device 1000 includes a plurality of cores 1002, the features of which are disclosed in FIGS. 3-10 and related descriptions. Additionally, each core 1002 includes an array control 1003 that is programmed according to configuration data in configuration data registers 1004 . Each array control 1003 is coupled to the redundant fuse array 1001 .

To illustrate the present invention, FIG. 10 only shows four cores 1002 and two physical-level fuse arrays 1001, but it is not intended to limit the present invention. In other embodiments, other numbers of cores 1002 can also be used according to the disclosure of the present invention. And physical level fuse array 1001.

In operation, each physical level fuse array 1001 receives configuration data in configuration data registers 1004 representing a particular configuration of the physical level fuse array 1001 . In one embodiment, the physical level fuse array 1001 acts as an aggregated physical level fuse array according to the value of the configuration data. The size of the aggregated physical-level fuse array is equal to the sum of the sizes of the respective physical-level fuse arrays 1001, and the aggregated physical-level fuse array may be used to store the next multiple configuration data, and the amount of data stored is greater than that of a single physical-level fuse array 1001 The amount of data stored. Therefore, the array control 1003 controls the corresponding core 1002 to read the physical level fuse array 1001, such as an aggregated physical level fuse array. In other embodiments, to control long-back, the physical level fuse array 1001 is programmed with the same configuration data as a redundant fuse array according to the value of the configuration data, and the array control 1003 in each core 1002 has many The element is used to perform OR logic on the contents of two (or more) arrays, so that if at least one blown fuse of the array 1001 is blown, at least another corresponding fuse in the array 1001 remains blown. In a fail-safe embodiment, at least one physical-level fuse array 1001 is selectively disabled and the remaining arrays 1001 are enabled, either as an aggregate configuration or as an OR logic configuration, based on configuration data values. Therefore, the array control 1003 in each core 1002 does not access the contents of the disabled array 1001 but accesses the enabled redundant array according to a specific configuration data in the configuration data register 1004 .

Configuration data registers 1004 are programmable by any known device with programmable fuses, external pin settings, JTAG programming, or other similar means.

In another embodiment, the inventors have discovered that when at least one physical level fuse array is disposed on a single die with multiple cores, problems may occur when the cores access the array. Specifically, under boot/reset operations, each core in a multi-core processor must read the physical level fuse array according to a serial direction. First, the first core reads the array, then the second core reads the array, then the third core reads the array, and so on. Those skilled in the art are well aware that the read of the fuse array is the most time consuming compared to other operations performed by the core, so when many cores have to read the same array, the time required is roughly one core multiplied by the number of cores on the die. Those skilled in the art are well aware that these fuses must be read in order to obtain reliable results, but according to the manufacturing process, the reading times and life of the semiconductor fuse will affect the quality of the semiconductor fuse. Therefore, in other embodiments, the present invention reduces the time it takes for the core to read the physical level fuse array, and is used to increase fuses by reducing the number of accesses to the cores of a multi-core processor during boot and reset operations. The lifetime of the array.

Please refer to FIG. 11 , which shows a schematic diagram of a mechanism for rapidly loading configuration data into a multi-core device 1100 according to the present invention. The device 1100 has a plurality of cores 1102 whose characteristics are described in the related descriptions of FIGS. 3-10 . Additionally, each core 1102 has an array control 1103 that is programmed with load data into a load data register 1104 . Each core 1102 is coupled to a physical level fuse 1101 , the features of which are described in the related descriptions of FIGS. 3-10 . Each core 1102 is coupled to random access memory (RAM) 1105 , which is disposed on the same die as the core 1102 , but cannot be disposed within the core 1102 . Therefore, RAM 1105 is referred to as non-core RAM 1105 .

For convenience of illustration, FIG. 11 only shows four cores 1102 and one physical-level fuse array 1101 , but this is not intended to limit the present invention. In other embodiments, any number of cores 1101 and multiple physical-level fuse arrays 1101 can be extended.

In operation, each core receives load data in a load data register 1104 representing a particular load data relative to the physical level fuse array 1101 . The content value of the load data register 1104 designates one core 1102 as the primary core 1102, and the other remaining cores are called secondary cores 1102, which have a load order. Therefore, under a boot/reset operation, the array control 1103 causes the main core 1102 to read the contents of the physical level fuse array 1101 and then write the contents of the physical level fuse array 1101 to the uncore RAM 1105 . If multiple physical-level fuse arrays 1101 are disposed on a die, the capacity of the uncore RAM 1105 must be able to store data of all physical-level fuse arrays 1101 . After the main core 1102 stores the content of the physical level fuse array 1101 into the uncore RAM 1105 , the array control 1103 instructs the corresponding secondary core 1102 to read the specific content loaded into the data register 1104 in the uncore RAM 1105 .

It is known to have programmable fuses, external pin settings, JTAG programs, or other related devices, all of which can be programmed into the data register 1104 . The embodiment shown in FIG. 11 can also be integrated in the redundant fuse array scheme described in FIG. 10 .

Please refer to FIG. 12 , which shows a possible embodiment of the error confirmation correction (ECC) mechanism according to the present invention. The error acknowledgment correction mechanism 1200 can be integrated in the embodiments shown in FIGS. 3-11 and enhances the compression and decompression of configuration data. FIG. 12 depicts a microprocessor core 1220 disposed on a die coupled to a physical level fuse array 1201 . The physical level fuse array 1201 includes a compressed configuration data block 1203 . The compressed configuration data block is described above. To compress configuration data block 1203 , physical level fuse array 1201 has ECC code block 1202 . Each ECC code block 1202 is associated with a corresponding data block 1203 . In a possible embodiment, the data block 1203 has 64 bits (ie, 64 fuses), and the ECC code block 1202 has 8 bits (ie, 8 fuses). The core 1220 has a reset controller 1222 which receives a reset signal RESET. The reset controller 1222 has an ECC element 1224 coupled to a decompressor 1226 through the bus CDATA. The ECC element 1224 is coupled to the fuse array 1201 through an address bus ADDR, a data bus DATA and a code bus CODE.

In operation, fuse array 1201 is programmed with configuration data from data block 1203 as described in FIGS. 3-11 . Configuration data corresponding to a specific data block 1203 or across multiple data blocks 1203 corresponding to a specific data type (such as microcode insertion data, microcode register data) will not be programmed. Additionally, configuration data for more than two data types may be programmed into the same data block 1203 . In addition, the ECC code programming array 1201 in the ECC code block 1202 . According to the known ECC mechanism, the ECC code is programmed into a corresponding data block 1203, but it is not intended to limit the present invention. In other embodiments, variations of SECDED Hamming codes, Chipkill ECC, or Preamble Error Correction (FEC) codes may also be used. In a possible embodiment, the addresses related to the data block 1203 and the corresponding ECC code block 1202 are both known. Therefore, there is no need to use the corresponding ECC code block 1202 of the adjacent data block 1203 in FIG. 12 .

The structure and function of the decompressor 1226 are substantially the same as the decompressor 421 shown in FIG. 4, and have been briefly described in FIGS. 5-11. When resetting the kernel 1220, before performing the decompression function described above, the ECC element in the reset controller 1222 accesses the fuse array to obtain its contents. Through the bus ADDR, the addresses of the data block 1203 and the ECC code block 1202 may be obtained. The configuration data in the compressed data block 1203 can be obtained through the bus DATA. The ECC code in each ECC code block 1202 can be obtained through the bus CODE. After obtaining the data, address and code, the ECC component 1224 generates an ECC confirmation for the data extracted from each data block 1202 according to the ECC mechanism. The ECC mechanism is used to generate an ECC code, and the ECC code is stored in the corresponding ECC code. Block 1202. The ECC element 1224 also compares the ECC confirmation with the corresponding ECC code of the array 1201 to generate an ECC syndrome. The ECC component 1224 further decodes the ECC syndrome to determine whether no error occurs, whether a correctable error occurs or an uncorrectable error occurs. The ECC element 1224 is also used to correct correctable errors. The uncorrected and corrected data are provided to the decompressor 1226 via the bus CDATA for the decompression described above. Uncorrectable errors are provided to decompressor 1226 via bus CDATA. The decompressor 1226 may cause the kernel 1220 to shut down or otherwise flag errors if an operationally critical portion of the configuration data is determined to be uncorrectable.

In a possible embodiment, the ECC component 124 includes at least one microcode program, which is used to execute the above-mentioned ECC function

The present invention and corresponding descriptions provide software or algorithms and symbols representing the manipulation of data bits in a computer memory. These contents and diagrams enable those skilled in the art to effectively convey related contents to others skilled in the art. Use the above algorithm to express a self-consistent order. The steps require physical-scale manipulations of physical quantities. Generally speaking, these physical quantities may be optical, electrical or magnetic signals, which can be stored, converted, integrated, compared and otherwise manipulated. Some of these signals will be referred to as bits, values, elements, symbols, properties, items, quantities or other related content for convenience.

However, it should be noted that these similar terms relate to physical quantities and are used only for convenience in describing these quantities. Unless specifically stated otherwise, the above terms (such as processing, estimating, calculating, judging, displaying, or other related terms) refer to the actions of a computer system, a microprocessor, a central processing unit, or similar electronic computing devices. And processing, which manipulates and converts data representing physical properties, registers, and memory quantities of a computer system to obtain data of physical quantities of memory, registers, or other similar information storage devices, or display devices of other similar computer systems.

It should be noted that the software implementation of the present invention is encoded on a program storage medium or other similar type of transmission medium. The program storage medium may be electronic (such as ROM, flash ROM, E-erasable ROM), random access memory magnetic (such as a floppy disk or a hard disk), or optical (such as CD-ROM CD ROM), and other read-only or random-access components. Likewise, the transmission medium may be metallic wire, twisted pair wire, coaxial cable, fiber optics, or other known similar transmission media. The present invention is not limited to these Examples.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined as defined by the appended claims.

Claims (18)

1. A processing device for providing configuration data to a microprocessor, the processing device comprising: A fuse array set, disposed on a die, and comprising: a first fuse array; and a second fuse array; and At least one core is disposed on the die, at least the core is coupled to the fuse array group, and includes: array control, which includes a configuration data register, the array control accesses the first and second fuse arrays, and processes a first state of the first fuse array and a state of the second fuse array according to the contents of the configuration data register second state, wherein the first fuse array is programmed according to a compressed configuration data of at least the core, and the contents of the configuration data register cause the array control to block access to the second fuse array and only allow access to the first fuse array , to know the first state, The processing device also includes a virtual fuse array, data of the virtual fuse array is compressed to generate the compressed configuration data, the virtual fuse array corresponds to at least the kernel. 2. The processing device of claim 1, wherein at least the core comprises an x86 compatible single-core or multi-core microprocessor. 3. The processing device of claim 1 , wherein the content of the configuration data register causes the array control to process the first state and the second state as an aggregated fuse array, the aggregated fuse array comprising at least the core's Configuration data is compressed, and the compressed configuration data is programmed into the first and the second fuse arrays. 4. The processing device as claimed in claim 1, wherein the content of the configuration data register causes the array control to process the first state and the second state as a plurality of redundant fuse arrays, the redundant fuses The array is programmed with a compressed configuration data of at least the core, and the array control includes a plurality of elements for OR logic operation of the first state and the second state. 5. The processing device of claim 1 , wherein the second fuse array is programmed according to at least the kernel's compressed configuration data, and the contents of the configuration data register cause the array control to block access to the first fuse array And only the access of the second fuse array is allowed to know the second status. 6. A processing method for providing configuration data to a microprocessor, the processing method comprising: setting a fuse array group on the die, wherein the fuse array group includes a first fuse array and a second fuse array; disposing at least one core on the die, at least the core being coupled to the fuse array; and using at least the core's array control to access and process the first state of the first fuse array and the second state of the second fuse array according to the contents of configuration data registers included in the array control, wherein the first fuse array is programmed according to at least the core's compressed configuration data, and the contents of the configuration data register cause the array control to block access to the second fuse array and only allow access to the first fuse array, for knowing the first state, The processing method also includes compressing data of a virtual fuse array corresponding to at least the kernel to generate the compressed configuration data. 7. The processing method of claim 6, wherein at least the core comprises an x86 compatible single-core or multi-core microprocessor. 8. The processing method as claimed in claim 6, wherein the content of the configuration data register causes the array control to process the first state and the second state as an aggregated fuse array, the aggregated fuse array including at least the core and the compressed configuration data is programmed into the first and the second fuse arrays. 9. The processing method as claimed in claim 6, wherein the content of the configuration data register makes the array control process the first state and the second state as a plurality of redundant fuse arrays, the redundant fuse array Programmed by a compressed configuration data of at least the core, and the array control includes a plurality of elements for performing an OR logic operation on the first state and the second state. 10. The processing method of claim 6, wherein the second fuse array is programmed according to at least the kernel's compressed configuration data, and the contents of the configuration data register cause the array control to block access to the first fuse array And only the access of the second fuse array is allowed to know the second status. 11. A processing device for providing configuration data to a microprocessor, the processing device comprising: a fuse array disposed on the die and including a plurality of semiconductor fuses programmed according to compressed configuration data; random access memory (RAM) disposed on the die; and a plurality of cores, respectively disposed on the die, wherein each core is coupled to the fuse array and the random access memory, and each of the cores is loaded into a data register according to the content accessing the fuse array or the random access memory to obtain the compressed configuration data, wherein the contents of the load data register specify the load order of each of the cores, and wherein the load sequence designates one of the cores as a master core, and upon a boot/reset operation, the master core reads the fuse array and writes the compressed configuration data to the random access memory, The data of the virtual fuse array is compressed to generate the compressed configuration data, and the virtual fuse array corresponds to the kernel. 12. The processing device of claim 11, wherein each of the kernels accesses and decompresses the compressed configuration data for initializing a plurality of elements of each of the kernels. 13. The processing device of claim 11 , wherein each of the cores comprises: The array control is used for reading the loading data register, and controlling the access of the fuse array or the random access memory according to the content of the loading data register. 14. The processing device as claimed in claim 11 , wherein the load order designates the rest of the cores as secondary cores, and after the primary core has written the compressed configuration data into the random access memory, every A kernel reads the random access memory according to the loading order to obtain the compressed configuration data. 15. A processing method for providing configuration data to a microprocessor, the processing method comprising: disposing a fuse array disposed on the die, wherein the fuse array includes a plurality of semiconductor fuses programmed according to compressed configuration data; setting random access memory (RAM) on the die; disposing a plurality of cores individually on the die, and coupling each core to the fuse array and the random access memory; and In a boot/reset operation, each of the cores accesses the fuse array or the random access memory according to the content of the loaded data register to know the compressed configuration data, wherein the contents of the load data register specify the load order of each of the cores, and wherein the load sequence designates one of the cores as a master core, and upon a boot/reset operation, the master core reads the fuse array and writes the compressed configuration data to the random access memory, The processing method further includes: compressing data of a virtual fuse array to generate the compressed configuration data, the virtual fuse array corresponding to the kernel. 16. The processing method of claim 15, wherein each of said kernels accesses and decompresses said compressed configuration data for initializing a plurality of elements of each of said kernels. 17. The processing method of claim 15, wherein each of said kernels comprises: The array control is used for reading the loading data register, and controlling the access of the fuse array or the random access memory according to the content of the loading data register. 18. The processing method as claimed in claim 15 , wherein the loading order specifies that the remaining cores in the cores are secondary cores, and after the primary core has written the compressed configuration data in the random access memory, every A kernel reads the random access memory according to the loading order to obtain the compressed configuration data.