CN104166343A - High-precision time synchronization system and method for distributed positioning system - Google Patents
High-precision time synchronization system and method for distributed positioning system Download PDFInfo
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Abstract
Disclosed are a high-precision time synchronization system and method for a distributed positioning system. The high-precision time synchronization system comprises a main processing device and a plurality of terminal processing devices in wireless communication with the main processing device. The terminal processing devices receive a reference frequency fixed message sent by the main processing device, and keep coincident with the main processing device in timing frequency; the main processing device allocates the timing sequence for the terminal processing devices; the terminal processing devices send a query message to the main processing device according to the timing sequence; the main processing device records the time when the query message is received, and sends a response message to the terminal processing devices; the terminal processing devices record the time when the response message is received, and calculate the time difference between the terminal processing devices and the main processing device according to a bidirectional time synchronization method, and time synchronization of the terminal processing devices and the main processing device is achieved. By means of the high-precision time synchronization system and method, the time synchronization precision can keep greater than 1 ns for a long time.
Description
Technical Field
The invention relates to a high-precision time synchronization system for a distributed positioning system and a synchronization method thereof.
Background
Distributed positioning systems are widely used in many fields, from daily mobile phone base station positioning to marine rescue satellite positioning systemsThe system, underground tunnel personnel, equipment positioning and the like are all applied. An important factor in positioning accuracy is the time synchronization error between the various stations. The error of time synchronization is generally proportional to the positioning error, e.g. 1A time error of 300m will bring a circular probability error.
Time synchronization by means of an external frequency source is the most widely used technical means today. The time synchronization is carried out through a satellite navigation system such as a GPS and a Beidou, and because the time synchronization is interfered by factors such as atmospheric ionosphere scattering and the like, the high precision can be achieved only in a statistical sense, the real-time updating cannot be achieved, the actual precision is difficult to exceed 100ns, and a great number of outliers are accompanied. The time service precision of the forwarding satellite is slightly high, but the time service precision can only reach the level of tens of nanoseconds. Other external timing means, e.g. long, short, low frequency time codes, with a precision of about 0.10.1s, which is far lower than the requirement of a positioning system. In addition, the common time synchronization system based on pseudo code phase measurement at present is difficult to achieve the accuracy of less than 5ns due to low chip phase resolution, and is difficult to maintain the time synchronization between stations after the time calibration is finished due to the lack of an effective time calibration protocol.
As described above, in the prior art, when the timing accuracy is better than 5ns and can be maintained for a long time, the implementation method and accuracy guarantee thereof are difficult to meet the requirements.
Disclosure of Invention
The invention provides a high-precision time synchronization system for a distributed positioning system and a synchronization method thereof, which can keep the time synchronization precision better than 1ns for a long time.
In order to achieve the above object, the present invention provides a high-precision time synchronization system for a distributed positioning system, the synchronization system comprising a main processing device and a plurality of terminal processing devices in wireless communication with the main processing device;
the circuit structure of the main processing device and the terminal processing device comprises:
an antenna;
a power amplifier module electrically connected to the antenna;
the up-down converter module is electrically connected with the power amplifier module;
the intermediate frequency transmitting, receiving and digital processing module is electrically connected with the upper and lower converter modules;
the intermediate frequency transmitting, receiving and digital processing module comprises:
the intermediate frequency receiving module is electrically connected with the output end of the upper and lower frequency converter module;
the intermediate frequency transmitting module is electrically connected with the input end of the upper and lower frequency converter modules;
the digital processing module is electrically connected with the output end of the intermediate frequency receiving module, the input end of the intermediate frequency transmitting module and the output end of the frequency controller;
the digital processing module also comprises a digital carrier tracking loop circuit, a pseudo code tracking loop circuit, a timing phase error estimation circuit and a timing clock.
The high-precision time synchronization system also comprises a power supply which is electrically connected with the power amplifier module, the up-down converter module and the intermediate frequency transmitting, receiving and digital processing module.
The power amplifier module comprises:
the duplexer is electrically connected with the antenna and performs bidirectional data transmission with the antenna;
an input amplifier electrically connected to the output terminal of the duplexer;
and the output amplifier is electrically connected with the input end of the duplexer.
The up-down converter module comprises:
the down converter is electrically connected with the output end of the input amplifier and the input end of the intermediate frequency receiving module;
the up-converter is electrically connected with the input end of the output amplifier and the input end of the intermediate frequency transmitting module;
and the frequency controller is electrically connected with the down converter, the up converter and the digital processing module.
The intermediate frequency receiving module comprises an analog-to-digital converter electrically connected with the output end of the down converter and a frequency mixing module electrically connected with the output end of the analog-to-digital converter; the intermediate frequency transmitting module comprises an amplifying filter electrically connected with the input end of the upper frequency converter and a digital-to-analog converter electrically connected with the input end of the amplifying filter.
The invention also provides a high-precision time synchronization method for the distributed positioning system, which comprises the following steps:
step S1, the main processing device transmits fixed information of the reference frequency to each terminal processing device, each terminal processing device receives the fixed information, obtains the timing frequency of the main processing device included in the fixed information through the pseudo tracking loop circuit, and keeps the timing frequency consistent with the timing frequency of the main processing device by adjusting the local timing clock;
the fixed information is a circularly played pseudo-random code sequence generated by the digital processing module according to the clock reference frequency of the main processing device;
step S2, the main processing device sends network access information to each terminal processing device, and assigns a timing sequence to each terminal processing device;
the network access message is a section of information sequence which is generated by a digital processing module of the main processing device and agreed with the terminal processing device;
at the initial moment of sending the network access message, clearing a timing clock of the main processing device;
and step S3, the terminal processing device adopts a bidirectional time synchronization method to sequentially realize time synchronization with the main processing device according to the timing sequence distributed by the main processing device.
The step S3 includes the following steps:
step S3.1, the terminal processing device sends inquiry information to the main processing device according to the sequence distributed by the main processing device;
the inquiry message includes a synchronization header and an inquiry message body, the synchronization header includes fixed information generated by the digital processing module based on the clock reference frequency of the main processing module as a reference frequency, the length of the fixed information is consistent with the length of the fixed information of the reference frequency sent by the main processing device in step S1, and the inquiry message body includes number information of the terminal processing device;
at the initial moment of sending the inquiry message body, clearing a timing clock of the terminal processing device;
s3.2, after the transmission time tp, the main processing device receives the inquiry message sent by the terminal processing device, and the main processing device calculates the arrival time of the inquiry message through the pseudo code tracking loop circuit；
The pseudo code tracking loop circuit calculates the total number of pseudo code periods generated by the pseudo code tracking loop circuit between the zero time of a timing clock of the main processing device and the last bit of the body of the received inquiry message, and converts the number of the pseudo code periods into the arrival time of the inquiry message；
Step S3.3, the main processing device sends a response message to the terminal processing device when the timing clock reaches td;
the response message includes the time when the main processor receives the inquiry message bodyAnd the number information of the terminal processing device;
s3.4, after the transmission time tp, the terminal processing device receives the response message, and the terminal processing device calculates the arrival time of the response message through the pseudo code tracking loop circuitAnd extracting the time from the response message；
The pseudo code tracking loop circuit calculates the total number of pseudo code periods generated by the pseudo code tracking loop circuit between the zero time of a timing clock of the terminal processing device and the last bit of the received response message body, and converts the number of the pseudo code periods into the arrival time of the response message；
Step S3.5, the digital processing module in the terminal processing device calculates the clock difference ∈ of the terminal processing device itself with respect to the main processing device:
；
wherein,is the time when the main processing device receives the inquiry message body sent by the terminal processing device,the time when the terminal processing device receives the response message sent by the main processing device is shown, and td is the interval time between the time when the main processing device clears the clock to send the response message to the terminal processing device;
and S3.6, adjusting the self timing clock by the digital processing module in the terminal processing device according to the clock difference epsilon so as to realize the precise synchronization of the timing clock and the main processing device.
After the main processing device transmits the response message to each terminal processing device in the gap and transmits the response message to all the terminal processing devices, the main processing device continuously transmits the fixed information of the reference frequency to each terminal processing device, each terminal processing device receives the fixed information, obtains the timing frequency of the main processing device contained in the fixed information through a pseudo code tracking loop circuit, and keeps the same with the timing frequency of the main processing device by adjusting a local timing clock.
The high-precision time synchronization method for the distributed positioning system adopts frequency division multiplexing and time division multiplexing;
the frequency division multiplexing is embodied as follows: the main processing device adopts a first frequency f1 to send a message to the terminal processing device, and the terminal processing device adopts a second frequency f2 to send the message to the main processing device;
the time division multiplexing is embodied as follows: when one terminal processing device completes the time synchronization operation with the main processing device, the other terminal processing device starts sending the inquiry message to the main processing device to start the time synchronization operation with the main processing device.
The high-precision time synchronization method of the distributed positioning system comprises the following steps:
the workflow of the generation of the transmission signal and the intermediate frequency transmission comprises the following steps aiming at the condition that the main processing device transmits a signal to the terminal processing device and the condition that the terminal processing device transmits a signal to the main processing device:
A. the digital processing module generates a transmitting signal, and 1023-time spread spectrum and DQPSK differential quadrature phase shift keying modulation are adopted for the transmitting signal;
B. the digital processing module respectively carries out spread spectrum, pulse shaping and difference filtering on baseband signals input into the I path and the Q path;
C. the digital processing module utilizes a numerically controlled oscillator NCO to carry out quadrature modulation on signals of the path I and the path Q;
D. the intermediate frequency transmitting module performs analog-to-digital conversion on the signals of the path I and the path Q by using an analog-to-digital converter;
E. the intermediate frequency transmitting module performs band-pass filtering on the signals of the path I and the path Q by using an amplifying filter and outputs the signals to the up-down converter module for transmission;
the intermediate frequency receiving and signal processing workflow of the received signal comprises the following steps for the condition that the main processing device receives the signal transmitted by the terminal processing device and the condition that the terminal processing device receives the signal transmitted by the main processing device:
A. the intermediate frequency receiving module respectively samples two paths of orthogonal signals subjected to down-conversion by the up-down converter module;
B. the intermediate frequency receiving module performs digital-to-analog conversion on the two paths of orthogonal signals by using a digital-to-analog converter;
C. the intermediate frequency receiving module carries out orthogonal frequency mixing on the two paths of orthogonal signals after the digital-to-analog conversion by using the frequency mixing module;
D. the digital processing module utilizes a timing phase error estimation circuit to eliminate the timing phase error of the signal after orthogonal frequency mixing;
E. the digital processing module despreads the two paths of signals with the timing phase error eliminated by using a pseudo code tracking loop circuit to obtain baseband signals;
F. the digital processing module utilizes a carrier tracking loop circuit to carry out carrier synchronization on the despread baseband signal, eliminates carrier frequency and phase errors of a local carrier and a received signal, reduces crosstalk between the I path signal and the Q path signal and maximizes the signal-to-noise ratio of the baseband signal;
G. the digital processing module utilizes a pseudo code tracking loop circuit to accurately measure the difference between the pseudo code phase of the received signal and the locally generated pseudo code phase, and corrects the phase of the local pseudo code through the difference so as to achieve the aim of keeping synchronization with the pseudo code of the received signal.
The pseudo code tracking loop circuit adopts a non-equivalent sampling technology, and achieves pseudo code phase resolution superior to one percent of chip precision.
The invention can keep the time synchronization precision better than 1ns for a long time.
Drawings
Fig. 1 is a block diagram of the present invention.
Fig. 2 is a circuit block diagram of the main processing device and the terminal device of the present invention.
Fig. 3 is a schematic diagram of the bidirectional time synchronization of the present invention.
Fig. 4 is a flow chart of the synchronization method of the present invention.
Fig. 5 is a flowchart for achieving bidirectional time synchronization between the terminal processing device and the main processing device.
Fig. 6 is an embodiment of the synchronization method of the present invention.
Fig. 7 is a flowchart of the generation of the transmission signal and the intermediate frequency transmission.
Fig. 8 is a flowchart of the intermediate frequency reception of the received signal and the signal processing.
FIG. 9 is a block diagram of a pseudo code tracking loop circuit employing a non-equal sampling technique.
Detailed Description
The preferred embodiment of the present invention will be described in detail below with reference to fig. 1 to 9.
As shown in fig. 1, the present invention provides a high-precision time synchronization system for a distributed positioning system, which comprises a main processing device 1 and a plurality of terminal processing devices 2 in wireless communication with the main processing device 1.
The main processing device is used for controlling and managing each terminal processing device, such as the access of a network and the starting of time correction; the system is responsible for receiving timing inquiry information sent by each terminal processing device, obtaining the accurate arrival time of the timing inquiry information through pseudo code phase measurement, packaging the time information in a response signal and sending the response signal back to the terminal processing device; providing accurate reference frequencies to each terminal processing device through wireless broadcasting; the second pulse is output to trigger the positioning equipment to sample data.
The terminal processing device is used for receiving a control signal of the main processing device and sending timing inquiry information according to a time slot allocated by the main processing device after accessing a timing network; measuring the arrival time of the received response signal of the main processing device, and calculating and correcting the timing starting point difference between the response signal and the main processing device by taking out the time information contained in the response packet; after timing is completed, the reference frequency broadcasted by the main processing device is received and processed, and the timing frequency of the main processing device is kept consistent.
As shown in fig. 2, the circuit configurations of the main processing device 1 and the terminal processing device 2 both include:
an antenna 3;
a power amplifier module 4 electrically connected to the antenna 3;
an up-down converter module 5 electrically connected with the power amplifier module 4;
the intermediate frequency transmitting, receiving and digital processing module 6 is electrically connected with the upper and lower converter modules 5;
and a power supply 7 electrically connected with the power amplifier module 4, the up-down converter module 5 and the intermediate frequency transmitting, receiving and digital processing module 6.
The intermediate frequency transmitting and receiving and digital processing module 6 completes the functions of interface data exchange, baseband signal processing, intermediate frequency modulation and demodulation, bidirectional time synchronization and the like. Intermediate frequency signals generated by the intermediate frequency transmitting, receiving and digital processing module 6 are subjected to up-conversion by the up-down converter module 5, are subjected to power amplification by the power amplifier module 4, are radiated by the antenna 3, are received by the antenna 3, are subjected to power amplification by the power amplifier module 4, and are subjected to down-conversion by the up-down converter module 5 to form intermediate frequency signals, and the intermediate frequency signals are output to the intermediate frequency transmitting, receiving and digital processing module 6 for processing.
The power amplifier module 4 comprises:
a duplexer 403 electrically connected to the antenna 3, the duplexer 403 performing bidirectional data transmission with the antenna 3;
an input amplifier 401 electrically connected to the output terminal of the duplexer 403;
an output amplifier 402 electrically connected to the input terminal of the duplexer 403.
The up-down converter module 5 comprises:
a down converter 501 electrically connected to the output terminal of the input amplifier 401;
an up-converter 502 electrically connected to the input of the output amplifier 402;
a frequency controller 503 (providing a clock reference frequency) electrically connecting the down-converter 501 and the up-converter 502.
The intermediate frequency transmitting, receiving and digital processing module 6 comprises:
an intermediate frequency receiving module 601 electrically connected to the output end of the down converter 501;
an intermediate frequency transmitting module 602 electrically connected to the input end of the upper frequency converter 502;
and the digital processing module 603 is electrically connected to the output end of the intermediate frequency receiving module 601, the input end of the intermediate frequency transmitting module 602, and the output end of the frequency controller 503.
The intermediate frequency receiving module 601 comprises an analog-to-digital converter electrically connected to the output end of the down converter 501, and a frequency mixing module electrically connected to the output end of the analog-to-digital converter;
the if transmitting module 602 includes an amplifying filter electrically connected to the input end of the upper converter 502 and a digital-to-analog converter electrically connected to the input end of the amplifying filter.
The digital processing module 603 further includes a digital carrier tracking loop circuit, a pseudo code tracking loop circuit, a timing phase error estimation circuit, and a timing clock.
In this embodiment, the model of the frequency mixing module is XBH-101-1, and the digital processing module 603 adopts an FPGA (Field Programmable gate Array).
As shown in fig. 3, the principle of two-way time synchronization is shown. Wherein,is the time of arrival of the inquiry message as determined by the main processing means,is the time of arrival of the reply message as determined by the terminal processing means,in order to interrogate for the duration of the message,for the propagation time of the reply message, the value of which includes the true value of the propagation timeAnd propagation time errorI.e. by，εIs the initial time offset between the main processing device and the terminal processing device. Wherein,the terminal processing device is based onCan calculate the timing deviation of the terminal, and the terminal processing device can calculate the timing deviation according to the timing deviationεAnd adjusting the clock of the self to realize fine synchronization. As can be seen from the above process, the clock error is obtainedεThe distance delay is eliminated in the process, so that the system error caused by the signal propagation distance between the main processing device and the terminal processing device can be eliminated by adopting a two-way time synchronization method.
As shown in fig. 4, the present invention provides a high-precision time synchronization method for a distributed positioning system, which includes the following steps:
step S1, the main processing device transmits fixed information of the reference frequency to each terminal processing device, each terminal processing device receives the fixed information, obtains the timing frequency of the main processing device included in the fixed information through the pseudo tracking loop circuit, and keeps the timing frequency consistent with the timing frequency of the main processing device by adjusting the local timing clock;
the fixed information is a circularly played pseudo-random code sequence generated by the digital processing module according to the clock reference frequency of the main processing device;
a DDS (Direct Digital Synthesizer) circuit is adopted as a timing clock in the terminal processing device and is realized by programming in the Digital processing module;
step S2, the main processing device sends network access information to each terminal processing device, and assigns a timing sequence to each terminal processing device;
the network access message is a section of information sequence which is generated by a digital processing module of the main processing device and agreed with the terminal processing device;
at the initial moment of sending the network access message, clearing a timing clock of the main processing device;
step S3, the terminal processing device adopts a bidirectional time synchronization method to realize time synchronization with the main processing device in sequence according to the timing sequence distributed by the main processing device;
as shown in fig. 5, the step S3 includes the following steps:
step S3.1, the terminal processing device sends inquiry information to the main processing device according to the sequence distributed by the main processing device;
the inquiry message includes a synchronization header and an inquiry message body, the synchronization header includes fixed information generated by the digital processing module based on the clock reference frequency of the main processing module as a reference frequency, the length of the fixed information is consistent with the length of the fixed information of the reference frequency sent by the main processing device in step S1, and the inquiry message body includes number information of the terminal processing device; at the initial moment of sending the inquiry message body, clearing a timing clock of the terminal processing device;
step S3.2, passing transmission time tpThe main processor receives the inquiry message from the terminal processor and calculates the arrival time of the inquiry message by the pseudo-code tracking loop circuit；
The pseudo code tracking loop circuit calculates the total number of pseudo code periods generated by the pseudo code tracking loop circuit between the zero time of a timing clock of the main processing device and the last bit of the body of the received inquiry message, and converts the number of the pseudo code periods into the arrival time of the inquiry message；
Step S3.3, the main processing device reaches t when its timing clock reaches tdThen, sending a response message to the terminal processing device;
the response message includes the time when the main processor receives the inquiry message bodyAnd the number information of the terminal processing device;
step S3.4, passing transmission time tpThe terminal processing device receives the response message, and calculates the arrival time of the response message through the pseudo code tracking loop circuitAnd extracting the time from the response message；
The pseudo code tracking loop circuit calculates the total number of pseudo code periods generated by the pseudo code tracking loop circuit between the zero time of a timing clock of the terminal processing device and the last bit of the received response message body, and converts the number of the pseudo code periods into the arrival time of the response message；
Step S3.5, the digital processing module in the terminal processing device calculates the clock difference ∈ of the terminal processing device itself with respect to the main processing device:
；
wherein,is the time when the main processing device receives the inquiry message body sent by the terminal processing device,is the time when the terminal processing device receives the response message sent by the main processing device, tdIs the interval time between the main processing device clearing from its timing clock to sending the response message to the terminal processing device;
and S3.6, adjusting the self timing clock by the digital processing module in the terminal processing device according to the clock difference epsilon so as to realize the precise synchronization of the timing clock and the main processing device.
In the high-precision time synchronization method for the distributed positioning system, after the main processing device sends a gap of a response message to each terminal processing device and sends the response message to all the terminal processing devices, the main processing device continuously sends fixed information of a reference frequency to each terminal processing device, each terminal processing device receives the fixed information, a timing frequency of the main processing device contained in the fixed information is obtained through a pseudo code tracking loop circuit, and the timing frequency of the main processing device is kept consistent with the timing frequency of the main processing device by adjusting a local timing clock.
In the high-precision time synchronization method for the distributed positioning system, the main processing device sends a message to the terminal processing device by using the first frequency f1, and the terminal processing device sends a message to the main processing device by using the second frequency f 2.
As shown in fig. 6, a high-precision time synchronization method according to the present invention is described by taking a main processing device and two terminal processing devices as an example, and the synchronization method implements a bidirectional timing mechanism between the main processing device and the plurality of terminal processing devices by frequency division multiplexing and time division multiplexing. The frequency division multiplexing is expressed that the transmitting frequency of the main processing device is f1, and the transmitting frequency of the terminal processing device is f 2; time division multiplexing is represented by two terminal processing devices respectively transmitting timing inquiry information in complementary overlapping time regions. By the method, the interference between the uplink and the downlink and the uplink of each terminal processing device is effectively avoided. The specific implementation mode is as follows: fixed information (reference frequency) is first broadcast by the main processing means at frequency f1 to assist the receivers of the two terminal processing means in signal synchronization, including timing synchronization, carrier synchronization and code loop synchronization. The duration of broadcasting the fixed information is related to the specific algorithm and hardware adopted by the terminal processing device, and usually 10-30 s can satisfy the above conditions. The main processing unit then broadcasts an incoming message at frequency f1, which specifies the timing sequence of the two terminal processing units. Meanwhile, at the initial moment of broadcasting the network access message, the main processing device clears the local timing clock. Upon receiving the network access message, the terminal processing apparatus 1 starts to transmit an inquiry message at frequency f 2. The query message consists of a synchronization header and a query message body. The function of the synchronous head is the same as the fixed information of the main processing device, so the synchronous head is a preset fixed sequence, and the length of the synchronous head is the same as the fixed information of the main processing device; the inquiry message body includes information such as the number of the terminal processing device. At the time of sending the inquiry message, the terminal processing device 1 clears the local timer clock. Elapsed transmission time t1pThe main processing device receives the inquiry message sent by the terminal processing device 1, and records the time when the main processing device receives the inquiry message(ii) a Next, the master processing device arrives at the local clockThen, a response message is sent. The response message includesAnd the number of the terminal processing device 1. Elapsed transmission time t1pThe terminal processing device 1 receives the response message, the terminal processing device 1 receives the time of the response messageRecorded in association with the extracted reply messageSubstituting into formulaThe clock difference of the terminal processing device 1 relative to the main processing device can be calculated. The terminal processing apparatus 2 waits for a certain period of time after receiving the network access message, and then transmits an inquiry message at the frequency point f2, similarly to the terminal processing apparatus 1. At the time of sending the inquiry message, the terminal processing device 2 clears the local timer clock. Elapsed transmission time t2pThe main processing device receives the inquiry message sent by the terminal processing device 2 and records the time when the main body of the inquiry message is received(ii) a Then, the local clock arrivesThe main processing device then sends a response message. The response message includesAnd the number of the terminal processing device 2. Elapsed transmission time t2pThe terminal processing device 2 receives the response message and the time when the response message is receivedRecorded in association with the extracted reply messageSubstituting into formulaThe clock difference of the master processing device relative to the clock difference can be calculated. The main processing device continues to transmit a fixed sequence (broadcast fixed information) after transmitting the response message to the two terminal processing devices in the gap and after transmitting the response message, so as to help the two terminal processing devices keep consistent timing frequency with the main processing device all the time.
The antenna 3, the power amplifier module 4, the up-down converter module 5, the intermediate frequency receiving module 601 and the intermediate frequency transmitting module 602 in the main processing device 1 are responsible for sending fixed information of reference frequency, network access information and response information through a wireless link and receiving inquiry information of a terminal processing device; the digital processing module 603 in the main processing device 1 generates fixed information of reference frequency and network access message, processes the received baseband signal (inquiry information), performs signal pseudo code phase measurement on the received inquiry message through the pseudo code tracking loop circuit to obtain the arrival time of the inquiry message, and packs the time information in the response message.
The antenna 3, the power amplifier module 4, the up-down converter module 5, the intermediate frequency receiving module 601 and the intermediate frequency transmitting module 602 in the terminal processing device 2 are responsible for sending inquiry messages through a wireless link and receiving fixed information of reference frequency, network access messages and response messages sent by a main processing device; the digital processing module 603 in the terminal processing device 2 generates an inquiry message, processes the received baseband signal (fixed information, network access message, and response message), extracts the arrival time of the inquiry message included in the response message sent by the main processing device, and performs pseudo code phase measurement on the received response message through the pseudo code tracking loop circuit to obtain the arrival time of the response message.
As shown in fig. 7, the workflow of generating the transmission signal and transmitting the intermediate frequency signal includes the following steps:
A. the digital processing module 603 generates a transmission signal, and 1023-time spread spectrum and DQPSK (differential quadrature phase shift keying) modulation are adopted for the transmission signal;
B. the digital processing module 603 performs spread spectrum, pulse shaping and difference filtering on the baseband signals input to the I path and the Q path respectively;
C. the digital processing module 603 performs quadrature modulation on the I-path and Q-path signals using a Numerically Controlled Oscillator (NCO);
D. the intermediate frequency transmitting module 602 performs analog-to-digital conversion on the I path signal and the Q path signal by using an analog-to-digital converter;
E. the intermediate frequency transmitting module 602 performs band-pass filtering on the I path and the Q path signals by using an amplifying filter, and outputs the signals to the up-down converter module 5 for transmission.
The input rates of the I path and Q path baseband signals are respectively 10kbps, the chip rate after spread spectrum is 10.23MHz, the QPSK (quadrature phase shift keying) signal modulation rate synthesized by the I path and Q path baseband signals is 20.46MHz, a root-raised cosine filter with a roll-off coefficient of 0.5 is adopted for pulse forming, the 3dB bandwidth is about 15MHz, and the central frequency of quadrature modulation of a digital control oscillator is 75 MHz.
As shown in fig. 8, the workflow of the intermediate frequency reception and signal processing of the received signal comprises the following steps:
A. the intermediate frequency receiving module 601 respectively samples two paths of orthogonal signals which are subjected to down-conversion by the up-down converter module 5;
B. the intermediate frequency receiving module 601 performs digital-to-analog conversion on the two paths of orthogonal signals by using a digital-to-analog converter;
C. the intermediate frequency receiving module 601 performs orthogonal frequency mixing on the two paths of orthogonal signals after digital-to-analog conversion by using a frequency mixing module;
D. the digital processing module 603 eliminates the timing phase error of the quadrature-mixed signal by using a timing phase error estimation circuit;
E. the digital processing module 603 despreads the two paths of signals with the timing phase error removed by using a pseudo code tracking loop circuit to obtain baseband signals;
F. the digital processing module 603 performs carrier synchronization on the despread baseband signal by using a carrier tracking loop circuit, eliminates carrier frequency and phase errors of a local carrier and a received signal, reduces crosstalk between the I-path signal and the Q-path signal, and maximizes the signal-to-noise ratio of the baseband signal;
G. the digital processing module 603 accurately measures the difference between the pseudo code phase of the received signal and the locally generated pseudo code phase by using the pseudo code tracking loop circuit, and corrects the phase of the local pseudo code according to the difference so as to achieve the purpose of keeping synchronization with the pseudo code of the received signal.
The carrier tracking adopted by the invention is a structure of a digital two-order frequency-locked loop auxiliary three-order phase-locked loop, and the pseudo code tracking adopts a digital delay lagging second-order tracking loop. Both loops are implemented by programming on an FPGA (Field Programmable gate Array). The carrier tracking loop circuit has the function of pulling the multi-frequency offset into the linear range of carrier tracking, so that the time resolution of the pseudo code tracking loop circuit can be improved. The timing phase error estimation circuit is also programmed into the FGPA based on a sophisticated difference filtering algorithm.
As shown in fig. 9, a block diagram of a pseudo code tracking loop circuit employing a non-equal sampling technique is shown. The working principle of the pseudo code tracking loop circuit is as follows: multiplying the input signals of the I path and the Q path by the carrier reproduced by the carrier tracking loop circuit to recover baseband signals (multiplying the signals of the I path by the SIN reproduced carrier to recover signals of the I path of the baseband, multiplying the signals of the Q path by the COS reproduced carrier to recover signals of the Q path of the baseband); the signals of the I path and the Q path of the baseband are respectively multiplied by the output E of a local pseudo code generator controlled and output by a numerical control oscillator (code NCO); the function of the 2-bit shift register is to generate a leading and lagging output of a clock to the pseudo-code generator; p represents an advanced local pseudo code, E represents a current local pseudo code, and L represents a delayed local pseudo code; the multiplication results of signals of a base band I path and a base band Q path and advanced, current and lagging local pseudo codes enter an integrating and clearing device, the integrating and clearing device carries out integration operation according to the period of the pseudo random codes, and then clearing the integration results; after each pseudo code period is finished, the code ring discriminator compares E, P, L integral results of each path, converts the difference between the path E and the path P into carrier frequency deviation, converts the difference between the path P and the path L into the deviation of code NCO, and sends the result to the code ring filter; the results output by the code loop filter are respectively used for correcting the carrier frequency deviation and the deviation of a numerical control oscillator (code NCO), so that the phase of the local pseudo code is consistent with that of the pseudo code contained in the received signal, and then the operation of the next pseudo code period is carried out. The combination of the code loop discriminator and the code loop filter determines its thermal noise error and maximum line-of-sight direction dynamic stress threshold. The phase detection algorithm applied by the code loop discriminator is a non-coherent lead minus lag envelope normalized by a lead plus lag envelope. The phase discrimination algorithm adopts an inverse-orthonormal method, the algorithm reduces the sensitivity to amplitude, and the phase discrimination precision of the algorithm is ensured by using a non-equivalent sampling technology. A second-order loop filter is adopted as a code loop filter of the pseudo code tracking loop circuit. In terms of sampling rate, the pseudo code tracking loop circuit samples the 10.23MHz pseudo code with a sampling rate of 100 MHz. The sampling frequency is relatively prime to the pseudo-code rate on the premise that the Nyquist sampling condition is satisfied. By this approach, the pseudo code tracking loop can achieve a time resolution better than the chip rate 1/100. If integer-times sampling is used, the sampling rate needs to be at least over 4GHz to achieve such resolution, which is difficult to achieve at the current circuit level. The sampling method of the invention can be used to obtain high-precision time resolution with little time cost.
The invention realizes the comprehensive action of the digital carrier tracking loop and the pseudo code tracking loop by programming in the FPGA, measures the frequency and phase difference between the local carrier and the received signal carrier through the digital carrier tracking loop, eliminates the signal crosstalk caused by the error and increases the signal-to-noise ratio of the signal, accurately measures the difference between the pseudo code phase of the received signal and the pseudo code phase generated locally through the pseudo code tracking loop circuit on the basis, and corrects the phase of the local pseudo code through the difference so as to achieve the aim of keeping synchronization with the pseudo code of the received signal. The pseudo code tracking loop circuit adopts a non-equivalent sampling technology, achieves pseudo code phase resolution superior to one percent of chip precision, and provides a foundation for time synchronization precision superior to 1ns in precision.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (10)
1. A high-precision time synchronization system for a distributed positioning system is characterized by comprising a main processing device (1) and a plurality of terminal processing devices (2) which are in wireless communication with the main processing device (1);
the circuit structure of the main processing device (1) and the terminal processing device (2) comprises:
an antenna (3);
a power amplifier module (4) electrically connected to the antenna (3);
an up-down converter module (5) electrically connected with the power amplifier module (4);
the intermediate frequency transmitting, receiving and digital processing module (6) is electrically connected with the upper and lower converter module (5);
the intermediate frequency transmitting, receiving and digital processing module (6) comprises:
the intermediate frequency receiving module (601) is electrically connected with the output end of the upper and lower converter module (5);
the intermediate frequency transmitting module (602) is electrically connected with the input end of the upper and lower frequency converter module (5);
the digital processing module (603) is electrically connected with the output end of the intermediate frequency receiving module (601), the input end of the intermediate frequency transmitting module (602) and the output end of the frequency controller (503);
the digital processing module (603) also comprises a digital carrier tracking loop circuit, a pseudo code tracking loop circuit, a timing phase error estimation circuit and a timing clock.
2. A high accuracy time synchronization system for distributed positioning systems as in claim 1, further comprising a power supply (7) electrically connected to the power amplifier module (4), the up-down converter module (5) and the intermediate frequency transmit receive and digital processing module (6).
3. A high accuracy time synchronization system for distributed positioning systems as in claim 1, characterized by said power amplifier module (4) comprising:
a duplexer (403) electrically connected to the antenna (3), the duplexer (403) performing bidirectional data transmission with the antenna (3);
an input amplifier (401) electrically connected to the output terminal of the duplexer (403);
an output amplifier (402) electrically connected to the input terminal of the duplexer (403);
the up-down converter module (5) comprises:
the down converter (501) is electrically connected with the output end of the input amplifier (401) and the input end of the intermediate frequency receiving module (601);
an up-converter (502) electrically connected to the input of the output amplifier (402) and the input of the intermediate frequency transmission module (602);
a frequency controller (503) electrically connected to the down-converter (501), the up-converter (502) and the digital processing module (603).
4. A high accuracy time synchronization system for a distributed positioning system as defined in claim 3, wherein said intermediate frequency receiving module (601) comprises an analog-to-digital converter electrically connected to the output of the down-converter (501) and a mixing module electrically connected to the output of the analog-to-digital converter; the intermediate frequency transmitting module (602) comprises an amplifying filter electrically connected with the input end of the upper frequency converter (502) and a digital-to-analog converter electrically connected with the input end of the amplifying filter.
5. A high accuracy time synchronization method for a distributed positioning system according to any of claims 1-4, characterized in that the method comprises the steps of:
step S1, the main processing device (1) sends fixed information of reference frequency to each terminal processing device (2), each terminal processing device (2) receives the fixed information, obtains the timing frequency of the main processing device contained in the fixed information through a pseudo code tracking loop circuit, and keeps consistent with the timing frequency of the main processing device by adjusting a local timing clock;
the fixed information is a circularly played pseudo-random code sequence generated by the digital processing module according to the clock reference frequency of the main processing device;
step S2, the main processing device (1) sends a network access message to each terminal processing device (2), and assigns a time correction sequence to each terminal processing device (2);
the network access message is a section of information sequence which is generated by a digital processing module (603) of the main processing device and is agreed with the terminal processing device;
at the initial moment of sending the network access message, clearing a timing clock of the main processing device;
and step S3, the terminal processing device (2) adopts a bidirectional time synchronization method to realize time synchronization with the main processing device in sequence according to the timing sequence distributed by the main processing device.
6. The method for highly accurate time synchronization of distributed positioning systems as claimed in claim 5, wherein said step S3 comprises the steps of:
step S3.1, the terminal processing device (2) sends an inquiry message to the main processing device (1) according to the sequence distributed by the main processing device;
the inquiry message includes a synchronization header and an inquiry message body, the synchronization header includes fixed information generated by the digital processing module based on the clock reference frequency of the main processing module as a reference frequency, the length of the fixed information is consistent with the length of the fixed information of the reference frequency sent by the main processing device in step S1, and the inquiry message body includes number information of the terminal processing device;
at the initial moment of sending the inquiry message body, the timing clock of the terminal processing device (2) is cleared;
step S3.2, after the transmission time tp, the main processing device (1) receives the inquiry message sent by the terminal processing device, and the main processing device (1) calculates the arrival time of the inquiry message through a pseudo code tracking loop circuit；
The pseudo code tracking loop circuit calculates the total number of pseudo code periods generated by the pseudo code tracking loop circuit between the zero time of a timing clock of the main processing device and the last bit of the body of the received inquiry message, and converts the number of the pseudo code periods into the arrival time of the inquiry message；
Step S3.3, when the timing clock of the main processing device (1) reaches td, sending a response message to the terminal processing device (2);
the response message includes the time when the main processor receives the inquiry message bodyAnd the number information of the terminal processing device;
s3.4, after the transmission time tp, the terminal processing device (2) receives the response message, and the terminal processing device (2) calculates the arrival time of the response message through a pseudo code tracking loop circuitAnd extracting the time from the response message；
The pseudo code tracking loop circuit calculates the total number of pseudo code periods generated by the pseudo code tracking loop circuit between the zero time of a timing clock of the terminal processing device and the last bit of the received response message body, and converts the number of the pseudo code periods into the arrival time of the response message；
Step S3.5, the digital processing module (603) in the terminal processing device calculates the clock difference e of the terminal processing device itself with respect to the main processing device:
；
wherein,is received by the main processing device at the terminalThe time of the body of the inquiry message sent by the physical device,the time when the terminal processing device receives the response message sent by the main processing device is shown, and td is the interval time between the time when the main processing device clears the clock to send the response message to the terminal processing device;
and S3.6, adjusting the self timing clock by the digital processing module (603) in the terminal processing device according to the clock difference epsilon so as to realize the precise synchronization with the timing clock of the main processing device.
7. The method of highly accurate time synchronization in a distributed positioning system according to claim 6, wherein the main processing device (1) continues to transmit the fixed information of the reference frequency to each of the terminal processing devices (2) after transmitting the response message to each of the terminal processing devices (2) and after transmitting the response message to all of the terminal processing devices (2), each of the terminal processing devices (2) receives the fixed information, obtains the timing frequency of the main processing device included in the fixed information by the pseudo code tracking loop circuit, and keeps the timing frequency of the main processing device consistent with the timing frequency of the main processing device by adjusting the local timing clock.
8. The method for high precision time synchronization of a distributed positioning system as claimed in claim 7, wherein the method for high precision time synchronization of a distributed positioning system employs frequency division multiplexing and time division multiplexing;
the frequency division multiplexing is embodied as follows: the main processing device (1) transmits a message to the terminal processing device (2) by using the first frequency f1, and the terminal processing device (2) transmits a message to the main processing device (1) by using the second frequency f 2;
the time division multiplexing is embodied as follows: when one terminal processing device (2) completes the time synchronization operation with the main processing device (1), the other terminal processing device (2) starts sending the inquiry message to the main processing device (1) and starts the time synchronization operation with the main processing device (1).
9. The method for high precision time synchronization of a distributed positioning system as claimed in claim 8, wherein said method for high precision time synchronization of a distributed positioning system comprises:
the workflow of the generation of the transmission signal and the intermediate frequency transmission comprises the following steps for the situation that the main processing device (1) transmits the signal to the terminal processing device (2) and the situation that the terminal processing device (2) transmits the signal to the main processing device (1):
A. a digital processing module (603) generates a transmitting signal, and 1023-time spread spectrum and DQPSK differential quadrature phase shift keying modulation are adopted for the transmitting signal;
B. the digital processing module (603) respectively carries out spread spectrum, pulse shaping and difference filtering on baseband signals input into the I path and the Q path;
C. the digital processing module (603) utilizes a numerically controlled oscillator NCO to carry out quadrature modulation on signals of the I path and the Q path;
D. the intermediate frequency transmitting module (602) performs analog-to-digital conversion on the signals of the path I and the path Q by using an analog-to-digital converter;
E. the intermediate frequency transmitting module (602) performs band-pass filtering on the signals of the path I and the path Q by using an amplifying filter and outputs the signals to the up-down converter module (5) for transmission;
the work flow of the intermediate frequency receiving and the signal processing of the received signal comprises the following steps for the case that the main processing device (1) receives the signal transmitted by the terminal processing device (2) and the case that the terminal processing device (2) receives the signal transmitted by the main processing device (1):
A. the intermediate frequency receiving module (601) respectively samples two paths of orthogonal signals subjected to down-conversion by the up-down converter module (5);
B. the intermediate frequency receiving module (601) performs digital-to-analog conversion on the two paths of orthogonal signals by using a digital-to-analog converter;
C. the intermediate frequency receiving module (601) carries out orthogonal frequency mixing on the two paths of orthogonal signals after the digital-to-analog conversion by using the frequency mixing module;
D. a digital processing module (603) eliminates the timing phase error of the quadrature mixed signal by using a timing phase error estimation circuit;
E. the digital processing module (603) despreads the two paths of signals with the timing phase error eliminated by using a pseudo code tracking loop circuit to obtain baseband signals;
F. the digital processing module (603) utilizes a carrier tracking loop circuit to carry out carrier synchronization on the despread baseband signal, eliminates carrier frequency and phase errors of a local carrier and a received signal, reduces crosstalk between an I path signal and a Q path signal, and maximizes the signal-to-noise ratio of the baseband signal;
G. the digital processing module (603) utilizes the pseudo code tracking loop circuit to accurately measure the difference between the pseudo code phase of the received signal and the locally generated pseudo code phase, and corrects the phase of the local pseudo code through the difference so as to achieve the purpose of keeping synchronization with the pseudo code of the received signal.
10. A method for highly accurate time synchronization of a distributed positioning system as defined in claim 9 wherein said pseudo code tracking loop circuit employs a non-equal sampling technique to achieve pseudo code phase resolution better than one percent chip accuracy.
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