CN104158535B - FV convertor - Google Patents

Abstract

A frequency-to-voltage converter is provided, including: a constant current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first voltage storage, a second voltage storage, and a third voltage storage, wherein , the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are conducted under the control of the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, and the fifth clock signal respectively. On or off to generate a voltage corresponding to the frequency of the incoming clock signal.

Description

Frequency to Voltage Converter

technical field

The present invention relates to a converter, and more particularly to a frequency-to-voltage converter.

Background technique

Frequency-to-voltage converters are widely used in the control process of control equipment such as speed sensors, tachometers, and cruise control. Therefore, the conversion accuracy of the frequency-to-voltage converter directly affects the control accuracy of the control equipment. However, currently used frequency-to-voltage converters are easily affected by process, power supply voltage, and ambient temperature during operation, thereby affecting the conversion accuracy of converting frequency to voltage.

Therefore, there is a need for a frequency-to-voltage converter with high conversion accuracy.

Contents of the invention

The object of the present invention is to provide a frequency-to-voltage converter, thereby improving the conversion accuracy of converting frequency into voltage.

The present invention provides a frequency-to-voltage converter, including: a constant current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first voltage storage, a second voltage storage, and a third voltage storage , wherein the first connection end of the first switch is connected to the constant current source, the second connection end of the first switch is grounded, the control end of the first switch receives the first clock signal, and the first connection end of the second switch is connected to the constant current source. The current source, the second connection terminal of the second switch is connected to the first terminal of the first voltage storage, the second terminal of the first voltage storage is grounded, the control terminal of the second switch receives the second clock signal, and the first terminal of the third switch The connection terminal is connected to the constant current source, the second connection terminal of the third switch is connected to the first terminal of the second voltage storage, the second terminal of the second voltage storage is grounded, the control terminal of the third switch receives the third clock signal, and the second connection terminal of the third switch receives the third clock signal. The first connection terminal of the four switches is connected to the first terminal of the second voltage storage, the second connection terminal of the fourth switch is connected to the first terminal of the third voltage storage, the second terminal of the third voltage storage is grounded, and the fourth switch The control end of the fifth switch receives the fourth clock signal, the first connection end of the fifth switch is connected to the first end of the second voltage storage, the second connection end of the fifth switch is grounded, and the control end of the fifth switch receives the fifth clock signal.

Optionally, the first end of the third voltage storage is used as an output end, the first switch is turned on in response to the effective level of the first clock signal received by the control end of the first switch, and the second switch is turned on in response to the The active level of the second clock signal received by the control end is turned on, the third switch is turned on in response to the active level of the third clock signal received by the control end of the third switch, and the fourth switch responds to the active level of the fourth switch The active level of the fourth clock signal received by the control end is turned on, and the fifth switch is turned on in response to the active level of the fifth clock signal received by the control end of the fifth switch.

Optionally, it also includes: a clock circuit, which generates a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal based on an input signal, wherein the first clock signal to the fifth clock signal The signals have the same frequency, and the start time and end time of the active level of the first clock signal to the fifth clock signal cycle in the following order: the end time of the active level of the fifth clock signal < the active level of the third clock signal Flat start time < end time of active level of the first clock signal < end time of active level of the third clock signal < start time of active level of the first clock signal ≤ active level of the second clock signal end time < the end time of the active level of the fourth clock signal < the start time of the active level of the fifth clock signal, and the start time of the active level of the second clock signal ≤ the active level of the fifth clock signal end time, or, the end time of the active level of the fifth clock signal < the start time of the active level of the second clock signal < the start time of the active level of the third clock signal, and the active level of the third clock signal Flat end time < start time of active level of the fourth clock signal < start time of active level of the first clock signal, or, start time of active level of the first clock signal ≤ effective level of the fourth clock signal flat start time≤the end time of the active level of the second clock signal, or, the end time of the active level of the second clock signal<the start time of the active level of the fourth clock signal<the active level of the fourth clock signal flat end time, wherein each cycle of the first clock signal to the fifth clock signal includes an active level and an inactive level, and the first switch responds to the inactive level of the first clock signal received by the control terminal of the first switch. The active level is turned off, the second switch is turned off in response to the non-active level of the second clock signal received by the control end of the second switch, and the third switch responds to the third clock signal received by the control end of the third switch The inactive level of the fourth switch is turned off, the fourth switch is turned off in response to the inactive level of the fourth clock signal received by the control terminal of the fourth switch, and the fifth switch responds to the fifth clock signal received by the control terminal of the fifth switch. The inactive level of the clock signal is disconnected.

Optionally, the active level of the first clock signal is one of high level and low level, the inactive level of the first clock signal is the other one of high level and low level, and the second clock signal The active level of the clock signal is one of high level and low level, the inactive level of the second clock signal is the other of high level and low level, and the active level of the third clock signal is high level and one of low level, the inactive level of the third clock signal is the other of high level and low level, and the active level of the fourth clock signal is one of high level and low level, The inactive level of the fourth clock signal is the other of high level and low level, the active level of the fifth clock signal is one of high level and low level, and the inactive level of the fifth clock signal is one of high level and low level. Level is the other of high level and low level.

Optionally, the frequencies of the first clock signal to the fifth clock signal respectively have a monotone function relationship with the frequency of the input signal.

Optionally, the clock circuit includes: a phase shifting unit, which uses the input signal to generate a sixth clock signal, a seventh clock signal, and an eighth clock signal with the same frequency, wherein the ratio of the sixth clock signal to the eighth clock signal is The duty cycle is the same, and the start time of the active level of the seventh clock signal is within the duration of the active level of the sixth clock signal, and the start time of the active level of the eighth clock signal is within the active level of the seventh clock signal and the time interval between the start time of the active level of the sixth clock signal and the start time of the active level of the seventh clock signal is greater than 0 and less than one-third of the period of the sixth clock signal, The time interval between the start time of the effective level of the seventh clock signal and the start time of the effective level of the eighth clock signal is greater than 0 and less than one-third of the period of the sixth clock signal; The sixth clock signal is divided by two times n times to generate the ninth clock signal, the sixth clock signal is divided by n+2 times to generate the tenth clock signal, and the seventh clock signal is divided by n+1 times to obtain the ninth clock signal The n+1 second frequency division signal of the seven clock signal, the n+1 second frequency division signal is reversed to generate the eleventh clock signal, and the n+2 second frequency division is performed on the seventh clock signal to obtain the seventh The n+2 frequency division signal of the clock signal is divided by two, and the n+2 frequency division signal of the seventh clock signal is reversed to generate the twelfth clock signal, and the eighth clock signal is generated by n+1 frequency division by two The thirteenth clock signal is divided by n+2 times on the eighth clock signal to obtain n+2 times of two frequency division signals of the eighth clock signal, and the n+2 times of two frequency division signals of the eighth clock signal are reversed. To generate the first clock signal, wherein, n is an integer greater than or equal to 0, the n+2 frequency-divided signal of the seventh clock signal is the third clock signal, and the n+2 frequency-divided signal of the eighth clock signal is The fourteenth clock signal; the first logic operation circuit performs logical OR operation on the tenth clock signal generated by the two-frequency division circuit and the fourteenth clock signal to output the second clock signal; the second logic operation circuit divides the two The twelfth clock signal generated by the frequency division circuit and the thirteenth clock signal are logically ANDed to output the fourth clock signal; the third logic operation circuit converts the ninth clock signal and the eleventh clock signal generated by the frequency division circuit and performing a logical AND operation on the twelfth clock signal to output the fifth clock signal.

Optionally, each cycle of the sixth clock signal to the eighth clock signal includes an active level and an inactive level respectively, wherein the active levels of the sixth clock signal to the eighth clock signal are high level, and the sixth clock signal The inactive level of the signal to the eighth clock signal is low level.

Optionally, the phase shifting unit includes: a frequency divider, which divides the input signal by m to generate a fifteenth clock signal, where m is an integer greater than 1; a phase shifter, which performs a frequency division on the fifteenth clock signal Phase shifting generates a sixth clock signal, a seventh clock signal, and an eighth clock signal.

Optionally, the phase shifting unit includes: a phase shifter, which shifts the phase of the input signal to generate the sixteenth clock signal, the seventeenth clock signal, and the eighteenth clock signal, wherein the sixteenth clock signal to the eighth clock signal The duty cycle of the eighteenth clock signal is the same as that of the input signal, and the start time of the active level of the seventeenth clock signal is within the duration of the active level of the sixteenth clock signal, and the eighteenth clock signal The start time of the active level of the signal is within the duration of the active level of the seventeenth clock signal, and the start time of the active level of the sixteenth clock signal is between the start time of the active level of the seventeenth clock signal The time interval between is greater than 0 and less than one-third of the period of the sixteenth clock signal, the time between the start time of the active level of the seventeenth clock signal and the start time of the active level of the eighteenth clock signal The interval is greater than 0 and less than one-third of the period of the sixteenth clock signal; the frequency divider divides the frequency of the sixteenth clock signal by m to generate the sixth clock signal, and divides the frequency of the seventeenth clock signal by m to generate the sixth clock signal Seven clock signals, the eighth clock signal is generated by dividing the eighteenth clock signal by m, wherein m is an integer greater than 1.

Optionally, each cycle of the sixteenth clock signal to the eighteenth clock signal includes an active level and an inactive level, wherein the active levels of the sixteenth clock signal to the eighteenth clock signal are high level , the inactive levels of the sixteenth clock signal to the eighteenth clock signal are low level.

Optionally, a sixth switch is further included, wherein the first connection terminal of the sixth switch is connected to the second connection terminal, and the first connection terminal and the second connection terminal are connected to the first terminal of the third voltage storage device. The control end of the six switches receives the nineteenth clock signal, wherein the nineteenth clock signal is an inverse signal of the fourth clock signal.

According to the frequency-to-voltage converter of the present invention, the fixed time difference between the effective level start time and duration of each clock signal can be used to eliminate the influence of process, power supply voltage and environmental factors on the conversion accuracy. Furthermore, according to the present invention, the influence of switching overshoot of the current source of the frequency-to-voltage converter can be eliminated.

Additional aspects and/or advantages of the present invention will be set forth in part in the following description, and some will be clear from the description, or can be learned through practice of the present invention.

Description of drawings

The above-mentioned and other objects, features and advantages of the present invention will become more clear through the following detailed description in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a circuit diagram of a frequency-to-voltage converter according to an exemplary embodiment of the present invention.

FIG. 2 shows examples of waveform diagrams of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal according to an exemplary embodiment of the present invention.

FIG. 3 shows a circuit diagram of a frequency-to-voltage converter according to another exemplary embodiment of the present invention.

FIG. 4 shows a circuit diagram of a clock circuit in the frequency-to-voltage converter of FIG. 3 according to an exemplary embodiment of the present invention.

detailed description

Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown, wherein like numerals refer to like parts throughout.

FIG. 1 shows a circuit diagram of a frequency-to-voltage converter according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the circuit 100 of the frequency-to-voltage converter according to the present invention includes: a constant current source Ic, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a A voltage storage C1, a second voltage storage C2, and a third voltage storage C3.

The first connection end of the first switch SW1 is connected to the constant current source Ic, the second connection end of the first switch SW1 is grounded, the first connection end of the second switch SW2 is connected to the constant current source Ic, and the second connection end of the second switch SW2 The connection terminal is connected to the first terminal of the first voltage storage C1, the second terminal of the first voltage storage C1 is grounded, the first connection terminal of the third switch SW3 is connected to the constant current source Ic, and the second connection terminal of the third switch SW3 Connected to the first terminal of the second voltage storage C2, the second terminal of the second voltage storage C2 is grounded, the first connection terminal of the fourth switch SW4 is connected to the first terminal of the second voltage storage C2, the second terminal of the fourth switch SW4 The second connection terminal is connected to the first terminal of the third voltage storage C3, the second terminal of the third voltage storage C3 is grounded, the first connection terminal of the fifth switch SW5 is connected to the first terminal of the second voltage storage C2, and the fifth switch SW5 is connected to the first terminal of the second voltage storage C2. The second connection terminal of SW5 is grounded, and the first terminal of the third voltage storage C3 is used as the output terminal of the frequency-to-voltage converter circuit 100 to output the voltage Vout.

The control terminal of the first switch SW1 receives the first clock signal F1, and under the control of the effective level of the first clock signal F1, the first switch SW1 is turned on, so that the constant current source Ic is grounded. The control terminal of the second switch SW2 receives the second clock signal F2, and under the control of the effective level of the second clock signal F2, the second switch SW2 is turned on, so that the constant current source Ic charges the first voltage storage C1. The control terminal of the third switch SW3 receives the third clock signal F3, and under the control of the active level of the third clock signal F3, the third switch SW3 is turned on, so that the constant current source Ic charges the second voltage storage C2. The control terminal of the fourth switch SW4 receives the fourth clock signal F4, and under the control of the active level of the fourth clock signal F4, the fourth switch SW4 is turned on, so that the second voltage storage C2 and the third voltage storage C3 share charges. The control terminal of the fifth switch SW5 receives the fifth clock signal F5, and under the control of the active level of the fifth clock signal F5, the fifth switch SW5 is turned on, so that the second voltage storage C2 is discharged through the fifth switch SW5.

Here, the first clock signal F1 to the fifth clock signal F5 received by the control terminals of the first switch SW1 to the fifth switch SW5 respectively include an active level and an inactive level in each cycle.

Specifically, the first switch SW1 can be turned off in response to the inactive level of the first clock signal F1 received by the control terminal of the first switch SW1, so as to disconnect the constant current source Ic from the ground. As an example, the first switch SW1 may be a transmission gate or a field effect transistor (for example, an NMOS transistor or a PMOS transistor). It should be understood that, according to different implementations of the first switch SW1, the active level of the first clock signal F1 can be one of high level and low level, and correspondingly, the inactive level of the first clock signal F1 can be It is the other of high level and low level.

The second switch SW2 can be turned off in response to the inactive level of the second clock signal F2 received by the control terminal of the second switch SW2, so as to stop charging the first voltage storage C1 by the constant current source Ic. As an example, the second switch SW2 may be a transmission gate or a field effect transistor (for example, an NMOS transistor or a PMOS transistor). It should be understood that, depending on the implementation of the second switch SW2, the active level of the second clock signal F2 can be one of high level and low level, and correspondingly, the inactive level of the second clock signal F2 can be It is the other of high level and low level.

The third switch SW3 can be turned off in response to the inactive level of the third clock signal F3 received by the control terminal of the third switch SW3, so as to stop the constant current source Ic from charging the second voltage storage C2. As an example, the third switch SW3 may be a transmission gate or a field effect transistor (for example, an NMOS transistor or a PMOS transistor). It should be understood that, depending on the implementation of the third switch SW3, the active level of the third clock signal F3 can be one of high level and low level, and correspondingly, the inactive level of the third clock signal F3 can be It is the other of high level and low level.

The fourth switch SW4 can be turned off in response to the inactive level of the fourth clock signal F4 received by the control terminal of the fourth switch SW4 to stop the charge sharing between the second voltage storage C2 and the third voltage storage C3 . As an example, the fourth switch SW4 may be a transmission gate or a field effect transistor (for example, an NMOS transistor or a PMOS transistor). It should be understood that, according to different implementations of the fourth switch SW4, the active level of the fourth clock signal F4 can be one of high level and low level, and correspondingly, the inactive level of the fourth clock signal F4 can be It is the other of high level and low level.

The fifth switch SW5 may be turned off in response to the inactive level of the fifth clock signal F5 received by the control terminal of the fifth switch SW5, so as to stop the discharge of the second voltage storage C2. As an example, the fifth switch SW5 may be a transmission gate or a field effect transistor (for example, an NMOS transistor or a PMOS transistor). It should be understood that, depending on the implementation of the fifth switch SW5, the active level of the fifth clock signal F5 can be one of high level and low level, and correspondingly, the inactive level of the fifth clock signal F5 can be It is the other of high level and low level.

In addition, in the frequency voltage converter circuit 100, when the fourth switch SW4 is implemented by a field effect transistor, and the physical size of the fourth switch SW4 is close to the physical size of the third capacitor C3, in order to reduce the clock feed of the fourth switch SW4 To avoid the influence of the pass-through effect, a sixth switch (not shown) may be added at the first end of the third voltage storage C3 as a redundant switch. The sixth switch may be the same field effect transistor (NMOS transistor or PMOS transistor) as the fourth switch. At this time, the source (one of the first connection end and the second connection end) of the sixth switch can be connected to the drain (the other one of the first connection end and the second connection end), and the connected The source and the drain are connected to the first end of the third memory C3, and the gate (control end) of the sixth switch receives the reverse signal of the fourth clock signal F4 (hereinafter referred to as the nineteenth clock signal), thereby Reduce the impact of clock feedthrough effects.

It should be understood that an inverter may be added to the circuit 100 of the frequency-to-voltage converter to enable the control terminal of the sixth switch to receive the nineteenth clock signal. Here, the inverter may receive the fourth clock signal F4, invert the received fourth clock signal F4, and output the inverted fourth clock signal F4 as the nineteenth clock signal.

Preferably, the first clock signal F1 to the fifth clock signal F5 received by the circuit 100 of the frequency voltage converter have the same frequency, and the start time and end time of the active levels of the first clock signal F1 to the fifth clock signal F5 Cycle in the following order: start time of the active level of the second clock signal F2<end time of the active level of the fifth clock signal F5<start time of the active level of the third clock signal F3<time of the first clock signal F1 The end time of the active level<the end time of the active level of the third clock signal F3<the start time of the active level of the first clock signal F1<the end time of the active level of the second clock signal F2≤the fourth clock signal The start time of the active level of F4<the end time of the active level of the fourth clock signal F4<the start time of the active level of the fifth clock signal F5.

It has been described above that within a period including the start time and end time of the active levels of the first clock signal F1 to the fifth clock signal F5, the start time and the start time of the active levels of the first clock signal F1 to the fifth clock signal F5 The order in which the end times appear. However, the present invention is not limited to the fact that the start time of the active level of the second clock signal F2 occurs first. Since the first clock signal F1 to the fifth clock signal F5 all appear cyclically, it should be understood that the description of the above order may vary according to the different cycle division methods, but they are essentially the same technically.

For example, when the end time of the active level of the fifth clock signal F5 appears first, the start time of the active level of the second clock signal F2 appears last, that is, the end time of the active level of the fifth clock signal F5<the end time of the active level of the second clock signal F5 The start time of the active level of the third clock signal F3<the end time of the active level of the first clock signal F1<the end time of the active level of the third clock signal F3<the start time of the active level of the first clock signal F1 <the end time of the active level of the second clock signal F2≤the start time of the active level of the fourth clock signal F4<the end time of the active level of the fourth clock signal F4<the end time of the active level of the fifth clock signal F5 start time<start time of the active level of the second clock signal F2.

In addition, it should also be understood that no matter how the cycle is divided, the above sequence must exist within two cycles that all include the start time and end time of the active levels of the first clock signal F1 to the fifth clock signal F5.

In addition, in the present invention, the order of the start time and end time of the active levels of the first clock signal F1 to the fifth clock signal F5 is not limited to the above-mentioned preferred embodiment. In another embodiment, the first clock signal F1 to the fifth clock signal F5 received by the frequency voltage converter circuit 100 have the same frequency, and the active levels of the first clock signal F1 to the fifth clock signal F5 start The time and end time cycle in the following order: the end time of the active level of the fifth clock signal F5<the start time of the active level of the third clock signal F3<the end time of the active level of the first clock signal F1<the third The end time of the active level of the clock signal F3<the start time of the active level of the first clock signal F1≤the end time of the active level of the second clock signal F2<the end time of the active level of the fourth clock signal F4< The start time of the active level of the fifth clock signal F5;

And, the start time of the active level of the second clock signal F2≤the end time of the active level of the fifth clock signal F5, or, the end time of the active level of the fifth clock signal F5<the effective level of the second clock signal F2 The start time of the level<the start time of the active level of the third clock signal F3;

And, the end time of the active level of the third clock signal F3<the start time of the active level of the fourth clock signal F4<the start time of the active level of the first clock signal F1, or, the effective level of the first clock signal F1 The start time of the level ≤ the start time of the active level of the fourth clock signal F4 ≤ the end time of the active level of the second clock signal F2, or, the end time of the active level of the second clock signal F2<the fourth clock The start time of the active level of the signal F4<the end time of the active level of the fourth clock signal F4.

FIG. 2 shows examples of waveform diagrams of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the first clock signal F1 to the fifth clock signal F5 have the same frequency, and the active levels of the first clock signal F1 to the fifth clock signal F5 are all high level, and the first clock signal F1 to the fifth clock signal F5 have the same frequency. The inactive levels of the fifth clock signal F5 are all low levels. In addition, the start time and end time of the active levels of the first clock signal F1 to the fifth clock signal F5 cycle in the following order: the start time of the active level of the second clock signal F2=the active level of the fifth clock signal F5 The end time of < the start time of the active level of the third clock signal F3 < the end time of the active level of the first clock signal F1 < the end time of the active level of the third clock signal F3 < the effective level of the first clock signal F1 The start time of the level=the end time of the active level of the second clock signal F2=the start time of the active level of the fourth clock signal F4<the end time of the active level of the fourth clock signal F4<the fifth clock signal F5 The start time of the active level.

At time t1, the first switch SW1 and the second switch SW2 in the circuit 100 shown in FIG. 1 are respectively turned on in response to the first clock signal F1 and the second clock signal F2 being at a high level (ie, active level). . The third switch SW3 to the fifth switch SW5 are turned off in response to the third clock signal F3 to the fifth clock signal F5 being at a low level (ie, inactive level), respectively. At this time, the constant current source Ic is grounded, and the first voltage storage C1 is discharged through the first switch SW1 and the second switch SW2.

At time t2, the third clock signal F3 jumps to a high level (that is, an active level), the third switch SW3 is turned on, the first switch SW1 and the second switch SW2 are in a turned-on state, and the fourth switch SW4 and the second switch SW2 are in a turned-on state. The fifth switch SW5 is in an off state. At this time, the constant current source Ic is grounded, and the first voltage storage C1 and the second voltage storage C2 are discharged.

At time t3, the first clock signal F1 jumps to a low level (that is, an inactive level), the first switch SW1 is turned off, the second switch SW2 and the third switch SW3 are in a conducting state, and the fourth switch SW4 and The fifth switch SW5 is in an off state. At this time, the constant current source Ic starts to charge the first voltage storage C1 and the second voltage storage C2.

At time t4, the third clock signal F3 jumps to a low level (that is, an inactive level), the third switch SW3 is turned off, the second switch SW2 is in an on state, and the first switch SW1, the fourth switch SW4 and the The fifth switch SW5 is in an off state. At this time, the constant current source Ic continues to charge the first voltage storage C1.

At time t5, the first clock signal F1 jumps to a high level, and the first switch SW1 is turned on; the second clock signal jumps to a low level (that is, an inactive level), and the second switch SW2 is turned off; The fourth clock signal F4 jumps to a high level (ie, active level), the fourth switch SW4 is turned on; the third switch SW3 and the fifth switch SW5 are in an off state. At this time, the constant current source Ic is grounded, and the second voltage storage C2 and the third voltage storage C3 share charges.

At time t6, the fourth clock signal F4 jumps to a low level (that is, an inactive level), the fourth switch SW4 is turned off, the first switch SW1 is in an on state, the second switch SW2, the third switch SW3 and the The fifth switch SW5 is in an off state. At this point, the charge sharing between the second voltage storage C2 and the third voltage storage C3 ends.

At time t7, the fifth clock signal F5 jumps to a high level (that is, an active level), the fifth switch SW5 is turned on, the first switch SW1 is turned on, and the second switch SW2 to the fourth switch SW4 are turned off. open state. At this time, the second voltage storage C2 is discharged through the fifth switch SW5.

It can be seen from the above analysis that, under the condition that the frequencies of the first clock signal F1 to the fifth clock signal F5 remain unchanged, in the initial working stage of the circuit 100 shown in FIG. 1 , when the second clock signal F2 is at an active level for the first time, the first The first switch SW1 and the second switch SW2 are turned on, and the constant current source Ic is grounded, so as to eliminate the influence of the current overshoot on the circuit 100 shown in FIG. 1 when the switch is turned on. The constant current source Ic charges the second voltage accumulator C2 during the period corresponding to the Δt period during the period when the third clock signal F3 is at an active level for the first time. During the period when the fourth clock signal F4 is at an active level for the first time, the second voltage storage C2 shares charges with the third voltage storage C3 for the first time, and the voltage of the third voltage storage C3 increases from 0, correspondingly, the voltage Vout at the output terminal changes from 0 starts to rise. During the period when the fifth clock signal F5 is at an active level for the first time, the second voltage storage C2 is discharged through the fifth switch SW5.

When the third clock signal F3 is at an active level again, since the frequency of the first clock signal F1 to the fifth clock signal F5 remains unchanged, Δt remains unchanged, and the charging time of the second voltage storage C2 remains unchanged, so that the second voltage The voltage of memory C2 does not change. When the fourth clock signal F4 is at an active level again, the second voltage storage C2 and the third voltage storage C3 share charges again, so that the voltage of the third voltage storage C3 continues to increase, and correspondingly, the output voltage Vout continues to rise. When the fifth clock signal F5 is at an active level again, the second voltage storage C2 is discharged through the fifth switch SW5 again. Thereafter, the circuit 100 shown in FIG. 1 is charged, shared, and discharged according to the order of charging the second voltage storage C2, sharing charge between the second voltage storage C2 and the third voltage storage C3, and discharging the second voltage storage C2. Finally, the second voltage storage C2 The voltage of the triple voltage store C3 will stabilize at the voltage at which the second voltage store C2 is charged within the time Δt. Therefore, the final output voltage Vout of the circuit 100 shown in FIG. 1 may represent the charging voltage of the second voltage storage C1 within the time period Δt.

As the charging time is longer, the voltage across the voltage store is also greater. Therefore, the longer the Δt time, the greater the voltage generated by charging the second voltage storage C2. Correspondingly, the output voltage Vout of the circuit 100 shown in FIG. 1 is also larger. Since Δt is related to the frequency of the first clock signal F1 to the fifth clock signal F5, the larger the frequency, the smaller the Δt, and the smaller the output voltage Vout, and the smaller the frequency, the larger the Δt, and the output voltage Vout Also bigger. Therefore, the frequency of the input first clock signal F1 to fifth clock signal F5 can be represented by the voltage Vout output by the frequency-to-voltage converter.

It should be understood that the first voltage storage C1 in the circuit 100 of the frequency-to-voltage converter shown in FIG. The voltage storage C2 may be a capacitor or other devices capable of voltage storage, and the third voltage storage C3 in the circuit 100 of the frequency-to-voltage converter shown in FIG. 1 may be a capacitor or other devices capable of voltage storage.

FIG. 3 shows a circuit diagram of a frequency-to-voltage converter according to another exemplary embodiment of the present invention.

As shown in FIG. 3 , in addition to the circuit 100 shown in FIG. 1 (hereinafter simply referred to as the circuit 100 ), the frequency-to-voltage converter according to the present invention further includes a clock circuit 200 .

Specifically, the clock circuit 200 can generate five first clock signal F1 , second clock signal F2 , third clock signal F3 , fourth clock signal F4 , and fifth clock signal F5 with the same frequency by using the externally input signal Fin.

In addition, the start time and end time of the active levels of the first clock signal F1 to the fifth clock signal F5 cycle in the following order: the end time of the active level of the fifth clock signal F5<the active level of the third clock signal F3 The start time of < the end time of the active level of the first clock signal F1 < the end time of the active level of the third clock signal F3 < the start time of the active level of the first clock signal F1 ≤ the effective level of the second clock signal F2 The end time of the level<the end time of the active level of the fourth clock signal F4<the start time of the active level of the fifth clock signal F5;

And, the start time of the active level of the second clock signal F2≤the end time of the active level of the fifth clock signal F5, or, the end time of the active level of the fifth clock signal F5<the effective level of the second clock signal F2 The start time of the level<the start time of the active level of the third clock signal F3;

And, the end time of the active level of the third clock signal F3<the start time of the active level of the fourth clock signal F4<the start time of the active level of the first clock signal F1, or, the effective level of the first clock signal F1 The start time of the level ≤ the start time of the active level of the fourth clock signal F4 ≤ the end time of the active level of the second clock signal F2, or, the end time of the active level of the second clock signal F2<the fourth clock The start time of the active level of the signal F4<the end time of the active level of the fourth clock signal F4.

In addition, the frequencies of the first clock signal F1 to the fifth clock signal F5 respectively have a monotone function relationship with the frequency of the input signal Fin, for example, the first clock signal F1 to the fifth clock signal F5 increase with the frequency of the input signal Fin monotonously increasing, or the frequencies of the first clock signal F1 to the fifth clock signal F5 are monotonically decreasing as the frequency of the input signal Fin increases.

From the above analysis, it can be seen that the relationship between the frequency of the first clock signal F1 to the fifth clock signal F5 and the voltage Vout output by the circuit 100 is: the higher the frequency of the first clock signal F1 to the fifth clock signal F5, the higher the output voltage The smaller Vout is, the lower the frequency of the first clock signal F1 to the fifth clock signal F5 is, and the larger the output voltage Vout is. The frequencies of the first clock signal F1 to the fifth clock signal F5 generated by the clock circuit 200 respectively have a monotone function relationship with the frequency of the input signal Fin, therefore, the output voltage Vout of the frequency-to-voltage converter shown in FIG. 3 can be used to determine Indicates the frequency of the input signal Fin.

In one example, the frequencies of the first clock signal F1 to the fifth clock signal F5 have a monotonically increasing functional relationship with the frequency of the input signal Fin, then when the frequency of the input signal Fin increases, the first clock signal generated by the clock circuit 200 The frequencies of the first clock signal F1 to the fifth clock signal F5 increase accordingly, and since the output voltage Vout of the circuit 100 decreases with the increase of the frequency of the first clock signal F1 to the fifth clock signal F5, the frequency voltage The voltage Vout output by the converter will decrease accordingly.

In another example, the frequencies of the first clock signal F1 to the fifth clock signal F5 have a monotonically decreasing functional relationship with the frequency of the input signal Fin, then when the frequency of the input signal Fin increases, the clock circuit 200 generates The frequencies of the first clock signal F1 to the fifth clock signal F5 decrease accordingly, and since the output voltage Vout of the circuit 100 increases with the decrease of the frequency of the first clock signal F1 to the fifth clock signal F5, the frequency The voltage Vout output by the voltage converter will increase accordingly.

It should be understood that since the output voltage Vout of the circuit 100 is stabilized, the frequency of the input signal can be accurately represented. Therefore, the frequency-to-voltage converters in FIG. 1 and FIG. The frequency conversion precision of the first clock signal F1 to the fifth clock signal F5, or the signal Fin) is higher.

FIG. 4 shows a circuit diagram of a clock circuit 200 in the frequency-to-voltage converter of FIG. 3 according to an exemplary embodiment of the present invention.

As shown in FIG. 4 , the clock circuit 200 of the present invention includes: a phase shift unit 210 , a frequency division circuit 220 , a first logic operation circuit 230 , a second logic operation circuit 240 , and a third logic operation circuit 250 .

The phase shifting unit 210 generates the sixth clock signal F6 , the seventh clock signal F7 and the eighth clock signal F8 with the same frequency by using the input signal Fin. Here, the phase relationship of the sixth clock signal F6 to the eighth clock signal F8 is: the duty cycle of the sixth clock signal F6 to the eighth clock signal F8 is the same, and the start time of the active level of the seventh clock signal F7 is at Within the duration of the active level of the sixth clock signal F6, the start time of the active level of the eighth clock signal F8 is within the duration of the active level of the seventh clock signal F7, and the active level of the sixth clock signal F6 The time interval between the start time of the active level of the seventh clock signal F7 and the start time is greater than 0 and less than one-third of the period of the sixth clock signal F6, and the start time of the active level of the seventh clock signal F7 The time interval from the start time of the active level of the eighth clock signal F8 is greater than 0 and less than one third of the period of the sixth clock signal F6.

Specifically, each period of the sixth clock signal F6 to the eighth clock signal F8 respectively includes an active level and an inactive level. For example, the active levels of the sixth clock signal F6 to the eighth clock signal F8 are high level, and the inactive levels of the sixth clock signal F6 to the eighth clock signal F8 are low level.

As an example, the phase shift unit 210 may be implemented by a phase shifter to generate the above-mentioned sixth clock signal F6 to eighth clock signal F8.

As another example, the phase shifting unit 210 may include a frequency divider (not shown) and a phase shifter (not shown), the output terminal of the frequency divider is connected to the input terminal of the phase shifter. The frequency divider divides the external input signal Fin by m (m is an integer greater than 1) to generate the fifteenth clock signal, and the phase shifter shifts the phase of the fifteenth clock signal to generate the sixth clock signal F6 and the seventh clock signal Signal F7, eighth clock signal F8.

As another example, the phase shift unit 210 may include a frequency divider (not shown) and a phase shifter (not shown), the output terminal of the phase shifter is connected to the input terminal of the frequency divider. The phase shifter phase-shifts the input signal Fin to generate the sixteenth clock signal, the seventeenth clock signal, and the eighteenth clock signal. Here, the phase relationship between the sixteenth clock signal and the eighteenth clock signal is: tenth clock signal The duty cycle of the sixth clock signal to the eighteenth clock signal is the same as the duty cycle of the input signal Fin, and the start time of the active level of the seventeenth clock signal is within the duration of the active level of the sixteenth clock signal Within, the start time of the active level of the eighteenth clock signal is within the duration of the active level of the seventeenth clock signal, and the start time of the active level of the sixteenth clock signal is the same as the effective level of the seventeenth clock signal The time interval between the start times of the level is greater than 0 and less than one-third of the period of the sixteenth clock signal, and the start time of the effective level of the seventeenth clock signal is equal to the effective level of the eighteenth clock signal A time interval between start times is greater than 0 and less than one third of a period of the sixteenth clock signal. After that, the frequency divider divides the sixteenth clock signal by m to generate the sixth clock signal F6, divides the seventeenth clock signal by m to generate the seventh clock signal F7, and divides the eighteenth clock signal by m to generate Eighth clock signal F8.

Specifically, each period of the sixteenth clock signal to the eighteenth clock signal includes an active level and an inactive level respectively. For example, the active levels of the sixteenth clock signal to the eighteenth clock signal are high level, and the inactive levels of the sixteenth clock signal to the eighteenth clock signal are low level.

The frequency divider in the phase shift unit 210 divides the frequency of the input signal Fin by m, so as to expand the frequency range that the frequency voltage converter can convert.

The frequency division circuit 220 performs n (n is an integer greater than or equal to 0) times of frequency division on the sixth clock signal F6 to generate the ninth clock signal F9, and performs n+2 times of frequency division on the sixth clock signal F6 to generate the tenth clock signal. The clock signal F10 is divided by n+1 times on the seventh clock signal F7 to obtain the n+1 times divided by two signal of the seventh clock signal F7, and the n+1 times divided by two signal is reversed to generate the first The eleventh clock signal F11 is divided by n+2 times on the seventh clock signal F7 to obtain the n+2 times divided by two signal of the seventh clock signal F7, and the n+2 times divided by two on the seventh clock signal F7 The signal is reversed to generate the twelfth clock signal F12, the eighth clock signal F8 is divided by n+1 times to generate the thirteenth clock signal F13, and the eighth clock signal F8 is divided by n+2 times to obtain the thirteenth clock signal F13 The n+2 frequency-divided signal of the eighth clock signal F8 is reversed to the n+2 frequency-divided signal of the eighth clock signal F8 to generate the first clock signal F1. Here, the n+2 frequency-divided signal of the seventh clock signal is the third clock signal F3, and the n+2 frequency-divided signal of the eighth clock signal is the fourteenth clock signal F14.

The frequency division circuit 220 by two is described below by taking n=1 as an example. Referring to FIG. 4 , the divide-by-two circuit 220 can divide the sixth clock signal F6 once by divider 2201 to generate the ninth clock signal F9, and divide the sixth clock signal F9 through dividers 2201, 2202 and 2203. F6 is divided by two twice to generate the tenth clock signal F10, and the seventh clock signal F7 is divided by two by two frequency dividers 2204 and 2205 to obtain the second frequency-divided signal of the seventh clock signal F7. The commutator 2207 reversely generates the eleventh clock signal F11 on the two-time frequency-divided signal, and divides the seventh clock signal F7 three times by two to obtain the seventh clock signal through the frequency dividers 2204, 2205, and 2206. The three frequency-divided signals of F7 are reversed by the inverter 2208 to the three frequency-divided signals of the seventh clock signal F7 to generate the twelfth clock signal F12, and the eighth clock signal is generated by the frequency dividers 2209 and 2210. The signal F8 is divided by two times to generate the thirteenth clock signal F13, and the eighth clock signal F8 is divided by three times by two frequency dividers 2209, 2210 and 2211 to obtain the third frequency division of the eighth clock signal F8 by two signal, through the inverter 2212, the third frequency-divided signal of the eighth clock signal F8 is reversed to generate the first clock signal F1, and the third frequency-divided signal of the seventh clock signal F7 is the third clock signal F3, The three times frequency-divided signal of the eighth clock signal F8 is the fourteenth clock signal F14.

It should be understood that various divide-by-twos may be employed. For example, a frequency divider by two can be implemented with a D flip-flop. For example, connect the data input end of the D flip-flop to the inverting data output end of the D flip-flop, use the clock signal input end of the D flip-flop as the input end of the frequency divider by two, and use the data output end of the D flip-flop as the second frequency divider. output of the divider. It can also be understood that since the D flip-flop has an inverting data output terminal, the signal obtained by performing inversion in the foregoing embodiments can be output through the inverting data output terminal of the D flip-flop. At the same time, when using the D flip-flop to implement the above embodiment, since the D flip-flop has two output terminals (data output terminal and inverted data output terminal), the connection mode of the circuit can be selected by itself (for example: for the sixth clock When the signal F6 is divided by two three times to generate the tenth clock signal F10, the data output end of the first D flip-flop can be connected with the clock signal input end of the second D flip-flop, and the data output end of the second D flip-flop Connect with the clock signal input end of the third D flip-flop, generate the tenth clock signal F10 at the data output end of the third D flip-flop, or connect the inverted data output end of the first D flip-flop to the second D flip-flop Connect the clock signal input end of the second D flip-flop to the clock signal input end of the third D flip-flop, and generate the tenth clock signal F10 at the data output end of the third D flip-flop). Of course, the frequency divider by two can also be realized by other circuits capable of realizing the frequency division by two function.

It should be understood that the frequency division circuit by two is not limited to the realization by the frequency divider by two, and the sixth clock signal F6 can also be divided by ⁿ times by two to generate n times by two of the sixth clock signal F6 by using a 2n frequency divider. The frequency signal, that is, the ninth clock signal F9, generates the tenth clock signal ^F10 by dividing the ⁿ times of the second frequency signal of the sixth clock signal F6 twice to generate the tenth clock signal F10. The signal F7 is divided by n+1 times to obtain the n+1 frequency-divided signal of the seventh clock signal F7, and the n+1 frequency-divided signal is reversed to generate the eleventh clock signal F11. The n+1 frequency-divided signal of the seven clock signal F7 is divided by 1 to obtain the n+2 frequency-divided signal of the seventh clock signal F7, that is, the third clock signal, and the n+2 frequency-divided signal of the seventh clock signal F7 The twelfth clock signal F12 is generated by reversely dividing the two-time frequency signal twice, and the eighth clock signal F8 is divided by n+1 times to generate n+1 of the eighth clock signal F8 through a 2 ⁿ⁺¹ frequency divider The second frequency-divided signal, that is, the thirteenth clock signal F13, divides the n+1 frequency-divided signal of the eighth clock signal F8 by one frequency to obtain the n+2 frequency-divided signal of the eighth clock signal F8 , that is, the fourteenth clock signal F14, which reverses the frequency-divided n+2 times signal of the eighth clock signal F8 to generate the first clock signal F1.

The first logical operation circuit 230 is a two-input OR gate. The first logical operation circuit 230 performs logical OR operation on the tenth clock signal F10 and the fourteenth clock signal F14 generated by the divide-by-two circuit 220 to output the second clock signal F2.

The second logical operation circuit 240 is a two-input AND gate. The second logical operation circuit 240 performs logical AND operation on the twelfth clock signal F12 and the thirteenth clock signal F13 generated by the divide-by-2 circuit to output the fourth clock signal F4.

The third logical operation circuit 250 is a two-input AND gate. The third logical operation circuit 250 performs a logical AND operation on the ninth clock signal F9 , the eleventh clock signal F11 and the twelfth clock signal F12 generated by the divide-by-two circuit to output the fifth clock signal F5 .

The above-mentioned clock circuit 220 generates the first clock signal F1 to the fifth clock signal F5 by means of digital logic operations, and the waveforms of the generated first clock signal F1 to the fifth clock signal F5 are not easily affected by the process, power supply voltage, and ambient temperature. And the start time of the active levels of the first clock signal F1 to the fifth clock signal F5 maintains a stable time difference, so that the on or off time of the first switch SW1 to the fifth switch SW5 in the circuit 100 can be effectively controlled, Avoid the influence of constant current source Ic switch overshoot.

According to the frequency-to-voltage converter of the present invention, the second voltage storage C2 is charged by the constant current source Ic, and at the same time, the first switch in the circuit 100 is controlled by the first clock signal F1 to the fifth clock signal F5 with the same frequency and fixed frequency Turning on or off of the fifth switch SW1 to SW5 makes the voltage of the second voltage storage C2 correspond to the charging time, that is, correspond to the frequency of the clock signal, so that the frequency can be converted into voltage accurately. Moreover, the conversion accuracy of the frequency-to-voltage converter is not easily affected by the process, power supply voltage, and ambient temperature.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it should be understood by those skilled in the art that modifications may be made thereto without departing from the spirit and scope of the invention as defined by the claims. and various changes in details.

Claims (10)

1. A frequency-to-voltage converter, comprising: a constant current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first voltage storage, a second voltage storage and a third voltage storage, Wherein, the first connection end of the first switch is connected to the constant current source, the second connection end of the first switch is grounded, the control end of the first switch receives the first clock signal, and the first connection end of the second switch is connected to the constant current source. source, the second connection terminal of the second switch is connected to the first terminal of the first voltage storage, the second terminal of the first voltage storage is grounded, the control terminal of the second switch receives the second clock signal, the first connection of the third switch end is connected to the constant current source, the second connection end of the third switch is connected to the first end of the second voltage memory, the second end of the second voltage memory is grounded, the control end of the third switch receives the third clock signal, and the fourth The first connection terminal of the switch is connected to the first terminal of the second voltage storage, the second connection terminal of the fourth switch is connected to the first terminal of the third voltage storage, the second terminal of the third voltage storage is grounded, and the The control terminal receives the fourth clock signal, the first connection terminal of the fifth switch is connected to the first terminal of the second voltage storage, the second connection terminal of the fifth switch is grounded, and the control terminal of the fifth switch receives the fifth clock signal, Wherein, the first clock signal to the fifth clock signal have the same frequency, and the start time and the end time of the active levels of the first clock signal to the fifth clock signal cycle in the following order: the active level of the fifth clock signal End time < start time of active level of the third clock signal < end time of active level of the first clock signal < end time of active level of the third clock signal < start time of active level of the first clock signal ≤ the end time of the active level of the second clock signal < the end time of the active level of the fourth clock signal < the start time of the active level of the fifth clock signal, Wherein, the start time of the active level of the second clock signal≤the end time of the active level of the fifth clock signal, or, the end time of the active level of the fifth clock signal<the start of the active level of the second clock signal time < the start time of the active level of the third clock signal, And, the end time of the active level of the third clock signal<the start time of the active level of the fourth clock signal<the start time of the active level of the first clock signal, or, the start time of the active level of the first clock signal time ≤ the start time of the active level of the fourth clock signal ≤ the end time of the active level of the second clock signal, or, the end time of the active level of the second clock signal < the start of the active level of the fourth clock signal time < the end time of the active level of the fourth clock signal. 2. The frequency-to-voltage converter as claimed in claim 1, wherein the first terminal of the third voltage storage is used as an output terminal, and the first switch responds to the effective level of the first clock signal received by the control terminal of the first switch is turned on, the second switch is turned on in response to the effective level of the second clock signal received by the control terminal of the second switch, and the third switch responds to the effective level of the third clock signal received by the control terminal of the third switch is turned on, the fourth switch is turned on in response to the effective level of the fourth clock signal received by the control terminal of the fourth switch, and the fifth switch is responded to the effective level of the fifth clock signal received by the control terminal of the fifth switch conduction, Wherein, the active level of the first clock signal is one of high level and low level, the inactive level of the first clock signal is the other one of high level and low level, and the effective level of the second clock signal is one of high level and low level. The level is one of high level and low level, the inactive level of the second clock signal is the other one of high level and low level, and the active level of the third clock signal is high level or low level. one of level, the inactive level of the third clock signal is the other of high level and low level, the active level of the fourth clock signal is one of high level and low level, and the fourth The inactive level of the clock signal is another one of high level and low level, the active level of the fifth clock signal is one of high level and low level, and the inactive level of the fifth clock signal is The other of high level and low level. 3. The frequency-to-voltage converter of claim 1, further comprising: a clock circuit for generating a first clock signal, a second clock signal, a third clock signal, a fourth clock signal and a fifth clock signal based on an input signal, Wherein, each cycle of the first clock signal to the fifth clock signal includes an active level and an inactive level respectively, and the first switch is turned off in response to the inactive level of the first clock signal received by the control terminal of the first switch. , the second switch is turned off in response to the inactive level of the second clock signal received by the control terminal of the second switch, and the third switch is turned off in response to the inactive level of the third clock signal received by the control terminal of the third switch open, the fourth switch is turned off in response to the inactive level of the fourth clock signal received by the control terminal of the fourth switch, and the fifth switch responds to the inactive level of the fifth clock signal received by the control terminal of the fifth switch level off. 4. The frequency-to-voltage converter according to claim 3, wherein the frequencies of the first clock signal to the fifth clock signal have a monotone function relationship with the frequency of the input signal. 5. The frequency-to-voltage converter as claimed in claim 3, wherein the clock circuit comprises: The phase shifting unit uses the input signal to generate the sixth clock signal, the seventh clock signal, and the eighth clock signal with the same frequency, wherein the duty ratios of the sixth clock signal to the eighth clock signal are the same, and the duty cycle of the seventh clock signal is The start time of the active level is within the duration of the active level of the sixth clock signal, the start time of the active level of the eighth clock signal is within the duration of the active level of the seventh clock signal, and the sixth clock signal The time interval between the start time of the active level of the clock signal and the start time of the active level of the seventh clock signal is greater than 0 and less than one-third of the period of the sixth clock signal, and the start time of the active level of the seventh clock signal The time interval between the time and the start time of the active level of the eighth clock signal is greater than 0 and less than one-third of the period of the sixth clock signal; Divide-by-two circuit, divide the sixth clock signal n times by two to generate the ninth clock signal, perform n+2 times divide the sixth clock signal by two to generate the tenth clock signal, and perform n+1 frequency division on the seventh clock signal The n+1 second frequency division signal of the seventh clock signal is obtained by the second frequency division, and the n+1 second frequency division signal is reversed to generate the eleventh clock signal, and the seventh clock signal is n+2 times Divide by two to obtain the n+2 frequency-divided signal of the seventh clock signal, reverse the n+2 frequency-divided signal of the seventh clock signal to generate the twelfth clock signal, and perform n+2 frequency-divided signal on the eighth clock signal The thirteenth clock signal is generated by 1 frequency division by two, and the n+2 frequency division of the eighth clock signal is performed to obtain the n+2 frequency division signal of the eighth clock signal, and the n+2 frequency division signal of the eighth clock signal is The second frequency division signal is reversed to generate the first clock signal, wherein n is an integer greater than or equal to 0, the n+2 second frequency division signal of the seventh clock signal is the third clock signal, and the n+2 frequency division signal of the eighth clock signal is The second frequency-divided signal is the fourteenth clock signal; The first logical operation circuit performs logical OR operation on the tenth clock signal and the fourteenth clock signal generated by the frequency division circuit to output the second clock signal; The second logical operation circuit performs logical AND operation on the twelfth clock signal and the thirteenth clock signal generated by the frequency division circuit to output the fourth clock signal; The third logical operation circuit performs logical AND operation on the ninth clock signal, the eleventh clock signal and the twelfth clock signal generated by the frequency division circuit to output the fifth clock signal. 6. The frequency-to-voltage converter as claimed in claim 5, wherein each cycle of the sixth clock signal to the eighth clock signal includes an active level and an inactive level respectively, wherein the sixth clock signal to the eighth clock signal The active level of the clock signal is high level, and the inactive levels of the sixth clock signal to the eighth clock signal are low level. 7. The frequency-to-voltage converter according to claim 6, wherein the phase shifting unit comprises: A frequency divider, which divides the input signal by m to generate a fifteenth clock signal, where m is an integer greater than 1; The phase shifter is configured to shift the phase of the fifteenth clock signal to generate a sixth clock signal, a seventh clock signal, and an eighth clock signal. 8. The frequency-to-voltage converter as claimed in claim 6, wherein the phase shifting unit comprises: A phase shifter, which shifts the phase of the input signal to generate the sixteenth clock signal, the seventeenth clock signal, and the eighteenth clock signal, wherein, the duty cycle of the sixteenth clock signal to the eighteenth clock signal is the same as that of the input The duty cycles of the signals are the same, and the start time of the active level of the seventeenth clock signal is within the duration of the active level of the sixteenth clock signal, and the start time of the active level of the eighteenth clock signal is within the tenth Within the duration of the active level of the seventh clock signal, and the time interval between the start time of the active level of the sixteenth clock signal and the start time of the active level of the seventeenth clock signal is greater than 0 and less than the sixteenth One-third of the period of the clock signal, the time interval between the start time of the effective level of the seventeenth clock signal and the start time of the effective level of the eighteenth clock signal is greater than 0 and less than that of the sixteenth clock signal one-third of the cycle; A frequency divider, which divides the sixteenth clock signal by m to generate the sixth clock signal, divides the seventeenth clock signal by m to generate the seventh clock signal, and divides the eighteenth clock signal by m to generate the eighth clock Signal, where m is an integer greater than 1. 9. The frequency-to-voltage converter as claimed in claim 8, wherein each period of the sixteenth clock signal to the eighteenth clock signal includes an active level and an inactive level respectively, wherein the sixteenth clock signal to the eighteenth clock signal The active level of the eighteenth clock signal is high level, and the inactive levels of the sixteenth to eighteenth clock signals are low level. 10. The frequency-to-voltage converter according to claim 1, further comprising a sixth switch, wherein the first connection terminal of the sixth switch is connected to the second connection terminal, and the first connection terminal and the second connection terminal are connected to The first terminal of the third voltage storage device and the control terminal of the sixth switch receive a nineteenth clock signal, wherein the nineteenth clock signal is an inverted signal of the fourth clock signal.