CN104157252B

CN104157252B - Shifting register, gate driving circuit and display device

Info

Publication number: CN104157252B
Application number: CN201410367798.3A
Authority: CN
Inventors: 张毅; 玄明花; 金泰逵
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2014-07-29
Filing date: 2014-07-29
Publication date: 2017-01-18
Anticipated expiration: 2034-07-29
Also published as: CN104157252A

Abstract

The invention discloses a shifting register, a gate driving circuit and a display device. The shifting register provided by the embodiment of the invention comprises an input module, a reset module, a driving module, a first output module and a second output module. The shifting register utilizes a direct-current power supply as the output source for the output signal output by an output signal end; compared with the output source adopting a clock signal as the output signal, the direct current power supply can avoid the problem about the unstable output signal caused by own high-frequency periodic conversion characteristic of the clock signal, and reduce the influence of a circuit load on the output signal, and can further improve the stability and the reliability of the output signal output by the shifting register.

Description

Shifting register, grid driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit and a display device.

Background

In a Thin Film Transistor display, a gate driving signal is generally supplied to a gate of each Thin Film Transistor (TFT) in a pixel region by a gate driving device. The Gate driving device can be formed on an Array substrate of the liquid crystal display through an Array process, namely, a Gate Driver on Array (GOA) process of the Array substrate, the integration process not only saves cost, but also can achieve an aesthetic design of bilateral symmetry of a liquid crystal Panel (Panel), and simultaneously, a binding region of a Gate Integrated Circuit (IC) and a wiring space of a Fan-out (Fan-out) are also saved, thereby realizing the design of a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.

The prior gate driving circuit mainly applies an input clock signal to a gate scanning line of a liquid crystal display panel after the input clock signal is converted by a shift register, and the clock signal can generate signal delay and attenuation due to the own high-frequency periodic conversion characteristic and the own resistance of a transmission line, so that stable voltage cannot be output, the normal work of a thin film transistor connected with the gate scanning line on the display panel is influenced, and the uneven picture display is caused.

Disclosure of Invention

In view of this, embodiments of the present invention provide a shift register, a gate driving circuit and a display device, so as to solve the problem of unstable output voltage caused by the clock signal as the voltage source of the output voltage of the shift register in the prior art.

Therefore, an embodiment of the present invention provides a shift register, including: the device comprises an input module, a reset module, a driving module, a first output module and a second output module; wherein,

the input module is used for providing an input signal of an input signal end to a first node under the control of a first clock signal;

the driving module is used for providing a second clock signal to a second node under the control of the voltage of the first node; and pulling down or pulling up the voltage of the first node when no signal is transmitted between the input signal terminal and the first node;

the reset module is used for providing the voltage of a first direct current source to the second node under the control of the voltage of the first node and the first clock signal; and causing the first dc source to cease providing voltage to the second node under control of the voltage of the first node;

the first output module is used for providing the voltage of the first direct current source to an output signal end under the control of the voltage of the second node;

the second output module is configured to provide a voltage of a second dc source to the output signal terminal under the control of the voltage of the second node;

the first node is located on a wire connecting the input module, the driving module and the reset module; the second node is located on a wire connecting the driving module, the reset module, the first output module and the second output module;

the first clock signal and the second clock signal are in opposite phase.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input module specifically includes: a first transistor; wherein,

the gate of the first transistor is connected to the first clock signal, the source thereof is connected to the input signal terminal, and the drain thereof is connected to the first node.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the driving module specifically includes: a second transistor and a first capacitor; wherein,

the grid electrode of the second transistor is connected with the first node, and the source electrode of the second transistor is connected with the second clock signal; the drain electrode of the first node is connected with the second node;

the first capacitor is connected between the gate of the second transistor and the drain of the second transistor.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module specifically includes: a third transistor, a fourth transistor, and a fifth transistor; wherein,

a gate of the third transistor is connected to the first clock signal, a source of the third transistor is connected to the second dc source, and a drain of the third transistor is connected to a drain of the fourth transistor and a gate of the fifth transistor, respectively;

a gate of the fourth transistor is connected to the first node, and a source thereof is connected to the first clock signal;

and the source electrode of the fifth transistor is connected with the first direct current source, and the drain electrode of the fifth transistor is connected with the second node.

Further, in the shift register provided in the embodiment of the present invention, the reset module further includes: a second capacitor; wherein,

the second capacitor is connected between the gate of the fifth transistor and the source of the fifth transistor.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output module specifically includes: a sixth transistor, a seventh transistor, an eighth transistor, and a third capacitor; wherein,

a gate of the sixth transistor is connected to the second node, a source of the sixth transistor is connected to the second dc source, and a drain of the sixth transistor is connected to a drain of the seventh transistor and a gate of the eighth transistor;

the grid electrode of the seventh transistor is connected with the first clock signal, and the source electrode of the seventh transistor is connected with the first direct current source;

the source electrode of the eighth transistor is connected with the second direct current source, and the drain electrode of the eighth transistor is connected with the output signal end;

the third capacitor is connected between the gate of the eighth transistor and the drain of the eighth transistor.

Alternatively, in a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output module specifically includes: a ninth transistor and a fourth capacitor; wherein,

a gate of the ninth transistor is connected to the second node, a source of the ninth transistor is connected to the low potential dc source, and a drain of the ninth transistor is connected to the output signal terminal;

the fourth capacitor is connected between the gate of the ninth transistor and the drain of the ninth transistor.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first output module specifically includes: a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein,

a gate of the tenth transistor is connected to the second node, a source of the tenth transistor is connected to the high-potential dc source, and a drain of the tenth transistor is connected to a drain of the eleventh transistor and a gate of the twelfth transistor, respectively;

the grid electrode of the eleventh transistor is connected with the first clock signal, and the source electrode of the eleventh transistor is connected with the low-potential direct current source;

and the source electrode of the twelfth transistor is connected with the high-potential direct current source, and the drain electrode of the twelfth transistor is connected with the output signal end.

Further, in the shift register provided in the embodiment of the present invention, the first output module further includes: a fifth capacitor; wherein,

the fifth capacitor is connected between the gate of the twelfth transistor and the source of the twelfth transistor.

Alternatively, in a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first output module specifically includes: a thirteenth transistor and a sixth capacitor, wherein,

the gate of the thirteenth transistor is connected to the second node, the source of the thirteenth transistor is connected to the high-potential direct-current source, and the drain of the thirteenth transistor is connected to the output signal terminal;

the sixth capacitor is connected between the gate of the thirteenth transistor and the drain of the thirteenth transistor.

Further, in the shift register provided in the embodiment of the present invention, the first to twelfth transistors are all P-type transistors, the first dc source is a high-potential dc source, and the second dc source is a low-potential dc source; or

The first to twelfth transistors are all N-type transistors, the first direct current source is a low-potential direct current source, and the second direct current source is a high-potential direct current source.

Specifically, in the shift register provided in the embodiment of the present invention, the thirteenth transistor is an N-type transistor, the first dc source is a high-potential dc source, and the second dc source is a low-potential dc source; or

The thirteenth transistor is a P-type transistor, the first direct current source is a low-potential direct current source, and the second direct current source is a high-potential direct current source.

Correspondingly, the embodiment of the invention also provides a gate driving circuit, which comprises a plurality of shift registers which are connected in series and provided by the embodiment of the invention; wherein,

the input signal end of the first stage shift register is connected with the initial signal end, and the input signal ends of the other shift registers except the first stage shift register are connected with the output signal end of the first stage shift register.

Correspondingly, the embodiment of the invention also provides a display device which comprises any one of the gate driving circuits provided by the embodiment of the invention.

The shift register, the gate driving circuit and the display device provided by the embodiment of the invention comprise: the device comprises an input module, a reset module, a driving module, a first output module and a second output module. Compared with a clock signal as an output source of the output signal, the direct-current power supply can avoid the problem of unstable output signal caused by the high-frequency periodic conversion characteristic of the clock signal, reduce the influence of line load on the output signal and improve the stability and reliability of the output signal output by the shift register.

Drawings

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 2a and fig. 2b are circuit timing diagrams of a shift register according to an embodiment of the present invention;

fig. 3a and fig. 3b are schematic structural diagrams of a shift register provided in an embodiment of the present invention, in which all transistors are P-type transistors;

fig. 4a and fig. 4b are schematic structural diagrams of a shift register in which all transistors are N-type transistors according to an embodiment of the present invention;

fig. 5a and 5b are schematic structural diagrams of a shift register including P-type transistors and N-type transistors according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

The following describes in detail specific embodiments of a shift register, a gate driver circuit, and a display device according to embodiments of the present invention with reference to the accompanying drawings.

As shown in fig. 1, a shift register according to an embodiment of the present invention includes: the device comprises an input module 1, a reset module 2, a driving module 3, a first output module 4 and a second output module 5; wherein,

an Input module 1, configured to provide an Input signal of an Input signal terminal Input to a first node a under control of a first clock signal CK;

the driving module 3 is used for providing a second clock signal CB to a second node B under the control of the voltage of the first node A; when no signal is transmitted between the Input signal end and the first node A, the voltage of the first node A is pulled up or pulled down;

a reset module 2 for supplying the voltage of the first dc power supply V1 to the second node B under the control of the voltage of the first node a and the first clock signal CK; and causing the first dc power supply V1 to stop supplying voltage to the second node B under the control of the voltage of the first node a;

the first Output module 4 is configured to provide the voltage of the first dc source V1 to the Output signal terminal Output under the control of the voltage of the second node B;

a second Output module 5, configured to provide the voltage of the second dc source V2 to the Output signal terminal Output under the control of the voltage of the second node B;

the first node A is positioned on a lead connecting the input module 1 with the driving module 3 and the resetting module 2; the second node B is positioned on a lead connecting the driving module 3 with the reset module 2, the first output module 4 and the second output module 5;

the first clock signal CK and the second clock signal CB have opposite phases.

The shift register provided in the embodiment of the present invention includes: the device comprises an input module, a reset module, a driving module, a first output module and a second output module. Compared with a clock signal as an output source of the output signal, the direct-current power supply can avoid the problem of unstable output signal caused by the high-frequency periodic conversion characteristic of the clock signal, reduce the influence of line load on the output signal and improve the stability and reliability of the output signal output by the shift register.

It should be noted that, in the shift register provided in the embodiment of the present invention, when the first dc source is a high-potential dc source, the second dc source is a low-potential dc source; when the first DC source is a low potential DC source, the second DC source is a high potential DC source.

The operation principle of the shift register provided by the embodiment of the present invention is briefly described below with reference to a circuit timing diagram.

Specifically, the operation of the shift register provided by the embodiment of the present invention may have three stages, as shown in fig. 2a and fig. 2b, which are respectively: a sampling phase T1, an output phase T2, and a reset phase T3;

in the sampling period T1, the Input signal terminal Input inputs an Input signal, and the Input module provides the Input signal of the Input signal terminal Input to the first node a under the control of the first clock signal CK; the reset module supplies the voltage of the first direct current power supply V1 to the second node B under the control of the voltage of the first node A and the first clock signal CK; the driving module supplies a second clock signal CB to a second node B under the control of the voltage of the first node A; at this time, the first Output module provides the voltage of the first dc source V1 to the Output signal terminal Output under the control of the voltage of the second node B;

in the output stage T2, no signal is transmitted between the Input signal terminal Input and the first node a; if the voltage of the first node A is a low-potential voltage in a last time period, the driving module pulls down the voltage of the first node A; if the voltage of the first node A is a high potential voltage in the last time period, the driving module pulls up the voltage of the first node A; and providing a second clock signal CB to a second node B under the control of the voltage of the first node a and the second clock signal CB; the reset module enables the first direct current power supply V1 to stop providing voltage to the second node B under the control of the voltage of the first node A; at this time, the second Output module provides the voltage of the second dc source V2 to the Output signal terminal Output under the control of the voltage of the second node B;

in the reset phase T3, the Input module makes the Input signal terminal Input and the first node a be in a conducting state under the control of the first clock signal CK; the reset module supplies the voltage of the first direct current power supply V1 to the second node B under the control of the voltage of the first node A and the first clock signal CK; at this time, the first Output module provides the voltage of the first dc source V1 to the Output signal terminal Output under the control of the voltage of the second node B.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

Preferably, in an implementation of the shift register according to an embodiment of the present invention, as shown in fig. 3a to 5b, the input module includes: a first transistor T1; wherein,

the first transistor T1 has a gate connected to the first clock signal CK, a source connected to the Input signal terminal Input, and a drain connected to the first node a.

Further, in the embodiment, as shown in fig. 3a and 3b, the first transistor T1 may be a P-type transistor, in which the first transistor T1 is turned on when the first clock signal CK is at a low level, and the first transistor T1 is turned off when the first clock signal CK is at a high level. Alternatively, as shown in fig. 4a and 4b, the first transistor T1 may be an N-type transistor, which is not limited herein.

The above is merely an example of the specific structure of the input module in the shift register, and in the specific implementation, the specific structure of the input module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Preferably, in an implementation of the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 5b, the driving module specifically includes: a second transistor T2 and a first capacitor C1; wherein,

a second transistor T2 having a gate connected to the first node a and a source connected to the second clock signal CB; the drain electrode of the first node B is connected with the first node B;

the first capacitor C1 is connected between the gate of the second transistor T2 and the drain of the second transistor T2. The first capacitor C1 is set to pull the voltage of the first node a low for the period T2 as shown in fig. 2a or high for the period T2 as shown in fig. 2b by the bootstrap action of the first capacitor C1 to keep the second transistor T2 in a conductive state.

Further, in the embodiment, as shown in fig. 3a and 3b, the second transistor T2 may be a P-type transistor, in which the second transistor T2 is turned on when the voltage of the first node a is at a low level, and the second transistor T2 is turned off when the voltage of the first node a is at a high level. Alternatively, as shown in fig. 4a and 4b, the second transistor T2 may be an N-type transistor, which is not limited herein.

The above is merely an example of the specific structure of the driving module in the shift register, and in the specific implementation, the specific structure of the driving module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, which is not limited herein.

Preferably, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a and fig. 4a, the reset module 2 may specifically include: a third transistor T3, a fourth transistor T4, and a fifth transistor T5; wherein,

a third transistor T3 having a gate connected to the first clock signal CK, a source connected to the second dc source V2, and a drain connected to the drain of the fourth transistor T4 and the gate of the fifth transistor T5, respectively;

a fourth transistor T4 having a gate connected to the first node a and a source connected to the first clock signal CK;

the fifth transistor T5 has a source connected to the first dc source V1 and a drain connected to the second node B.

Further, in practical implementation, as shown in fig. 3a and 3b, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be P-type transistors, in which the third transistor T3 is turned on when the first clock signal CK is at a low potential, and the third transistor T3 is turned off when the first clock signal CK is at a high potential; the fourth transistor T4 is turned on when the voltage of the first node a is low, and the fourth transistor T4 is turned off when the voltage of the first node a is high; the fifth transistor T5 is turned on when the voltage of the gate of the fifth transistor T5 is a low potential, and the fifth transistor T5 is turned off when the voltage of the gate of the fifth transistor T5 is a high potential. Alternatively, as shown in fig. 4a and 4b, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be N-type transistors, which is not limited herein.

Further, in the shift register provided in the embodiment of the present invention, in order to better maintain the gate voltage of the fifth transistor T5, as shown in fig. 3b and fig. 4b, the reset module may further include: a second capacitance C2; wherein,

the second capacitor C2 is connected between the gate of the fifth transistor T5 and the source of the fifth transistor T5.

The above is only an example of the specific structure of the reset module in the shift register, and in the specific implementation, the specific structure of the reset module is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Preferably, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the second output module may specifically include: a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, and a third capacitor C3; wherein,

a sixth transistor T6 having a gate connected to the second node B, a source connected to the second direct current source V2, and a drain connected to the drain of the seventh transistor T7 and the gate of the eighth transistor T8;

a seventh transistor T7 having a gate connected to the first clock signal CK and a source connected to the first dc source V1;

an eighth transistor T8, a source thereof is connected to the second dc source V2, and a drain thereof is connected to the Output signal terminal Output;

the third capacitor C3 is connected between the gate of the eighth transistor T8 and the drain of the eighth transistor T8. Specifically, the third capacitor C3 is provided in the second output module to pull the gate voltage of the eighth transistor T8 low during the T2 period as shown in fig. 2a or pull the gate voltage of the eighth transistor T8 high during the T2 period as shown in fig. 2b to keep the eighth transistor T8 in a conductive state through the bootstrap effect of the third capacitor C3.

Further, in practical implementation, as shown in fig. 3a and 3B, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, and at this time, the sixth transistor T6 is turned on when the voltage of the second node B is low, and the sixth transistor T6 is turned off when the voltage of the second node B is high; the seventh transistor T7 is turned on when the first clock signal CK is at a low potential, and the seventh transistor T7 is turned off when the first clock signal CK is at a high potential; the eighth transistor T8 is turned on when the voltage of the gate of the eighth transistor T8 is a low potential, and the eighth transistor T8 is turned off when the voltage of the gate of the eighth transistor T8 is a high potential. Alternatively, as shown in fig. 4a and 4b, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be N-type transistors, which is not limited herein.

Alternatively, in order to simplify the circuit structure, in the shift register provided in the embodiment of the present invention, as shown in fig. 5a and 5b, the second output module may specifically include: a ninth transistor T9 and a fourth capacitor C4; wherein,

a ninth transistor T9, having a gate connected to the second node B, a source connected to the second dc source V2, and a drain connected to the Output signal terminal Output;

the fourth capacitor C4 is connected between the gate of the ninth transistor T9 and the drain of the ninth transistor T9. Specifically, the fourth capacitor C4 is provided in the second output block to ensure stability of the gate voltage of the ninth transistor T9.

Further, in a specific implementation, as shown in fig. 5a, the ninth transistor T9 may be a P-type transistor. The ninth transistor T9 is turned on when the voltage of the second node B is at a low potential, and at this time, the ninth transistor T9 is turned off when the voltage of the second node B is at a high potential. Alternatively, as shown in fig. 5b, the ninth transistor T9 may be an N-type transistor, which is not limited herein.

The above is merely to illustrate a specific structure of the second output module in the shift register, and in a specific implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the first output module may specifically include: a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; wherein,

a tenth transistor T10 having a gate connected to the second node B, a source connected to the first dc source V1, and drains connected to the drain of the eleventh transistor T11 and the gate of the twelfth transistor T12, respectively;

an eleventh transistor T11 having a gate connected to the first clock signal CK and a source connected to the second dc source V2;

the twelfth transistor T12 has a source connected to the first dc source V1, and a drain connected to the Output signal terminal Output.

Further, in practical implementation, as shown in fig. 3a and 3B, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be P-type transistors, and at this time, the tenth transistor T10 is turned on when the voltage of the second node B is low, and the tenth transistor T10 is turned off when the voltage of the second node B is high; the eleventh transistor T11 is turned on when the first clock signal CK is at a low potential, and the eleventh transistor T11 is turned off when the first clock signal CK is at a high potential; the twelfth crystal T12 is turned on when the voltage of the gate of the twelfth crystal T12 is low, and the twelfth crystal T12 is turned off when the voltage of the gate of the twelfth crystal T12 is high. Alternatively, as shown in fig. 4a and 4b, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be N-type transistors, which is not limited herein.

Preferably, in the shift register according to the embodiment of the present invention, in order to better maintain the gate voltage of the twelfth transistor T12, as shown in fig. 3b and fig. 4b, the first output module may further include: a fifth capacitance C5; wherein,

the fifth capacitor C5 is connected between the gate of the twelfth transistor T12 and the source of the twelfth transistor T12.

Alternatively, to simplify the circuit structure, in the shift register provided in the embodiment of the present invention, as shown in fig. 5a and 5b, the first output module may specifically include: a thirteenth transistor T13 and a sixth capacitor C6, wherein,

a thirteenth transistor T13, having a gate connected to the second node B, a source connected to the first dc source V1, and a drain connected to the Output signal terminal Output;

the sixth capacitor C6 is connected between the gate of the thirteenth transistor T13 and the drain of the thirteenth transistor T13.

Specifically, the sixth capacitor C6 is provided in the first output block to ensure stability of the gate voltage of the thirteenth transistor T13.

Further, in an implementation, as shown in fig. 5a, the thirteenth transistor T13 may be an N-type transistor, and at this time, the thirteenth transistor T13 is turned on when the voltage of the second node B is high, and the thirteenth transistor T13 is turned off when the voltage of the second node B is low. Alternatively, as shown in fig. 5b, the thirteenth transistor T13 may be a P-type transistor, which is not limited herein.

The above is merely an example of the specific structure of the first output module in the shift register, and in the specific implementation, the specific structure of the first output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Preferably, in the shift register provided in the embodiment of the present invention, the transistors generally use transistors of the same material, and in order to simplify the manufacturing process, the first to twelfth transistors all use P-type transistors or N-type transistors. When the first to twelfth transistors are all P-type transistors, the first direct current source is a high-potential direct current source, and the second direct current source is a low-potential direct current source; or when the first to twelfth transistors are N-type transistors, the first direct current source is a low-potential direct current source, and the second direct current source is a high-potential direct current source.

For the shift register with the first output module having the structure of the thirteenth transistor and the sixth capacitor, as shown in fig. 5a, when the thirteenth transistor is an N-type transistor, the first dc source is a high-potential dc source, and the second dc source is a low-potential dc source; or, as shown in fig. 5b, when the thirteenth transistor is a P-type transistor, the first dc source is a low-potential dc source, and the second dc source is a high-potential dc source.

It should be noted that the Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), and is not limited herein. In specific implementation, the functions of the sources and the drains of the transistors can be interchanged according to the types of the transistors and different input signals, and are not particularly distinguished.

The operation of the shift register according to the embodiment of the present invention will be described below by taking the input/output timing diagrams shown in fig. 2a and fig. 2b as examples. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0.

Example one:

the operation of the shift register shown in fig. 3b is described by taking the structure of the shift register as an example, wherein in the shift register shown in fig. 3b, all the transistors are P-type transistors, and each P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential; the first direct current source is a high potential direct current source, and the second direct current source is a low potential direct current source; the corresponding input/output timing diagram is shown in fig. 2 a. Specifically, three phases T1, T2, and T3 in the input-output timing diagram shown in fig. 2a are selected.

In stage T1, Input is 0, CK is 0, and CB is 1. Since CK is equal to 0, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eleventh transistor T11 are all turned on; since the first transistor T1 is turned on and Input is 0, the potential of the first node a is low; since the potential of the first node a is low, the fourth transistor T4 and the second transistor T2 are turned on to charge the second capacitor C2; since CK is 0, the gate of the fifth transistor T5 is at a low potential, the fifth transistor T5 is turned on, and the voltage of the first dc source is supplied to the second node B; since the second transistor T2 is turned on, CB is 1, and thus the turned-on second transistor T2 supplies the second clock signal CB at the high potential to the second node B, so that the potential of the second node B is at the high potential, and the first capacitor C1 is charged; since the potential of the second node B is a high potential, the sixth transistor T6 and the tenth transistor T10 are turned off; the gate of the eighth transistor T8 is at a high potential, and the eighth transistor is turned off; the gate of the twelfth transistor T12 is at a low potential to charge the fifth capacitor C5, and the twelfth transistor T12 is turned on to supply the voltage of the first dc source V1 to the Output signal terminal Output, so that the Output signal terminal Output outputs a high-potential Output signal.

In stage T2, Input is 1, CK is 1, and CB is 0. Since CK is 1, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eleventh transistor T11 are all turned off; since the first transistor T1 is turned off, the potential of the first node a is low, and thus the fourth transistor T4 and the second transistor T2 are turned on; since CK is equal to 1, the gate of the fifth transistor T5 is at a high potential, the fifth transistor T5 is turned off, and at this stage, the potential at both ends of the second capacitor C2 is at a high potential to better maintain the gate of the fifth transistor T5 at the high potential; since the second transistor T2 is turned on and CB is equal to 0, the turned-on second transistor T2 supplies the second clock signal CB having a low potential to the second node B, and thus the potential of the second node B is a low potential; since the potential of the second node B is low, according to the bootstrap action of the first capacitor C1, in order to maintain the voltage difference between the two ends of the first capacitor C1, the potential of the first node a is further pulled low to ensure that the fourth transistor T4 and the second transistor T2 are turned on at this stage; since the potential of the second node B is a low potential, the sixth transistor T6 and the tenth transistor T10 are turned on; the gate of the twelfth transistor T12 is at a high potential, the twelfth transistor T12 is turned off, and at this stage, the fifth capacitor C5 discharges to make the potentials at the two ends of the fifth capacitor C5 at the high potential, so as to better maintain the gate of the twelfth transistor T12 at the high potential; the gate of the eighth transistor T8 is at a low potential, the eighth transistor T8 is turned on and provides the voltage of the second dc source V2 to the Output signal terminal Output, so that the Output signal terminal Output outputs a low potential Output signal; meanwhile, due to the bootstrap action of the third capacitor C3, in order to maintain the voltage difference across the third capacitor C3, the potential of the gate of the eighth transistor T8 is further pulled low to ensure that the eighth transistor T8 is turned on at this stage.

In stage T3, Input is 1, CK is 0, and CB is 1. Since CK is equal to 0, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eleventh transistor T11 are all turned on; since the first transistor T1 is turned on and Input is 1, the potential of the first node a is high; since the potential of the first node a is a high potential, the fourth transistor T4 and the second transistor T2 are turned off; since CK is equal to 0, the gate of the fifth transistor T5 is at a low potential, the second capacitor C2 is charged, the fifth transistor T5 is turned on and supplies the voltage of the first dc source V1 to the second node B, so the potential of the second node B is at a high potential, and at this stage, the first capacitor C1 discharges, and the potentials at the two ends are at a high potential, so as to better maintain the potential of the gate of the second transistor T2 at a high potential; since the potential of the second node B is a high potential, the sixth transistor T6 and the tenth transistor T10 are turned off; the gate of the eighth transistor T8 is at a high potential, and the eighth transistor is turned off; the gate of the twelfth transistor T12 is at a low potential to charge the fifth capacitor C5, the twelfth transistor T12 is turned on to supply the voltage of the first dc source V1 to the Output signal terminal Output, so that the Output signal terminal Output outputs a high-potential Output signal, and the potentials at the two ends of the third capacitor C3 are both at a high potential during the discharging process, so as to better maintain the potential at the gate of the eighth transistor T8 at a high potential.

Compared with the clock signal as the output source of the output signal, the direct current power supply of the shift register can not only avoid the problem of unstable output signal caused by the high-frequency periodic conversion characteristic of the clock signal, but also reduce the influence of line load on the output signal, thereby improving the stability and reliability of the output signal output by the shift register.

Specifically, the working process of the shift register with the structure shown in fig. 3a is the same as that described in the first example, except that the second capacitor and the fifth capacitor are omitted, and further description is omitted here.

Example two:

the operation of the shift register shown in fig. 4b is described by taking the structure of the shift register as an example, wherein in the shift register shown in fig. 4b, all transistors are N-type transistors, and each N-type transistor is turned off under the action of a low potential and turned on under the action of a high potential; the first direct current source is a low potential direct current source, and the second direct current source is a high potential direct current source; the corresponding input/output timing diagram is shown in fig. 2 b. Specifically, three phases T1, T2, and T3 in the input-output timing diagram shown in fig. 2b are selected.

In stage T1, Input is 1, CK is 1, and CB is 0. Since CK is 1, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eleventh transistor T11 are all turned on; since the first transistor T1 is turned on and Input is 1, the potential of the first node a is high; since the potential of the first node a is a high potential, the fourth transistor T4 and the second transistor T2 are turned on to charge the second capacitor C2; since CK is 1, the gate of the fifth transistor T5 is at a high potential, the fifth transistor T5 is turned on, and the voltage of the first dc source is supplied to the second node B; since the second transistor T2 is turned on and CB is equal to 0, the turned-on second transistor T2 supplies the second clock signal CB having a low potential to the second node B, so that the potential of the second node B is low, and the first capacitor C1 is charged; since the potential of the second node B is a low potential, the sixth transistor T6 and the tenth transistor T10 are turned off; the gate of the eighth transistor T8 is at a low potential, and the eighth transistor is turned off; the gate of the twelfth transistor T12 is at a high potential to charge the fifth capacitor C5, and the twelfth transistor T12 is turned on to supply the voltage of the first dc source V1 to the Output signal terminal Output, so that the Output signal terminal Output outputs a low-potential Output signal.

In stage T2, Input is 0, CK is 0, and CB is 1. Since CK is equal to 0, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eleventh transistor T11 are all turned off; since the first transistor T1 is turned off, the potential of the first node a is a high potential, and thus the fourth transistor T4 and the second transistor T2 are turned on; since CK is equal to 0, the gate of the fifth transistor T5 is at a low potential, the fifth transistor T5 is turned off, and at this stage, the potential at both ends of the second capacitor C2 is at a low potential, so as to better maintain the potential at the gate of the fifth transistor T5 at a low potential; since the second transistor T2 is turned on, CB is 1, and thus the turned-on second transistor T2 supplies the second clock signal CB of the high potential to the second node B, and thus the potential of the second node B is the high potential; since the potential of the second node B is high, according to the bootstrap action of the first capacitor C1, in order to maintain the voltage difference between the two ends of the first capacitor C1, the potential of the first node a is further pulled high to ensure that the fourth transistor T4 and the second transistor T2 are turned on at this stage; since the potential of the second node B is a high potential, the sixth transistor T6 and the tenth transistor T10 are turned on; the gate of the twelfth transistor T12 is at a low potential, the twelfth transistor T12 is turned off, and at this stage, the fifth capacitor C5 discharges to make the potentials at the two ends thereof at a low potential, so as to better maintain the potential at the gate of the twelfth transistor T12 at a low potential; the gate of the eighth transistor T8 is at a high potential, the eighth transistor T8 is turned on and provides the voltage of the second dc source V2 to the Output signal terminal Output, so that the Output signal terminal Output outputs a high potential Output signal; meanwhile, due to the bootstrap action of the third capacitor C3, in order to maintain the voltage difference across the third capacitor C3, the potential of the gate of the eighth transistor T8 is further pulled high to ensure that the eighth transistor T8 is turned on at this stage.

In stage T3, Input is 0, CK is 1, and CB is 0. Since CK is 1, the first transistor T1 and the third transistor T3 are both turned on; since the first transistor T1 is turned on and Input is 0, the potential of the first node a is low; since the potential of the first node a is a low potential, the fourth transistor T4 and the second transistor T2 are turned off; since CK is equal to 1, the gate of the fifth transistor T5 is at a high potential, the second capacitor C2 is charged, the fifth transistor T5 is turned on and provides the voltage of the first dc source to the second node B, so the potential of the second node B is at a low potential, and at this stage, the first capacitor C1 discharges, and the potentials at the two ends are at a low potential, so as to better maintain the potential of the gate of the second transistor T2 at a low potential; since the potential of the second node B is a low potential, the sixth transistor T6 and the tenth transistor T10 are turned off; the gate of the eighth transistor T8 is at a low potential, and the eighth transistor is turned off; the gate of the twelfth transistor T12 is at a high potential to charge the fifth capacitor C5, the twelfth transistor T12 is turned on to supply the voltage of the first dc source V1 to the Output signal terminal Output, so the Output signal terminal Output outputs a low potential Output signal, and the potential at both ends of the third capacitor C3 during the discharging is at a low potential, so as to better maintain the potential at the gate of the eighth transistor T8 at a low potential.

Specifically, the working process of the shift register with the structure shown in fig. 4a is the same as that described in the second example, except that the second capacitor and the fifth capacitor are omitted, and further description is omitted here.

Example three

The operation of the shift register shown in fig. 5a is described by taking the structure of the shift register as an example, wherein in the shift register shown in fig. 5a, except that the thirteenth transistor is an N-type transistor, all the transistors are P-type transistors. The N-type transistor is cut off under the action of low potential and is conducted under the action of high potential; each P-type transistor is cut off under the action of high potential and is conducted under the action of low potential; the first direct current source is a high potential direct current source, and the second direct current source is a low potential direct current source; the corresponding input/output timing diagram is shown in fig. 2 a. Specifically, three phases T1, T2, and T3 in the input-output timing diagram shown in fig. 2a are selected.

In stage T1, Input is 0, CK is 0, and CB is 1. Since CK is 0, both the first transistor T1 and the third transistor T3 are turned on; since the first transistor T1 is turned on and Input is 0, the potential of the first node a is low; since the potential of the first node a is low, the fourth transistor T4 and the second transistor T2 are turned on to charge the second capacitor C2; since CK is 0, the gate of the fifth transistor T5 is at a low potential, the fifth transistor T5 is turned on, and the voltage of the first dc source is supplied to the second node B; since the second transistor T2 is turned on, CB is 1, and thus the turned-on second transistor T2 supplies the second clock signal CB at the high potential to the second node B, so that the potential of the second node B is at the high potential, and the first capacitor C1 is charged; since the potential of the second node B is high, the ninth transistor T9 is turned off, the potential of the end of the sixth capacitor C6 connected to the second node B is high, the potential of the other end of the sixth capacitor C6 is low at this moment, the thirteenth transistor T13 is turned on, and the voltage of the first dc source V1 is supplied to the Output signal terminal Output, so the Output signal terminal Output outputs a high-potential Output signal; in addition, at this stage, since the thirteenth transistor T13 is turned on, the potential of the other end of the sixth capacitor C6 gradually rises, and since the capacitor has an effect of maintaining a voltage difference between the two ends of the capacitor, the potential of the end of the sixth capacitor C6 connected to the second node B is gradually pulled up along with the gradual rise of the potential of the other end, so that the gate voltage of the thirteenth transistor T13 is further pulled up, and the stability of the turn-on of the thirteenth transistor T13 at this stage is ensured.

In stage T2, Input is 1, CK is 1, and CB is 0. Since CK is 1, both the first transistor T1 and the third transistor T3 are turned off; since the first transistor T1 is turned off, the potential of the first node a is low, and thus the fourth transistor T4 and the second transistor T2 are turned on; since CK is equal to 1, the gate of the fifth transistor T5 is at a high potential, the fifth transistor T5 is turned off, and at this stage, the potential at both ends of the second capacitor C2 is at a high potential to better maintain the gate of the fifth transistor T5 at the high potential; since the second transistor T2 is turned on and CB is equal to 0, the turned-on second transistor T2 supplies the second clock signal CB having a low potential to the second node B, and thus the potential of the second node B is a low potential; since the potential of the second node B is low, according to the bootstrap action of the first capacitor C1, in order to maintain the voltage difference between the two ends of the first capacitor C1, the fourth transistor T4 and the second transistor T2 are enabled to be turned on at this stage; since the potential of the second node B is low, the thirteenth transistor T13 is turned off, the potential of the end of the fourth capacitor C4 connected to the second node B is low, and at this moment, when the potential of the other end of the fourth capacitor C4 is still at the stage T1, the potential of the Output signal end Output is high, the ninth transistor T9 is turned on and provides the voltage of the second dc source V2 to the Output signal end Output, so the Output signal end Output outputs a low-potential Output signal; in addition, at this stage, since the ninth transistor T9 is turned on, the potential at the other end of the fourth capacitor C4 gradually decreases, and since the capacitor has an effect of maintaining a voltage difference between the two ends of the capacitor, the potential at one end of the fourth capacitor C4 connected to the second node B is gradually pulled down as the potential at the other end of the fourth capacitor C4 gradually decreases, so that the gate voltage of the ninth transistor T9 is further pulled down, and the stability of turning on the ninth transistor T9 at this stage is ensured.

In stage T3, Input is 1, CK is 0, and CB is 1. Since CK is 0, both the first transistor T1 and the third transistor T3 are turned on; since the first transistor T1 is turned on and Input is 1, the potential of the first node a is high; since the potential of the first node a is a high potential, the fourth transistor T4 and the second transistor T2 are turned off; since CK is equal to 0, the gate of the fifth transistor T5 is at a low potential, the second capacitor C2 is charged, the fifth transistor T5 is turned on and supplies the voltage of the first dc source V1 to the second node B, so the potential of the second node B is at a high potential, and at this stage, the first capacitor C1 discharges, and the potentials at the two ends are at a high potential, so as to better maintain the potential of the gate of the second transistor T2 at a high potential; since the potential of the second node B is a high potential, the ninth transistor T9 is turned off, the potential of the end of the sixth capacitor C6 connected to the second node B is a high potential, and at this moment, when the potential of the other end of the sixth capacitor C6 is still at the stage T2, the potential of the Output signal terminal Output is a low potential, the thirteenth transistor T13 is turned on and supplies the voltage of the first dc source V1 to the Output signal terminal Output, and therefore the Output signal terminal Output outputs a high-potential Output signal; in addition, at this stage, since the thirteenth transistor T13 is turned on, the potential of the other end of the sixth capacitor C6 gradually rises, and since the capacitor has an effect of maintaining a voltage difference between the two ends of the capacitor, the potential of the end of the sixth capacitor C6 connected to the second node B is gradually pulled up along with the gradual rise of the potential of the other end, so that the gate voltage of the thirteenth transistor T13 is further pulled up, and the stability of the turn-on of the thirteenth transistor T13 at this stage is ensured.

Example four

The operation of the shift register shown in fig. 5b is described by taking the structure of the shift register as an example, wherein in the shift register shown in fig. 5b, except that the thirteenth transistor is a P-type transistor, the other transistors are N-type transistors. The N-type transistor is cut off under the action of low potential and is conducted under the action of high potential; each P-type transistor is cut off under the action of high potential and is conducted under the action of low potential; the first direct current source is a low potential direct current source, and the second direct current source is a high potential direct current source; the corresponding input/output timing diagram is shown in fig. 2 b. Specifically, three phases T1, T2, and T3 in the input-output timing diagram shown in fig. 2b are selected.

In stage T1, Input is 1, CK is 1, and CB is 0. Since CK is 1, the first transistor T1 and the third transistor T3 are both turned on; since the first transistor T1 is turned on and Input is 1, the potential of the first node a is high; since the potential of the first node a is a high potential, the fourth transistor T4 and the second transistor T2 are turned on to charge the second capacitor C2; since CK is 1, the gate of the fifth transistor T5 is at a high potential, the fifth transistor T5 is turned on, and the voltage of the first dc source is supplied to the second node B; since the second transistor T2 is turned on and CB is equal to 0, the turned-on second transistor T2 supplies the second clock signal CB having a low potential to the second node B, so that the potential of the second node B is low, and the first capacitor C1 is charged; since the potential of the second node B is low, the ninth transistor T9 is turned off, the potential of the end of the sixth capacitor C6 connected to the second node B is low, the potential of the other end of the sixth capacitor C6 is high at this moment, the thirteenth transistor T13 is turned on, and the voltage of the first dc source V1 is supplied to the Output signal terminal Output, so the Output signal terminal Output outputs a low-potential Output signal; in addition, at this stage, since the thirteenth transistor T13 is turned on, the potential of the other end of the sixth capacitor C6 gradually decreases, and since the capacitor has an effect of maintaining a voltage difference between the two ends thereof, the potential of the end of the sixth capacitor C6 connected to the second node B is gradually pulled down as the potential of the other end gradually decreases, so that the gate voltage of the thirteenth transistor T13 is further pulled down, and the stability of the turn-on of the thirteenth transistor T13 at this stage is ensured.

In stage T2, Input is 0, CK is 0, and CB is 1. Since CK is 0, the first transistor T1 and the third transistor T3 are all turned off; since the first transistor T1 is turned off, the potential of the first node a is a high potential, and thus the fourth transistor T4 and the second transistor T2 are turned on; since CK is equal to 0, the gate of the fifth transistor T5 is at a low potential, the fifth transistor T5 is turned off, and at this stage, the potential at both ends of the second capacitor C2 is at a low potential, so as to better maintain the potential at the gate of the fifth transistor T5 at a low potential; since the second transistor T2 is turned on, CB is 1, and thus the turned-on second transistor T2 supplies the second clock signal CB of the high potential to the second node B, and thus the potential of the second node B is the high potential; since the potential of the second node B is high, according to the bootstrap action of the first capacitor C1, in order to maintain the voltage difference between the two ends of the first capacitor C1, the potential of the first node a is further pulled high to ensure that the fourth transistor T4 and the second transistor T2 are turned on at this stage; since the potential of the first node a is a high potential, the fourth transistor T4 and the second transistor T2 are turned on; since CK is 0, the gate of the fifth transistor T5 is at a low potential, and the fifth transistor T5 is turned off; since the second transistor T2 is turned on, CB is 1, and thus the turned-on second transistor T2 supplies the second clock signal CB of the high potential to the second node B, and thus the potential of the second node B is the high potential; since the potential of the second node B is a high potential, the thirteenth transistor T13 is turned off, the potential of the end of the fourth capacitor C4 connected to the second node B is a high potential, and at this moment, when the potential of the other end of the fourth capacitor C4 is still at the stage T1, the potential of the Output signal terminal Output is a low potential, the ninth transistor T9 is turned on and supplies the voltage of the second dc source V2 to the Output signal terminal Output, so that the Output signal terminal Output outputs a high-potential Output signal; in addition, at this stage, since the ninth transistor T9 is turned on, the potential at the other end of the fourth capacitor C4 gradually rises, and since the capacitor has an effect of maintaining a voltage difference between the two ends of the capacitor, the potential at one end of the fourth capacitor C4 connected to the second node B is gradually pulled up along with the gradual rise of the potential at the other end, so that the gate voltage of the ninth transistor T9 is further pulled up, and the stability of turning on the ninth transistor T9 at this stage is ensured.

In stage T3, Input is 0, CK is 1, and CB is 0. Since CK is 1, the first transistor T1 and the third transistor T3 are both turned on; since the first transistor T1 is turned on and Input is 0, the potential of the first node a is low; since the potential of the first node a is a low potential, the fourth transistor T4 and the second transistor T2 are turned off; since CK is equal to 1, the gate of the fifth transistor T5 is at a high potential, the second capacitor C2 is charged, the fifth transistor T5 is turned on and provides the voltage of the first dc source to the second node B, so the potential of the second node B is at a low potential, and at this stage, the first capacitor C1 discharges, and the potentials at the two ends are at a low potential, so as to better maintain the potential of the gate of the second transistor T2 at a low potential; since the potential of the second node B is low, the ninth transistor T9 is turned off, the potential of the end of the sixth capacitor C6 connected to the second node B is low, and at this moment, when the potential of the other end of the sixth capacitor C6 is still at the stage T2, the potential of the Output signal end Output is high, the thirteenth transistor T13 is turned on and supplies the voltage of the first dc source V1 to the Output signal end Output, so the Output signal end Output outputs a low-potential Output signal; in addition, at this stage, since the thirteenth transistor T13 is turned on, the potential of the other end of the sixth capacitor C6 gradually decreases, and since the capacitor has an effect of maintaining a voltage difference between the two ends thereof, the potential of the end of the sixth capacitor C6 connected to the second node B is gradually pulled down as the potential of the other end gradually decreases, so that the gate voltage of the thirteenth transistor T13 is further pulled down, and the stability of the turn-on of the thirteenth transistor T13 at this stage is ensured.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 6, including a plurality of shift registers connected in series: SR (1), SR (2) … SR (N) … SR (N-1), SR (N) (N shift registers in total, N is more than or equal to 1 and less than or equal to N), the Input signal end Input of the first stage shift register SR (1) is connected with the start signal end STV, and the Input signal ends Input of the other stages of shift registers SR (N) except the first stage shift register SR (1) are connected with the Output signal end Output _ N-1 of the first stage shift register SR (N-1). The gate driving circuit sequentially outputs the Output signals Output from the Output signal terminals Output _ n of the shift registers sr (n) of the respective stages.

Further, in the gate driving circuit according to the embodiment of the present invention, the first clock signal CK, the second clock signal CB, the low potential dc source VL, and the high potential dc source VH are all input into each stage of the shift register.

Specifically, the specific structure of each shift register in the gate driving circuit is the same as that of the shift register of the present invention in function and structure, and repeated descriptions are omitted.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the gate driving circuit, where the gate driving circuit provides a scan signal for each gate line on an array substrate in the display device, and specific implementation of the display device may refer to the description of the gate driving circuit, and details of the same are omitted.

The shift register, the gate driving circuit and the display device provided by the embodiment of the invention include: the device comprises an input module, a reset module, a driving module, a first output module and a second output module. Compared with a clock signal as an output source of the output signal, the direct-current power supply can avoid the problem of unstable output signal caused by the high-frequency periodic conversion characteristic of the clock signal, reduce the influence of line load on the output signal and improve the stability and reliability of the output signal output by the shift register.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register, comprising: the device comprises an input module, a reset module, a driving module, a first output module and a second output module; wherein,

the first clock signal and the second clock signal are in opposite phase;

the first output module specifically includes: a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein the tenth transistor has a gate connected to the second node, a source connected to the first dc source, and a drain connected to the drain of the eleventh transistor and the gate of the twelfth transistor, respectively; the gate of the eleventh transistor is connected to the first clock signal, and the source of the eleventh transistor is connected to the second dc source; and the source electrode of the twelfth transistor is connected with the first direct current source, and the drain electrode of the twelfth transistor is connected with the output signal end.

2. The shift register of claim 1, wherein the input module specifically comprises: a first transistor; wherein,

3. The shift register according to claim 1, wherein the driving module specifically comprises: a second transistor and a first capacitor; wherein,

4. The shift register of claim 1, wherein the reset module specifically comprises: a third transistor, a fourth transistor, and a fifth transistor; wherein,

5. The shift register of claim 4, wherein the reset module further comprises: a second capacitor; wherein,

6. The shift register of claim 1, wherein the second output module specifically comprises: a sixth transistor, a seventh transistor, an eighth transistor, and a third capacitor; wherein,

7. The shift register of claim 1, wherein the second output module specifically comprises: a ninth transistor and a fourth capacitor; wherein,

the ninth transistor is connected with the second node at the grid electrode, the low-potential direct current source at the source electrode and the output signal end at the drain electrode;

8. The shift register of claim 1, wherein the first output module further comprises: a fifth capacitor; wherein,

9. A shift register as claimed in any one of claims 2 to 8, characterized in that:

all the transistors are P-type transistors, the first direct current source is a high-potential direct current source, and the second direct current source is a low-potential direct current source; or

All the transistors are N-type transistors, the first direct current source is a low-potential direct current source, and the second direct current source is a high-potential direct current source.

10. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 9 connected in series; wherein,

11. A display device comprising the gate driver circuit according to claim 10.