CN104143552B - A kind of electronics trapping memory cells - Google Patents
A kind of electronics trapping memory cells Download PDFInfo
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- CN104143552B CN104143552B CN201310164838.XA CN201310164838A CN104143552B CN 104143552 B CN104143552 B CN 104143552B CN 201310164838 A CN201310164838 A CN 201310164838A CN 104143552 B CN104143552 B CN 104143552B
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- 239000004020 conductor Substances 0.000 claims abstract description 4
- 230000005264 electron capture Effects 0.000 claims description 26
- 238000010893 electron trap Methods 0.000 claims description 10
- 229910019044 CoSix Inorganic materials 0.000 claims description 3
- 229910005889 NiSix Inorganic materials 0.000 claims description 3
- 229910010421 TiNx Inorganic materials 0.000 claims description 3
- 229910008486 TiSix Inorganic materials 0.000 claims description 3
- 229910008764 WNx Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 abstract 2
- 230000005611 electricity Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003856 quaternary ammonium compounds Chemical class 0.000 description 1
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Abstract
The invention discloses a kind of electronics trapping memory cells, raceway groove is included（26）And the insulating barrier between two neighboring raceway groove（25）, and also include raceway groove control gate（27）, positioned at insulating barrier（25）In, and be the good conductor of electricity.The present invention is by adding raceway groove control gate, the raceway groove in a physical significance is controlled close to the both sides of raceway groove control gate, that is the first memory cell and the second memory cell open and close respectively, the memory cell of such a prior art can store two information, therefore, storage density uprises, and unit carrying cost reduces.
Description
Technical Field
The invention relates to the field of memory cells, in particular to an electronic capture memory cell.
Background
In electron capture (Charge Trap) memory technology, in particular SONOS memory technology, one physical memory cell can be used to store two bits of information, as shown below.
FIG. 1a is a schematic diagram of a prior art electron capture memory cell; 3 FIG. 31 3 b 3 is 3 a 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 31 3 a 3; 3 FIG. 1c is a cross-sectional view taken along line B-B' of FIG. 1 a; FIG. 1d is a cross-sectional view taken along line C-C 'of FIG. 1b, wherein FIG. 1d is an overall cross-sectional view of the memory cell taken along line C-C'.
As shown in fig. 1a to 1d, the prior art electron trap memory cell includes a control gate 11, a memory cell 13, an insulating dielectric 12 between the control gate 11 and the memory cell 13, a tunnel insulating dielectric 14, a channel 16, and an insulating layer 15 between two adjacent channels. As can be seen from fig. 1c and 1d, the prior art has one channel 16 and two dummy memory cells 131 and 132 in the memory cell 13.
The memory technology uses the principle of hot electron injection, since electrons can not freely move in the material of the memory cell 13, by changing the positions of the source and drain of the memory cell during writing, electrons can be selectively stored in two dummy memory cells 131 and 132, which are respectively positioned at two sides of the control gate 11, of one physical memory cell 13 by the principle of hot electron injection, and each dummy memory cell can be used for storing one bit of information, so that one physical memory cell 13 can be used for storing two bits of information.
In order to increase the storage density, reduce the unit storage cost, and continuously reduce the nodes, but with the continuous reduction of the nodes, the process is more and more difficult, and the method for reducing the cost of the unit storage unit by reducing the nodes is more and more difficult, in the prior art, one physical storage unit can only store two bits of information, the storage density is not high enough, and the unit storage cost is high.
Disclosure of Invention
Therefore, the invention provides an electron capture memory cell, which can improve the storage density of the electron capture memory cell.
The invention provides an electron capture memory cell, comprising a channel (26) and an insulating layer (25) between two adjacent channels, and further comprising:
a channel control gate (27) located in the insulating layer (25) and being a good electrical conductor.
Preferably, the channel control gate (27) is used to control the opening and closing of the first storage channel (261) and the second storage channel (262) on both sides of the channel (26).
Preferably, the number of the channel control gates (27) in each of the insulating layers (25) is 1.
Preferably, one of the channel control gates (27) controls the opening and closing of the second storage channel (262) of the channel on one side and controls the opening and closing of the first storage channel (261) of the channel on the other side.
Preferably, the number of the channel control gates (27) in each of the insulating layers (25) is 2.
Preferably, one of the channel control gates is for controlling opening and closing of the second storage channel (262) of the channel on one side, and the other channel control gate is for controlling opening and closing of the first storage channel (261) of the channel on the other side.
Preferably, the channel control gate (27) is Cu, W, Al, Ta metal, or TiNx，WNx，CoSix,NiSix,TiSixA compound is provided.
Preferably, the memory cell (23) of the electron capture memory cell is open.
Preferably, the memory cells (23) of the electron capture memory cells are contiguous.
Preferably, the electron capture memory cell is a SONOS memory cell.
According to the invention, the channel control grid is added, and a channel in a physical sense is controlled to be close to two sides of the channel control grid, namely the first storage unit and the second storage unit are respectively opened and closed, so that the virtual storage unit in the prior art can store two bits of information, therefore, the storage density is high, and the unit storage cost is reduced.
Drawings
FIG. 1a is a schematic diagram of a prior art electron capture memory cell;
3 FIG. 31 3 b 3 is 3 a 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 31 3 a 3; 3
FIG. 1c is a cross-sectional view taken along line B-B' of FIG. 1 a;
FIG. 1d is a cross-sectional view taken along line C-C' of FIG. 1 b;
FIG. 2a is a schematic structural diagram of an electron capture memory cell according to a first embodiment of the present invention;
3 FIG. 32 3 b 3 is 3 a 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 32 3 a 3; 3
FIG. 2c is a cross-sectional view taken along line B-B' of FIG. 2 a;
FIG. 2d is a cross-sectional view taken along line C-C' of FIG. 2 b;
FIG. 3 is a schematic structural diagram of an electron trapping memory cell according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of an electron trapping open memory cell structure according to the present invention; and
FIG. 5 is a schematic diagram of a memory cell structure with electron trapping continuity according to the present invention.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.
FIG. 2a is a schematic structural diagram of an electron capture memory cell according to a first embodiment of the present invention; 3 FIG. 32 3 b 3 is 3 a 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 32 3 a 3; 3 FIG. 2c is a cross-sectional view taken along line B-B' of FIG. 2 a; fig. 2d is a cross-sectional view taken along line C-C 'of fig. 2b, wherein fig. 2d is an overall cross-sectional view of the memory cell taken along line C-C'.
As shown in fig. 2 a-2 d, the present invention provides an electron trapping memory cell comprising a control gate 21, a memory cell 23, an insulating dielectric 22 between the control gate 21 and the memory cell 23, a tunnel insulating dielectric 24, a channel 26, and an insulating layer 25 between two adjacent channels, and further comprising a channel control gate 27, wherein the channel control gate 27 is located in the insulating layer 25 and is a good electrical conductor. Wherein,the memory cell 23 is non-conductive and the channel control gate 27 may be a metal such as Cu, W, Al, Ta, or TiNx，WNx，CoSix,NiSix,TiSixAnd (c) a compound such as a quaternary ammonium compound. Preferably, the electron capture memory cell may be a SONOS memory cell.
As can be seen from fig. 2b, 2c and 2d, the present invention has one channel 26 in the physical sense, but has two channels 261 and 262 in the storage sense, and a virtual memory cell in the prior art is divided into two virtual memory cells, that is, one physical memory cell has four virtual memory cells. The channel control gate 27 is used to control the opening and closing of the first storage channel 261 and the second storage channel 262 on both sides of the channel 26.
The channel 26 is a physical channel, and the channel 26 can be controlled to open and close near the left and right sides of the channel control gate 27 by applying a control voltage to the channel control gate 27, so that the channel 26 in a physical sense is divided into two channels in a memory sense, as shown in fig. 2d, which are a first memory channel 261 and a second memory channel 262, respectively. Thus, a virtual memory cell (shown as 131 or 132 in fig. 1 c) in the prior art is divided into two virtual memory cells (shown as 231 or 232 in fig. 2 a), as shown in fig. 2c, the two virtual memory cells 231 are a first memory cell 2311 and a second memory cell 2312, respectively, and the two virtual memory cells 232 are a third memory cell 2321 and a fourth memory cell 2322, respectively. Thus, as can be seen from FIG. 2, a physical memory location 23 has four virtual memory locations in the sense of storage, each virtual memory location storing one bit of information, and the physical memory location 23 storing four bits of information.
Specifically, each physical channel 26 has a channel control gate 27 on each side. If a high voltage is applied to the channel control gate on one side and a low voltage is applied to the channel control gate on the other side, the channel 26 in one physical sense is divided into two channels in the sense of storage, a first storage channel 261 and a second storage channel 262, respectively. One memory channel corresponds to two dummy memory cells, for example, the first memory channel 261 corresponds to the first memory cell 2311 and the third memory cell 2321, and the second memory channel 262 corresponds to the second memory cell 2312 and the fourth memory cell 2322.
If the first memory channel 261 and its corresponding two dummy memory cells (the first memory cell 2311 and the third memory cell 2321) are to be operated (written, read, erased), a high voltage is applied to the channel control gate adjacent to the first memory channel 261 and a low voltage is applied to the channel control gate adjacent to the second memory channel 262. If the second memory channel 262 and its corresponding two dummy memory cells (the second memory cell 2312 and the fourth memory cell 2322) are to be operated (written, read, erased), a high voltage is applied to the channel control gate adjacent to the second memory channel 262 and a low voltage is applied to the channel control gate adjacent to the first memory channel 261. That is, the operation of the adjacent memory channels and the corresponding memory cells is controlled by applying a certain regular voltage to the different channel control gates.
Wherein, the number of the channel control gates 27 in each insulating layer 25 is 1, and each channel control gate 27 is used for controlling the opening and closing of the second storage channel 262 of the channel on one side adjacent to the channel on the other side and controlling the opening and closing of the first storage channel 261 of the channel on the other side adjacent to the channel on the other side.
After the channel control gate 27 is added, both sides of a channel in a physical sense, i.e., the first storage channel and the second storage channel, can be controlled to be opened and closed, respectively, by applying a control voltage to the channel control gate, so that one channel is divided into two in a storage sense, whereby a dummy memory cell defined in the prior art can store two bits of information. Therefore, the memory density becomes high, and the unit memory cost is reduced.
FIG. 3 is a schematic structural diagram of an electron trapping memory cell according to a second embodiment of the present invention. As shown in fig. 3, the number of the channel control gates 27 in each insulating layer 25 is 2, one of the channel control gates is used for controlling the opening and closing of the second storage channel 262 of the channel on the adjacent side, and the other channel control gate is used for controlling the opening and closing of the first storage channel 261 of the channel on the adjacent other side. In this embodiment, the other structural parts and the principle are the same as those of the first embodiment except that there are two channel control gates.
Specifically, each physical channel 26 has two channel control gates 27 on either side. If a high voltage is applied to the nearest channel control gate on one side and a low voltage is applied to the nearest channel control gate on the other side, a physical channel 26 is divided into two channels in the memory sense, a first memory channel 261 and a second memory channel 262, respectively. One memory channel corresponds to two dummy memory cells, for example, the first memory channel 261 corresponds to the first memory cell 2311 and the third memory cell 2321, and the second memory channel 262 corresponds to the second memory cell 2312 and the fourth memory cell 2322.
If the first memory channel 261 and its corresponding two dummy memory cells (the first memory cell 2311 and the third memory cell 2321) are to be written, read, and erased, a high voltage is applied to the channel control gate nearest to the first memory channel 261 and a low voltage is applied to the channel control gate nearest to the second memory channel 262. If the second memory channel 262 and its corresponding two dummy memory cells (the second memory cell 2312 and the fourth memory cell 2322) are to be written, read, and erased, a high voltage is applied to the channel control gate nearest to the second memory channel 262 and a low voltage is applied to the channel control gate nearest to the first memory channel 261. That is, the operation of the adjacent memory channels and the corresponding memory cells is controlled by applying a certain regular voltage to the different channel control gates.
After the two channel control gates 27 are added, the two sides of the channel in the physical sense, i.e. the first storage channel and the second storage channel, can be controlled to be opened and closed respectively by applying a control voltage to the channel control gates, so that one channel is divided into two in the storage sense, and thus a dummy memory cell defined in the prior art can store two bits of information. Therefore, the memory density becomes high, and the unit memory cost is reduced.
FIG. 4 is a schematic view of a broken-away configuration of the memory cell of the electron capture unit of the present invention; FIG. 5 is a schematic view of a sequential structure of the memory cells of the electron capture unit of the present invention. As shown in fig. 4, the storage unit 23 of the electron capture storage unit may be disconnected. As shown in fig. 5, the storage unit 23 of the electron capture storage unit may be continuous. The memory cells of the electron capture memory cells of the first and second embodiments of the invention may be continuous or discontinuous.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. An electron trapping memory cell comprising a channel (26) and an insulating layer (25) between two adjacent channels, comprising:
a channel control gate (27) which is provided in the insulating layer (25) and is a good electrical conductor;
wherein the channel control gate (27) is used for controlling the opening and closing of a first storage channel (261) and a second storage channel (262) which are positioned at two sides of the channel (26).
2. An electron-trapping memory cell according to claim 1, characterized in that the number of channel control gates (27) in each insulating layer (25) is 1.
3. The electron capture memory cell of claim 2,
each channel control gate (27) is used for controlling the opening and closing of the second storage channel (262) of the channel on the adjacent side and controlling the opening and closing of the first storage channel (261) of the channel on the adjacent other side.
4. An electron-trapping memory cell according to claim 1, characterized in that the number of channel control gates (27) in each insulating layer (25) is 2.
5. The electron capture memory cell of claim 4,
one of the channel control gates is used for controlling the opening and closing of a second storage channel (262) of the channel on the adjacent side, and the other channel control gate is used for controlling the opening and closing of a first storage channel (261) of the channel on the adjacent other side.
6. An electron-trapping memory cell according to any of claims 1 to 5, characterized in that the channel control gate (27) is a Cu, W, Al, Ta metal, or TiNx，WNx，CoSix,NiSix,TiSixA compound is provided.
7. An electron capture storage unit according to any of claims 1-5, characterized in that the storage unit (23) of the electron capture storage unit is disconnected.
8. An electron capture storage unit according to any of claims 1-5, characterized in that the storage units (23) of the electron capture storage unit are continuous.
9. The electron capture memory cell of any of claims 1-5, wherein the electron capture memory cell is a SONOS memory cell.
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| CN201310164838.XA CN104143552B (en) | 2013-05-07 | 2013-05-07 | A kind of electronics trapping memory cells |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1945836A (en) * | 2005-05-20 | 2007-04-11 | 硅存储技术公司 | Bidirectional split gate nand flash memory structure/array, programming, erasing reading and manufacturing |
| CN101207153A (en) * | 2006-12-20 | 2008-06-25 | 三星电子株式会社 | Non-volatile memory device and method of operating the same |
| CN101740638A (en) * | 2008-11-27 | 2010-06-16 | 上海华虹Nec电子有限公司 | Floating gate flash memory device adopting T-shaped gate structure and manufacturing technology thereof |
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| US7075146B2 (en) * | 2004-02-24 | 2006-07-11 | Micron Technology, Inc. | 4F2 EEPROM NROM memory arrays with vertical devices |
| US20060197140A1 (en) * | 2005-03-04 | 2006-09-07 | Freescale Semiconductor, Inc. | Vertical transistor NVM with body contact structure and method |
| US7829938B2 (en) * | 2005-07-14 | 2010-11-09 | Micron Technology, Inc. | High density NAND non-volatile memory device |
| KR101320519B1 (en) * | 2006-07-27 | 2013-10-23 | 삼성전자주식회사 | Non-volatile memory devices having pass transistors and method of operating the same |
| KR20080010900A (en) * | 2006-07-28 | 2008-01-31 | 삼성전자주식회사 | Nonvolatile Memory Device, Operation Method and Manufacturing Method Thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945836A (en) * | 2005-05-20 | 2007-04-11 | 硅存储技术公司 | Bidirectional split gate nand flash memory structure/array, programming, erasing reading and manufacturing |
| CN101207153A (en) * | 2006-12-20 | 2008-06-25 | 三星电子株式会社 | Non-volatile memory device and method of operating the same |
| CN101740638A (en) * | 2008-11-27 | 2010-06-16 | 上海华虹Nec电子有限公司 | Floating gate flash memory device adopting T-shaped gate structure and manufacturing technology thereof |
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