CN104123959B - The generic permutations circuit structure that replacement rule configuration is succinct - Google Patents

Abstract

The invention discloses a general replacement circuit structure with simple configuration of replacement rules, including a control module, a replacement rule register module, a source register module, an n-to-1 multiplexer, a result register module, and three write enable controls of the control module The signal end is respectively connected to the write enable control signal receiving end of the source register module, the result register module and the replacement rule register module, and the shift mode control signal output end of the control module is connected to the channel selection input end of the replacement rule register module; The n data output ports are connected to the n input channel ports of the n-to-1 multiplexer, and the output channel port of the n-to-1 multiplexer is connected to the data input port of the result register module; the replacement information output port of the replacement rule register module The channel selection input terminal of the n-to-1 multiplexer and the circular shift data input terminal of the replacement rule register module are respectively connected.

Description

General permutation circuit structure with simple configuration of permutation rules

technical field

The invention relates to the technical field of cryptographic chip integrated circuit design, in particular to a general replacement circuit structure with simple configuration of replacement rules.

Background technique

Bit Permutation (position replacement) and sub-block permutation (sub-block replacement) have an important position in the application of cryptographic algorithms. Bit-level position replacement is used in cryptographic algorithms such as DES, Present, and Sperent, for example. Bit permutation only changes the position of the bits in the data without changing the value of those bits. Assuming that a certain position replacement function converts n-bit data S into n-bit data D, then D[i]=S[π(i)], that is, the value of the i-th bit of data D is equal to the π-th of data S (i) The value of the bit, where 0≤i≤n-1, π represents a permutation rule function whose value range is an integer of [0, n-1], D[i] represents the value of the i-th bit of the data D , S[π(i)] represents the value of the π(i)th bit of the data S. Here, the data S is called the source data, and the data D is the result data. As shown in FIG. 1 , a schematic diagram of 4-bit permutation under a fixed permutation rule. Assuming that the data S is composed of 4-bit binary data, and the bits from left to right are recorded as S ₃ , S ₂ , S ₁ , S ₀ in turn, then the data S can be expressed as S={S ₃ S ₂ S ₁ S ₀ }, where the value of S _i is equal to 0 or 1. Similarly, the data D can be expressed as D={D ₃ D ₂ D ₁ D ₀ }. The replacement rule function in the position replacement shown in Figure 1 is: π(3)=1, π(2)=3, π(1)=0, π(0)=2, that is, the third bit of the data D The value of the first bit of data S comes from the first bit of data S, the value of the second bit of data D comes from the third bit of data S, the value of the first bit of data D comes from the 0th bit of data S, and the 0th bit of data D The value of the bit comes from bit 2 of the given data S. Under this replacement rule, if the value of data S is S={1110}, then the value of data D is D={1101}; if the value of data S is S={0101}, then the value of data D is is D={0011}.

Considering the continuous m bits in the above data as a whole, the whole forms a sub-block, and the size of the sub-block is m bits. Sub-block replacement is similar to position replacement, only the position of the sub-block is changed, and the internal data value of the sub-block is not changed. In the generalized Feistel-type cryptographic algorithm, the packet data is usually divided into multiple sub-blocks, and sub-block permutation is used for diffusion. In the existing cryptographic algorithms, the replacement rule of sub-block cyclical movement is usually adopted. At the same time, the realization of sub-block permutation support for arbitrary permutation rules is conducive to the realization of more secure cryptographic algorithms. The replacement of fixed rules can be implemented by means of hardware wiring. Although this method has the advantage of low implementation cost, it lacks flexibility. Each design can only support a fixed rule of replacement, and cannot support the replacement of arbitrary rules. However, the bit replacement rules in different cryptographic algorithms are not the same. In addition, in a cryptographic algorithm chip that supports user-defined position replacement or sub-block replacement rules, there is a need for a replacement circuit that supports arbitrary replacement rules, has simple configuration of replacement rule information, and is low in implementation cost. Therefore, there is a design requirement to support arbitrary permutation rules.

There are usually two ways to realize arbitrary regular position replacement or sub-block replacement, software and hardware.

The idea of using software to realize position replacement is usually to take out a bit of data from the source data according to the replacement rules, then move to the corresponding target position, and then merge the value into the result data, that is, to repeatedly fetch and mask (press Bitwise and), move, merge (bitwise or) four types of operations. Its time overhead is relatively large. When performing arbitrary position replacement for n-bit data, if a processor with a barrel shift register is used, generally 4n cycles are required. It will take even longer if the processor does not have a barrel shifter. In order to efficiently support position replacement in general-purpose processors, Ruly.B.LEE et al. proposed several position replacement instructions such as GRP, BFLY, and OMFLIP. Although these designs can flexibly support position replacement, their hardware overhead is large. According to public data, at least 19,000 equivalent gates are required in an ASIC design. In addition, programming is complicated when performing arbitrary position replacement by software. For sub-block replacement, if the size of the sub-block is not an integer multiple of the size of a byte, it will be very troublesome to implement the sub-block replacement by software, and the execution efficiency is low.

The common idea of using hardware to realize position replacement (or sub-block replacement) is to establish a corresponding data transmission channel between the corresponding bits (or sub-blocks) of source data and result data according to the replacement rules, and transfer each bit (or sub-block) in the source data to ) is passed to the corresponding position of the result data. In order to support arbitrary position permutation (or sub-block permutation), it is generally realized by using a configurable switching network, such as a crossbar switch network, a Benes network, and the like. Generally, at the same scale, the hardware resource overhead of the Benes network is lower than that of the crossbar network. However, these switching networks require a large number of permutation switches and control bit registers. For example, when using a Benes network to realize an n-bit permutation circuit, it is necessary a 2-2 displacement switch, The bit is used for storing the register of the replacement switch control information, and the 2n bits are used for the register of storing the data before and after the replacement, and one of the replacement switches is composed of two two-to-one multiplexers. For the replacement of n=128 arbitrary positions, when the Benes network is used to implement, 1664 two-to-one multiplexers and 1088-bit registers are required, of which 832-bit registers are used to store control bit information, and 256 bits are used to store data S and data d. In addition, under the Benes network, when a certain replacement rule is given, it is necessary to indirectly calculate the configuration information of each control bit from the replacement rule through a set of complex configuration algorithms. This makes the relationship between substitution rules and configuration information not intuitive.

Contents of the invention

The purpose of the present invention is to provide a general permutation circuit structure with simple configuration of permutation rules. Using a simple configuration algorithm, the permutation rule information of the permutation circuit can be configured simply and intuitively, effectively reducing the difficulty of using any permutation, and effectively reducing the permutation circuit complexity. chip area, thereby reducing chip production costs.

The technical scheme adopted in the present invention is:

A general replacement circuit structure with simple configuration of replacement rules is characterized in that it includes a control module, a replacement rule register module, a source register module, an n-to-1 multiplexer, and a result register module, and the control signal input terminal of the control module is used for Receive external input control information, the first write enable control signal end of the control module is connected to the write enable control signal receiving end of the source register module, and the second write enable control signal end of the control module is connected to the write enable of the result register module The control signal receiving end, the third write enable control signal end of the control module is connected to the write enable control signal receiving end of the replacement rule register module, the status signal output end of the control module is used to output the working state of the replacement circuit, and the shifting of the control module The output terminal of the bit pattern control signal is connected to the channel selection input terminal of the replacement rule register module; the data input terminal of the source register module is used to receive the source data input from the outside, and the n data output terminals of the source register module are correspondingly connected to an n-to-1 multiplexer n input channel ports of the device, and the output channel port of the n-choice 1 multiplexer is connected to the data input end of the result register module; the replacement rule input port of the replacement rule register module is used to receive the replacement rule information input from the outside, and the replacement rule register The replacement information output terminal of the module is respectively connected to the channel selection input terminal of the n-to-1 multiplexer and the cyclic shift data input terminal of the replacement rule register module, and the data output terminal of the result register module is used to output the data after replacement; the replacement circuit It also includes a clock signal input port, the clock signal input port is used to receive the clock signal provided by the outside, and provide the clock pulse signal for the whole replacement circuit;

Wherein, the control module is used to control the working state of the entire replacement circuit, receive and analyze the operation command word, and feed back the working state of the replacement circuit to output the replacement circuit; the control module includes a state machine and a counter;

The source register module is used to store data that requires position replacement or sub-block replacement, and is composed of n source data registers with a data bit width of m bits, and the numbers of the source data registers from left to right are S _n-1 ,S _n-2 ，……，S ₁ ，S ₀ ;

The n-choice 1 multiplexer is used to select the data in the source data register of the corresponding number from the source register module, and the data bit widths of its n input channel ports and 1 output channel port are all m bits; 1. The No. 0 input channel port of the multiplexer is connected to the data output end of the No. _S0 register in the source register module, and the No. 1 input channel port is connected to the data output end of the _No. S1 register in the source register module, No. 2, 3, 4, ... n-1 and so on, the output channel port of n selecting 1 multiplexer is connected to the data input terminal in the result register module;

The replacement rule register module is used to store replacement rules, including n replacement rule registers with a data bit width of k bits and a two-to-one multiplexer with a data bit width of k bits, wherein k is greater than or equal to The smallest positive integer; the numbers of the n replacement rule registers from left to right are: A ₀ , A ₁ ,...,A _n-2 , A _n-1 ; the n replacement rule registers are connected according to the following rules to form a shift Bit register chain: when 0<i≤n-1, the data input end of the No. A _i replacement rule register is connected to the data output end of the No. A _i-1 replacement rule register; the data input of the A No. ₀ replacement rule register The terminal is connected to the output end of the two-choice one multiplexer; the channel selection input end of the two-choice one multiplexer is connected to the shift mode control signal output end of the control module; the circular shift data input of the two-choice one multiplexer End is connected to the data output end of No. A _n-1 replacement rule register in the replacement rule register module, and now these replacement rule registers work in the circular shift mode; the replacement rule input end of the two-choice one multiplexer is used to receive the replacement Rule information, these replacement rule registers work in shift mode at this moment; the data output end of No. A _n-1 replacement rule register is simultaneously used as the replacement information output end;

The result register module is used to store the exchanged data, and is composed of n result registers with a data bit width of m bits; the numbers of the result registers from left to right are D _n-1 , D _n-2 ,... , D ₁ , D ₀ ; n result registers are connected according to the following rules to form a shift register chain: when 0<i≤n-1, the data input terminal of No. D _i result register is connected to No. D _i-1 result The data output end of the register; and the data input end of the No. _D0 result register is connected to the output channel port of the n-to-1 multiplexer, and the data output ends of the n result registers are spliced together as the data output port after replacement.

The invention controls and coordinates the work among the modules of the replacement rule register module, the source register module, the n-to-1 multiplexer and the result register module in the replacement circuit through the control module, and analyzes and processes the received external control information , to reasonably control the coordinated action between each module;

Advantages: 1. Through the replacement circuit structure of the present invention, a position replacement or sub-block replacement circuit supporting any replacement rule can be flexibly developed, the replacement circuit structure provided by the present invention, the relationship between the configuration information of the replacement rule and the replacement rule It is simple and clear, does not need to use complex configuration algorithms to determine configuration information, and can effectively reduce the difficulty of using any regular position replacement or sub-block replacement;

2. Utilizing the replacement circuit structure provided by the present invention has the advantage of low cost, especially when n is greater than 16, the DC synthesis result shows that the area of the replacement circuit provided by the present invention is smaller than that of the Benes network of the same size. The permutation circuit structure provided by the present invention, when performing n-bit permutation, only needs bit registers, an n-to-1 multiplexer and a simple control circuit; one of the n-to-one multiplexers can be constructed with n-1 two-to-one multiplexers; when n is larger, the The number of two-to-one multiplexers is much smaller than that in the Benes network For example, when n=128, only 127 two-to-one multiplexers are needed in the present invention, while the Benes network requires 1664 two-to-one multiplexers. The control module part mainly includes Bit register (where 2 bits are used to represent the state machine, Bits are used for counting) and some logic circuits, and its area overhead is relatively small; taking the n=128-bit position replacement circuit as an example, the DC synthesis results under TSMC’s 130nm process library show that the area of the control module is about 210 The equivalent gate is less than the area of 100 two-choice one-to-one multi-way selections. Therefore, it can be considered that when n does not exceed 128, the area of the control circuit does not exceed the area of 100 two-to-one multiplexers.

Description of drawings

Fig. 1 is a schematic diagram of a 4-bit position replacement under a replacement rule in the background technology of the present invention;

Fig. 2 is a schematic block diagram of circuit structure of the present invention;

Fig. 3 is the functional block diagram of the position replacement circuit structure supporting 128 bits of arbitrary replacement rules of the present invention;

Fig. 4 is a functional block diagram of a sub-block replacement circuit supporting arbitrary replacement rules of 16 sub-blocks according to the present invention.

detailed description

As shown in Figure 2, the present invention includes a control module, a replacement rule register module, a source register module, an n-to-1 multiplexer, and a result register module, and the control signal input terminal of the control module is used to receive externally input control information A, The first write enable control signal end en1 of the control module is connected to the write enable control signal receiving end of the source register module, and the second write enable control signal end en2 of the control module is connected to the write enable control signal receiving end of the result register module, The third write enable control signal end en3 of the control module is connected to the write enable control signal receiving end of the replacement rule register module, the state signal output end of the control module is used to output the working state B of the replacement circuit, and the shift mode control of the control module The signal output terminal mod is connected to the channel selection input terminal of the replacement rule register module; the data input terminal of the source register module is used to receive the source data S input from the outside, and the n data output terminals of the source register module are correspondingly connected to an n-to-1 multiplexer n input channel ports, the output channel port of n selecting 1 multiplexer is connected to the data input end of the result register module; the replacement rule input end of the replacement rule register module is used to receive the replacement rule information C of the external input, the replacement rule register The replacement information output terminal of the module is respectively connected to the channel selection input terminal of the n-to-1 multiplexer and the cyclic shift data input terminal of the replacement rule register module, and the data output terminal of the result register module is used to output the data D after replacement; this replacement The circuit also includes a clock signal input port, which is used to receive an externally provided clock signal and provide a clock pulse signal clk for the entire replacement circuit;

Wherein, the control module is used to control the working state of the entire replacement circuit, receive and analyze the operation command word, and feed back the working state of the replacement circuit; the control module includes a state machine and a counter; the state machine includes four kinds of work Status, respectively: load replacement rule status, load source data status, execution replacement status, and output replacement result status;

The output signal states of the control module under the four working states of the state machine are as follows:

"Load replacement rule state": the first write enable control signal (en1) output by the control module is invalid (indicated by '0'), and the second write enable control signal (en2) output by the control module is invalid (indicated by '0' Indicates), the third write enable control signal (en3) output by the control module is valid (indicated by '1'), the replacement rule register module shift mode control signal (mod) output by the control module is high level (even if the A The input data of No. ₀ replacement rule register comes from the replacement rule information input terminal input from the outside), and the output state information is "01".

In the "load source data state", the first write enable control signal (en1) output by the control module is valid (indicated by '1'), that is, the source data input from the outside can be received, and the second write enable control signal output by the control module The signal (en2) is invalid, the third write enable control signal (en3) output by the control module is invalid (indicated by '0'), the replacement rule register module shift mode control signal (mod) output by the control module is low level, The output status information is "10".

In the "execution replacement state", the first write enable control signal (en1) output by the control module is invalid, the second write enable control signal (en2) output by the control module is valid (indicated by '1'), and the output by the control module The third write enabling control signal (en3) is valid, and the replacement rule register module shift mode control signal (mod) of the control module output is low level (even if the input data of the No. A ₀ replacement rule register comes from the replacement rule register module. The circular shift data input terminal i0), the output state information is "11".

In the "output replacement result state", the first write enable control signal (en1) output by the control module is invalid, the second write enable control signal (en2) output by the control module is invalid, and the third write enable control signal (en2) output by the control module is invalid. The signal (en3) is invalid, the displacement rule register module shift mode control signal (mod) output by the control module is low level, and the output state information is "00".

When the output status information is "10" or "11", it means that the data in the result register module will be updated and the output result data is invalid. When the output status information is "00" or "01", it means that the output result data is valid.

The four working states of the state machine are switched according to the following rules:

The default state of the state machine is "output replacement result state", and the value of the counter is set to 0 in this state;

In the "output replacement result state", when the "load replacement rule information command" is received, the state machine transfers to the "load replacement rule state";

In the "load replacement rule state", the replacement rule register module can receive the replacement rule information input from the outside, and each time a replacement rule information is received, the value of the counter is increased by 1. When the value of the counter is equal to n, that is, when n After replacing the rule information, the state machine automatically transfers to the "output replacement result state";

In the "output replacement result state", when the "load source data command" is received, the state machine transfers to the "load source data state";

In the "loading source data state", when the externally input source data is written into the register of the source register module, the state machine automatically transfers to the "executing replacement state";

In the "execution replacement state", each replacement rule register in the replacement rule register module works in the circular shift mode, and at the same time, the result register in the result register module works in the left shift mode, that is, every time a clock cycle passes, the replacement rule The data in each replacement rule register in the register module moves one position to the right, and at the same time, the data in each result register in the result register module moves one position to the left, and the receiving n of the No. ₀ result register of D0 is multiplexed The output value of the selector; every time a clock cycle passes, the value of the counter is increased by 1; when the value of the counter is equal to n, the state machine automatically transfers to the "output replacement result state".

The source register module is used to store data that requires position replacement or sub-block replacement, and is composed of n source data registers with a data bit width of m bits, and the numbers of the source data registers from left to right are S _{n- 1} ,S _n-2 ,...,S ₁ ,S ₀ ; when the signal at the receiving end of the write enable control signal of the source register module is valid (en1=1), write the externally input data into the corresponding source data register. When the signal at the write enable end of the source register module is invalid (en1=0), the values in these source data registers remain unchanged.

The n-choice 1 multiplexer is used to select the data in the source data register of the corresponding number from the source register module, and the data bit widths of its n input channel ports and 1 output channel port are all m bits; 1. The No. 0 input channel port of the multiplexer is connected to the data output end of the No. _S0 register in the source register module, and the No. 1 input channel port is connected to the data output end of the _No. S1 register in the source register module, No. 2, 3, 4, ... n-1 and so on, the output channel port of n selecting 1 multiplexer is connected to the data input terminal in the result register module;

The replacement rule register module is used to store replacement rules, including n replacement rule registers with a data bit width of k bits and a two-to-one multiplexer with a data bit width of k bits, wherein k is greater than or equal to The smallest positive integer; the numbers of the n replacement rule registers from left to right are: A ₀ , A ₁ ,...,A _n-2 , A _n-1 ; the n replacement rule registers are connected according to the following rules to form a shift Bit register chain: when 0<i≤n-1, the data input end of the No. A _i replacement rule register is connected to the data output end of the No. A _i-1 replacement rule register; the data input of the A No. ₀ replacement rule register terminal is connected to the output terminal of the two-to-one multiplexer; the channel selection input of the two-to-one multiplexer is connected to the shift mode control signal output (mod) of the control module; when the mod signal is 0 (with low power flat representation), when the output of the two-select-one multiplexer comes from the data output terminal of the No. A _n-1 permutation rule register (i0 port), these permutation rule registers are working in the circular shift mode at this moment; when mod When the signal is 1 (indicated by a high level), the output of the two-choice multiplexer comes from the externally input permutation rule information (that is, the i1 port), and these permutation rule registers work in shift mode at this time; the first A _n- The data output terminal of No. ₁ replacement rule register is also used as the replacement information output terminal;

The result register module is used to store the exchanged data, and is composed of n result registers with a data bit width of m bits; the numbers of the result registers from left to right are D _n-1 , D _n-2 ,... , D ₁ , D ₀ ; n result registers are connected according to the following rules to form a shift register chain: when 0<i≤n-1, the data input terminal of No. D _i result register is connected to No. D _i-1 result The data output end of the register; and the data input end of the No. _D0 result register is connected to the output channel port of the n-to-1 multiplexer, and the data output ends of the n result registers are spliced together as the data output port after replacement. When the signal of the control signal receiving end of the write enable end of the result register module is valid, the data at the input end of each result register in this module is written into the corresponding result register under the trigger of the rising edge of the clock signal, so that the result data moves to the left One location; when the write enable control signal receiving end of the result register block is deasserted, the values in these result registers remain unchanged.

In practical applications, the replacement circuit is controlled and used by an external functional unit to complete the corresponding replacement function. The working process when the replacement circuit of the present invention completes the position replacement or sub-block replacement function is as follows:

Step 1: Configure replacement rules. When the state information output by the control module is "00" (representing that the external input can be received at this time), the external functional unit inputs the "loading replacement rule information command", and the state machine is transferred to the "loading replacement rule state", and in the subsequent n In a clock cycle, according to the position replacement (or sub-block replacement) rule, which bit (or sub-block) value of the i-th (or sub-block) representing the result data will be written in the replacement rule register module sequentially from the source data (or sub-block) block) data; assuming represented by π(i), 0≤i≤n-1, the order of writing is: π(n-1), π(n-2),……, π(1), π(0). When the writing of n pieces of replacement information is completed, the state machine automatically transfers to the "output replacement state". At this time, logically, the A _i -th replacement rule register in the replacement rule register module represents the i-th (or i-th sub-block) of the data after replacement, and the value in the A _i -th replacement rule register is equal to π (i), representing that the i-th bit (or i-th sub-block) of the result data comes from the π(i)-th bit (or π(i)-th sub-block) of the source data. In the above process, the duration of the "load replacement rule information command" issued by the external functional unit cannot exceed n clock cycles, otherwise a new round of replacement rule information loading process will be triggered.

Step 2: Load the source data. When the state information output by the control module is "00", the external input "load source data command", the state machine transfers to "load source data state", and the source data to be replaced is written into the source data register through the data input port . When the loading of the source data is completed, the state machine automatically transfers to the "execution replacement state", that is, it automatically transfers to the third step. The duration of the "load source data command" issued by the external functional unit cannot exceed n clock cycles, otherwise, a new source data load will be automatically triggered. That is, the externally input control information can become an invalid command "00" or "01" after the source data loading is completed.

Step 3: Execute the replacement process. This process requires a total of n cycles. The following operations are performed in each clock cycle:

(1) n selects 1 multiplexer according to the data provided by the replacement information output terminal of the replacement rule register module as a channel selection signal, selects the value in the corresponding number source data register from the source register module, and sends it to the result register The data input of the module.

(2) The data in each result register in the result register module moves to the left by one position, that is, the data in the result register D ₀ is passed to the result register D ₁ , the data in the result register D ₁ is passed to the result register D ₂ , and the result Register D ₃ , result register D ₄ ... and so on.

(3) The data of each replacement rule register in the replacement rule register module moves to the right by one position, that is, the data in the replacement rule register A ₀ is passed to the replacement rule register A ₁ , and the data in the replacement rule register A ₁ is passed to the replacement rule register A ₂ , replacement rule register A ₃ , replacement rule register A ₄ ...... and so on, but the value of the replacement rule register A _n-1 is passed to the replacement rule register A ₀ ; after n clock cycles, the replacement rule The value of each replacement rule register in the register module returns to the state after the first step is completed, and the output value of the result register module is the result after replacement.

Step 4: Read out the data result after replacement. After the third step above is completed, the status information output by the replacement circuit will change to "00", which means that the replacement result data is valid, and the external functional unit can read the replacement result from the data output port in the result register module data.

If the same replacement rule is used to replace multiple data, the first step of configuring the replacement rule only needs to be configured during the first replacement, and the step of configuring the replacement rule can be skipped for subsequent replacements, and the above-mentioned second step can be directly performed. , third, and fourth steps. When the data bit width m of each register in the above-mentioned source register module and the result register module and the data bit width m of each channel of the n-to-1 multiplexer are equal to 1, the replacement circuit structure of the present invention can be used to support any replacement rule bit-level position replacement circuit; when the above-mentioned m is an integer greater than 1, the sub-block replacement circuit supporting any replacement rule can be realized by using the replacement circuit structure of the present invention, wherein the size of the sub-block is m bits, source data and result data The data bit width of is n*m bits.

The working principle of the present invention is described in detail below in the mode of embodiment:

Example 1:

A general permutation circuit structure with simple permutation rule configuration provided by the present invention is used to realize a position permutation circuit supporting any permutation rule of 128 bits, and its circuit structure diagram is shown in FIG. 3 .

The replacement circuit includes five parts, which are source register module, 128-to-1 multiplexer, result register module, replacement rule register module and control module. In this example the value of n is 128, the value of m is 1, and the value of k is 7. Wherein, the source register module includes 128 source registers with a data bit width of 1 bit and a clock gate unit, the input of the clock gate unit is a clock signal (clk) and the first write enable control signal ( en1), the gated clock unit outputs a gated clock signal, and uses the gated clock signal as the clock signal of all source data registers in the source register module; each input channel port of the 128-choice 1 multiplexer , the data bit width of the output channel port is 1 bit; the described result register module contains 128 result registers and a gated clock unit whose data bit width is 1 bit, and the input of the gated clock unit is a clock signal (clk ) and the second write enable control signal (en2), the gating clock unit outputs a gating clock signal, and uses the gating clock signal as the clock signal of all result registers in the result register module, the result register module The data bit width of the data output port is 128 bits, and the data bit width of the data input port is 1 bit; the data bit width of the replacement rule input end of the described replacement rule register module is 7 bits, and the data bit width of the replacement information output end is 7 bits Bit; the replacement rule register module includes 128 data bit widths that are 7-bit replacement rule registers, an input/output channel data bit width that is 7-bit two-to-one multiplexer and a gate clock unit ; The input of the gated clock unit is a clock signal (clk) and the third write enable control signal (en3), the gated clock unit outputs a gated clock signal, and uses the gated clock signal as the replacement rule register module The clock signal of all the replacement rule registers in the replacement circuit; the control module is used to control and coordinate the work of each module in the replacement circuit, receive and analyze the control information input from the outside, and feed back the working state of the replacement circuit; the replacement circuit has four working states , which are the status of loading replacement rules, loading source data, executing replacement and outputting replacement results. The control module controls switching between various working states in combination with externally input control information; the data width of the control signal input end is 2 bits, which is used to receive externally input control commands, and the control commands include: load replacement rule information commands (use "10 " indicates), load the source data command (indicated by "11"); when the external input control information is "00" or "01", the control module regards it as an invalid command and does not process it; the status information output port The data width is 2 bits, which is used to feed back the working state of the replacement circuit; the control module includes a state machine with four states and a counter; the four states of the state machine correspond to the four working states of the replacement circuit respectively. In the description of the state machine described in this example, the value of n is 128. The output signal state of the control module and the switching rules between the four working states of the state machine are the same as the state machine in the above-mentioned specific embodiment. The description of is the same, just instantiate the value of n to 128, so I won't go into details here.

In a specific application, the permutation circuit is connected to a corresponding external functional unit according to specific requirements, and the permutation circuit is controlled and used by the external functional unit to complete the corresponding position permutation function.

The external functional unit inputs operation command words to the control module through the control signal input port; provides 128-bit data to be replaced through the input data port; provides corresponding replacement rule information through the replacement rule information input port; obtains the corresponding replacement result through the output data port ; Obtain the working state of the replacement circuit through the status information output port; the clock signal of the replacement circuit is the same as the clock signal of the external functional unit.

The permutation circuit described in Embodiment 1 completes the working process of the 128-bit position permutation as follows:

Step 1: Configure replacement rules. When the state information output by the replacement circuit is "00", the external functional unit sends a "load replacement rule information command", and the replacement circuit enters the "load replacement rule state". According to the position replacement rule, 128 pieces of 7-bit replacement rule information are sequentially written into the replacement rule register module through the replacement rule information input port. One bit of data, assuming represented by π(i), 0≤i≤127, each clock cycle external functional unit provides a replacement rule information, the order is: π(127), π(126),..., π(1), π(0). After the writing of 128 replacement rule information is completed, the replacement circuit automatically transfers to the "state of outputting replacement results". From a logical point of view, the No. A _i replacement rule register in the replacement rule register module represents the i-th bit of the data after replacement, and the value in the No. A _i replacement rule register is equal to π(i), which represents The i-th bit of the result data comes from the π(i)-th bit of the source data. In the above process, the duration of the "load replacement rule information command" issued by the external functional unit cannot exceed 128 clock cycles.

Step 2: Load the source data. When the status information output by the replacement circuit is "00", the external functional unit prepares the source data to be replaced, and issues a "load source data command", the state machine transfers to the "load source data state", and the source data to be replaced Data is written into the source data register through the data input port. When the source data is loaded, it will automatically go to the third step. The duration of the "load source data command" issued by the external functional unit cannot exceed 128 clock cycles.

Step 3: Execute the replacement process. During this process, the replacement circuit updates the data in the result register module according to the replacement rule information in the replacement rule register module. A total of 128 clock cycles are required. After this process is completed, the state machine automatically transfers to the "output permutation result state".

Step 4: Read out the data result after replacement. After the above third step is completed, the state information output by the replacement circuit becomes "00", and the data output by the result register module is the result data after replacement, and this value remains unchanged under the "output replacement result state". The external functional unit can read the replacement result data of this time.

If multiple data are replaced by the same replacement rule, the first step to configure the position replacement rule only needs to be configured during the first replacement, and the step of configuring the replacement rule can be skipped for subsequent replacements, and the above-mentioned first step can be directly performed. Two, three, and four steps.

In this embodiment, under the 130nm process library of TSMC, the DC synthesis result shows that its area is about 7756 equivalent gates, which can save nearly 30% of the area compared with the 128-bit Benes network (area is about 11275 equivalent gates). . The above data show that the universal replacement circuit structure involved in the present invention achieves the purpose of reducing costs and brings favorable economic benefits to later actual production.

Example 2:

A sub-block replacement circuit supporting arbitrary replacement rules for 16 sub-blocks (with a block size of 4 bits) is realized by using the general replacement circuit structure provided by the present invention with a simple configuration of replacement rules, and its circuit structure is shown in FIG. 4 .

The sub-block replacement circuit mainly includes five parts, namely, a source register module, a 16-to-1 multiplexer, a result register module, a replacement rule register module and a control module. The value of n is 16, the value of m is 4, and the value of k is 4 in this example. The source register module includes 16 source registers with a data bit width of 4 bits and a gated clock unit, the input of which is a clock signal (clk) and the first write enable control signal (en1) , the gated clock unit outputs a gated clock signal, and uses the gated clock signal as the clock signal of all source registers in the source register module, the data bit width of the data input port of the source register module is 64 bits, Divided into 16 sub-blocks and connected to the data input terminals of the corresponding source registers; the data bit width of each input and output channel port of the 16-choice multiplexer is 4 bits; the described result register module contains 16 A result register with a data bit width of 4 bits and a gated clock unit whose input is a clock signal (clk) and a second write enable control signal (en2), and which outputs a gated clock unit Clock signal, and this gated clock signal is used as the clock signal of all result registers in the result register module; The data bit width of the data input port of the result register module is 4 bits, and the data bit width of the data output port is 64 bits , which is spliced by the data output ends of 16 4-bit result registers; the replacement rule register module includes 16 replacement rule registers with a data bit width of 4 bits, and an input/output channel with a data bit width of 4 bits. Bit two-to-one multiplexer and a gating clock unit; the input of the gating clock unit is the clock signal (clk) and the third write enable control signal (en3), and the gating clock unit outputs a gating clock unit clock signal, and this gated clock signal is used as the clock signal of all replacement rule registers in the replacement rule register module; the data bit width of the replacement rule data input port of the replacement rule register module is 4 bits, and the output port of the replacement information The data bit width is 4 bits; in the description of the state machine described in this example, the value of n is 16, the state of the output signal of the control module and the switching rules between the four working states of the state machine It is the same as the description of the state machine in the above-mentioned specific implementation manner, only need to instantiate the value of n as 16, which will not be repeated here.

The permutation circuit described in Embodiment 2 completes the sub-block permutation process of any permutation rule with 16 sub-block sizes of 4 bits as follows:

Step 1: Configure replacement rules. When the state information output by the replacement circuit is "00", the external functional unit sends a "load replacement rule information command", and the replacement circuit is transferred to the "load replacement rule state", and the external functional unit is within the next 16 clock cycles. According to the sub-block replacement rules, 16 pieces of 4-bit replacement rule information are sequentially written into the replacement rule register module through the replacement rule information input port, and these replacement rule information indicates that the value of the ith sub-block of the result data after replacement will come from the source data Which sub-block’s data (assumed to be represented by π(i), 0≤i≤15), each clock cycle external functional unit provides a replacement rule information, the order is: π(15), π(14), ...., π(1), π(0). After the writing of the 16 replacement rule information is completed, the replacement circuit automatically transfers to the "output replacement result state". From a logical point of view, at this time, the No. A _i replacement rule register in the replacement rule register module represents the ith sub-block of the data after replacement, and the value in the A _i No. replacement rule register is equal to π(i), which represents Then the value of the ith sub-block of the result data comes from the value of the π(i)-th sub-block of the source data. In the above process, the duration of the "load replacement rule information command" issued by the external functional unit cannot exceed 16 clock cycles.

Step 2: Load the source data. When the status information output by the replacement circuit is "00", the external functional unit prepares the source data to be replaced, and issues a "load source data command", the state machine transfers to the "load source data state", and the source data to be replaced Data is written into the source data register through the data input port. When the source data is loaded, it will automatically go to the third step. The duration of the "load source data command" issued by the external functional unit cannot exceed 16 clock cycles.

Step 3: Execute the replacement process. During this process, the replacement circuit updates the data in the result register module according to the replacement rule information in the replacement rule register module. A total of 16 clock cycles are required. After this process is completed, the state machine automatically transfers to the "output permutation result state".

Step 4: Read out the data result after replacement. After the above third step is completed, the state information output by the replacement circuit becomes "00". At this time, the data output by the result register module is the result data after replacement, and this value remains unchanged in the "output replacement result state". The functional unit can read the replacement result data of this time.

If multiple data are replaced by the same replacement rule, the first step of configuring the sub-block replacement rule only needs to be configured at the first replacement, and the step of configuring the replacement rule can be skipped for subsequent replacements, and the above steps can be performed directly The second, third, and fourth steps.

This embodiment is under the 130nm process library of TSMC, and the result of DC synthesis shows that its area is about 1608 equivalent gates, which is equivalent to the sub-block replacement that realizes the same function with a 64-bit Benes network (with an area of about 5616 equivalent gates). In comparison, this embodiment can save nearly 70% of the area. The above data shows that the arbitrary replacement circuit structure involved in the present invention achieves the purpose of reducing costs and brings favorable economic benefits to later actual production.

It can be seen from the above embodiments that the present invention can support position replacement or sub-block replacement of any replacement rule.

Claims (1)

1. A general replacement circuit structure with simple configuration of replacement rules is characterized in that: it comprises a control module, a replacement rule register module, a source register module, n selects 1 multiplexer, a result register module, and a control signal input terminal of the control module It is used to receive external input control information. The first write enable control signal end of the control module is connected to the write enable control signal receiving end of the source register module, and the second write enable control signal end of the control module is connected to the write end of the result register module. Enable the control signal receiving end, the third write enabling control signal end of the control module is connected to the write enabling control signal receiving end of the replacement rule register module, the status signal output end of the control module is used to output the working state of the general replacement circuit, and control The shift mode control signal output terminal of the module is connected to the channel selection input terminal of the replacement rule register module; the data input terminal of the source register module is used to receive the source data input from the outside, and the n data output terminals of the source register module are correspondingly connected to select 1 of n The n input channel ports of the multiplexer, the output channel port of n selecting 1 multiplexer is connected to the data input end of the result register module; the replacement rule input port of the replacement rule register module is used to receive the replacement rule information of the external input, The replacement information output end of the replacement rule register module is respectively connected to the channel selection input end of the n-choice 1 multiplexer and the cyclic shift data input end of the replacement rule register module, and the data output end of the result register module is used for outputting data after replacement; The general replacement circuit also includes a clock signal input port, the clock signal input port is used to receive an externally provided clock signal, and provide a clock pulse signal for the entire general replacement circuit; Wherein, the control module is used to control the working state of the entire general replacement circuit, receive and analyze the operation command word, and feed back the working state of the general replacement circuit; the control module includes a state machine and a counter; The source register module is used to store data that requires position replacement or sub-block replacement, and is composed of n source data registers with a data bit width of m bits, and the numbers of the source data registers from left to right are S _n-1 ,S _n-2 ，……，S ₁ ，S ₀ ; The n-choice 1 multiplexer is used to select the data in the source data register of the corresponding number from the source register module, and the data bit widths of its n input channel ports and 1 output channel port are all m bits; 1. The No. 0 input channel port of the multiplexer is connected to the data output end of the No. _S0 register in the source register module, and the No. 1 input channel port is connected to the data output end of the _No. S1 register in the source register module, No. 2, 3, 4, ... n-1 and so on, the output channel port of n selecting 1 multiplexer is connected to the data input terminal in the result register module; The replacement rule register module is used to store replacement rules, including n replacement rule registers with a data bit width of k bits and a two-to-one multiplexer with a data bit width of k bits, wherein k is greater than or equal to The smallest positive integer; the numbers of the n replacement rule registers from left to right are: A ₀ , A ₁ ,...,A _n-2 , A _n-1 ; the n replacement rule registers are connected according to the following rules to form a shift Bit register chain: when 0<i≤n-1, the data input end of the No. A _i replacement rule register is connected to the data output end of the No. A _i-1 replacement rule register; the data input of the A No. ₀ replacement rule register The terminal is connected to the output terminal of the two-to-one multiplexer; the channel selection input terminal of the two-to-one multiplexer is connected to the shift mode control signal output end of the control module; the circular shift data input of the two-to-one multiplexer The terminal is connected to the data output end of No. A _n-1 replacement rule register in the replacement rule register module; the replacement rule input end of the two-choice multiplexer is used to receive the replacement rule information; the No. A _n-1 replacement rule register The data output terminal is also used as the replacement information output terminal; The result register module is used to store the exchanged data, and is composed of n result registers with a data bit width of m bits; the numbers of the result registers from left to right are D _n-1 , D _n-2 ,... , D ₁ , D ₀ ; n result registers are connected according to the following rules to form a shift register chain: when 0<i≤n-1, the data input terminal of No. D _i result register is connected to No. D _i-1 result The data output end of the register; and the data input end of the No. _D0 result register is connected to the output channel port of the n-to-1 multiplexer, and the data output ends of the n result registers are spliced together as the data output port after replacement.