CN104103720A - Method for preparing nitride semiconductor - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical class [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 229910002601 GaN Inorganic materials 0.000 claims description 26
- 238000005240 physical vapour deposition Methods 0.000 claims description 18
- 238000002360 preparation method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052788 barium Inorganic materials 0.000 claims description 2
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052791 calcium Inorganic materials 0.000 claims description 2
- 239000011575 calcium Substances 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 239000011701 zinc Substances 0.000 claims description 2
- 239000000428 dust Substances 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 17
- 239000010409 thin film Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
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Abstract
本发明提出了一种氮化物半导体的制备方法，通过在PVD法AlN薄膜层与CVD法氮化镓系列层之间沉积一CVD法AlxInyGa1-x-yN材料层，利用该材料层可减小AlN薄膜层与氮化镓系列层之间的应力作用，改善发光二极管的整体质量，从而最终改善发光效率。
The present invention proposes a method for preparing a nitride semiconductor, by depositing a CVD method Al x In y Ga 1-xy N material layer between the PVD method AlN thin film layer and the CVD method gallium nitride series layer, and using the material layer The stress effect between the AlN thin film layer and the gallium nitride series layer can be reduced, and the overall quality of the light emitting diode can be improved, thereby finally improving the luminous efficiency.
Description
技术领域 technical field
本发明涉及发光二极管制备技术领域，特别涉及一种氮化物半导体的制备方法。 The invention relates to the technical field of light-emitting diode preparation, in particular to a method for preparing a nitride semiconductor.
背景技术 Background technique
物理气相沉积(Physical Vapor Deposition，PVD)技术是指在真空条件下，采用物理方法，将材料源——固体或液体表面气化成气态原子、分子或部分电离成离子，并通过低压气体（或等离子体）过程，在基体表面沉积具有某种特殊功能的薄膜的技术。物理气相沉积方法主要包括：真空蒸镀、溅射镀膜、电弧等离子体镀、离子镀膜，及分子束外延等；其不仅可以沉积金属膜、合金膜、还可以沉积化合物、陶瓷、半导体、聚合物膜等；该技术工艺过程简单，对环境污染小，原材料消耗少，且成膜均匀致密，与基板的结合力强。 Physical vapor deposition (Physical Vapor Deposition, PVD) technology refers to the use of physical methods under vacuum conditions to vaporize the material source—solid or liquid surface into gaseous atoms, molecules or parts of ionization into ions, and through low-pressure gas (or plasma) Body) process, the technology of depositing a thin film with a certain special function on the surface of the substrate. Physical vapor deposition methods mainly include: vacuum evaporation, sputtering coating, arc plasma plating, ion coating, and molecular beam epitaxy, etc.; it can not only deposit metal films, alloy films, but also deposit compounds, ceramics, semiconductors, polymers, etc. Membranes, etc.; this technology has a simple process, less environmental pollution, less raw material consumption, uniform and dense film formation, and strong bonding with the substrate.
鉴于PVD法的以上优势，在发光二极管(Light-emitting diode，LED) 研究快速发展的情况下，该法也被广泛应用与发光二极管的制备中。美国专利文献US2013/ 0285065揭示了利用PVD法形成的AlN薄膜层表面平整，其粗糙度小于1nm；晶格质量较优，其002半峰宽小于200；后在此薄膜层上利用化学气相沉积法（CVD法）再沉积n型层、发光层和p型层等氮化物层。而在实际制备中，后续利用化学气相沉积法沉积的晶体层与前述PVD法的生长腔室环境差异加大，且材料组成为GaN系，其与AlN薄膜层的晶格失配较大，因而造成PVD法AlN薄膜层与CVD法氮化物层之间存在较大应力，从而易导致发光二极管质量变差，发光效率降低。 In view of the above advantages of the PVD method, this method is also widely used in the preparation of light-emitting diodes under the condition of rapid development of light-emitting diode (LED) research. The US patent document US2013/0285065 discloses that the surface of the AlN film layer formed by the PVD method is smooth, and its roughness is less than 1nm; the lattice quality is better, and its 002 half-peak width is less than 200; and then on this film layer, the chemical vapor deposition method is used. (CVD method) Re-deposit nitride layers such as n-type layer, light-emitting layer and p-type layer. However, in actual preparation, the difference between the crystal layer deposited by the chemical vapor deposition method and the growth chamber environment of the aforementioned PVD method is greater, and the material composition is GaN system, which has a large lattice mismatch with the AlN thin film layer, so As a result, there is a large stress between the PVD AlN thin film layer and the CVD nitride layer, which easily leads to deterioration of the quality of the light-emitting diode and a decrease in luminous efficiency.
发明内容 Contents of the invention
针对上述问题，本发明提出了一种氮化物半导体的制备方法，通过在PVD法AlN薄膜层与CVD法氮化物层之间沉积一CVD法AlxInyGa1-x-yN材料层，利用该材料层可减小AlN薄膜层与氮化物层之间的应力作用，改善发光二极管的整体质量，从而最终改善发光效率。 In view of the above problems, the present invention proposes a method for preparing a nitride semiconductor, by depositing a CVD method Al x In y Ga 1-xy N material layer between the PVD method AlN thin film layer and the CVD method nitride layer, utilizing the The material layer can reduce the stress effect between the AlN thin film layer and the nitride layer, improve the overall quality of the light emitting diode, and finally improve the luminous efficiency.
本发明解决上述问题的技术方案为：一种氮化物半导体的制备方法，包括以下步骤： The technical solution of the present invention to solve the above problems is: a method for preparing a nitride semiconductor, comprising the following steps:
步骤一：提供一衬底，利用物理气相沉积法（PVD法）在所述衬底上沉积一AlN层，形成第一缓冲层； Step 1: providing a substrate, and depositing an AlN layer on the substrate by physical vapor deposition (PVD method) to form a first buffer layer;
步骤二：在所述AlN层上利用化学气相沉积法（CVD）沉积一AlxInyGa1-x-yN（0<x≤1，0≤y≤1）层，形成第二缓冲层；所述第二缓冲层与所述第一缓冲层组合构成底层； Step 2: Depositing an Al x In y Ga 1-xy N (0<x≤1, 0≤y≤1) layer on the AlN layer by chemical vapor deposition (CVD) to form a second buffer layer; The second buffer layer is combined with the first buffer layer to form a bottom layer;
步骤三：在所述氮化物底层上利用CVD法沉积n型氮化镓层、发光层和p型氮化镓系层；该CVD法形成的AlxInyGa1-x-yN材料组成的第二缓冲层与所述AlN材料组成的第一缓冲层均为含铝材料层，故其材料系数相近，晶格失配较小；且因第二缓冲层的沉积方式与第三步骤沉积层的沉积方式相同，可优选金属有机化学气相沉积（MOCVD）法，因而可减小步骤一与步骤三之间的材料应力，从而改善底层的晶格层质量，改善整体外延结构质量。 Step 3: Deposit an n - type gallium nitride layer, a light-emitting layer and a p - type gallium nitride-based layer on the nitride bottom layer by CVD; The second buffer layer and the first buffer layer composed of the AlN material are all aluminum-containing material layers, so their material coefficients are similar and the lattice mismatch is small; and because the deposition method of the second buffer layer is different from that of the deposited layer in the third step The deposition method is the same, and the metal organic chemical vapor deposition (MOCVD) method can be preferred, so the material stress between steps 1 and 3 can be reduced, thereby improving the quality of the underlying lattice layer and improving the quality of the overall epitaxial structure.
优选的，所述形成的第一缓冲层的厚度范围为5埃～350埃。 Preferably, the thickness of the formed first buffer layer ranges from 5 angstroms to 350 angstroms.
优选的，所述形成的第二缓冲层的厚度范围为5埃～1500埃。 Preferably, the thickness of the formed second buffer layer ranges from 5 angstroms to 1500 angstroms.
优选的，所述形成的第二缓冲层的生长温度范围为400～1150℃。 Preferably, the growth temperature range of the formed second buffer layer is 400-1150°C.
优选的，所述步骤三形成的n型氮化镓层为n型掺杂氮化镓层或无掺杂氮化镓层与n型氮化镓层之组合层。 Preferably, the n-type GaN layer formed in the third step is an n-type doped GaN layer or a combination layer of an undoped GaN layer and an n-type GaN layer.
优选的，所述形成的底层为无掺杂或掺杂有n型或p型杂质。 Preferably, the formed bottom layer is undoped or doped with n-type or p-type impurities.
优选的，所述n型杂质为硅或锡的其中一种。 Preferably, the n-type impurity is one of silicon or tin.
优选的，所述p型杂质为锌、镁、钙、钡的其中一种。 Preferably, the p-type impurity is one of zinc, magnesium, calcium and barium.
优选的，所述n型或p型杂质的浓度范围为1017~1020/cm3。 Preferably, the concentration range of the n-type or p-type impurity is 10 17 -10 20 /cm 3 .
优选的，所述第一缓冲层在PVD腔室中沉积形成；所述第二缓冲层在MOCVD腔室中沉积形成。 Preferably, the first buffer layer is deposited and formed in a PVD chamber; the second buffer layer is deposited and formed in an MOCVD chamber.
本发明至少具有以下有益效果：本发明方法中，该MOCVD法形成的AlxInyGa1-x-yN材料组成的第二缓冲层与所述AlN材料组成的第一缓冲层晶格失配小，且其沉积腔室环境与所述第三步骤沉积层生长环境一致，因而可减小步骤一与步骤三之间的材料应力，改善整体外延结构质量。 The present invention has at least the following beneficial effects: In the method of the present invention, the lattice mismatch between the second buffer layer composed of AlxInyGa1 -xyN material formed by the MOCVD method and the first buffer layer composed of AlN material is small , and the deposition chamber environment is consistent with the growth environment of the deposition layer in the third step, so the material stress between step 1 and step 3 can be reduced, and the quality of the overall epitaxial structure can be improved.
附图说明 Description of drawings
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。 The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, and are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In addition, the drawing data are descriptive summaries and are not drawn to scale.
图1~2为本发明之实施例的发光二极管结构示意图。 1-2 are schematic diagrams of the structure of a light emitting diode according to an embodiment of the present invention.
图3为本发明之一种氮化物半导体的制备方法流程图。 Fig. 3 is a flowchart of a method for preparing a nitride semiconductor according to the present invention.
图中：1. 衬底；2. 底层；21. 第一缓冲层；22.第二缓冲层；3. n型氮化镓层；31.无掺杂氮化镓层；32. n型掺杂氮化镓层；4.发光层；5. p型氮化镓系层。 In the figure: 1. substrate; 2. bottom layer; 21. first buffer layer; 22. second buffer layer; 3. n-type gallium nitride layer; 31. undoped gallium nitride layer; 32. n-type doped heterogallium nitride layer; 4. light emitting layer; 5. p-type gallium nitride series layer.
具体实施方式 Detailed ways
下面结合附图和实施例对本发明的具体实施方式进行详细说明。 The specific implementation manner of the present invention will be described in detail below with reference to the drawings and embodiments.
实施例1Example 1
请参看附图1~3，一种氮化物半导体的制备方法，包括以下步骤： Please refer to accompanying drawings 1-3, a method for preparing a nitride semiconductor, comprising the following steps:
步骤一：提供衬底1，衬底可为蓝宝石衬底或硅衬底，也可以是图形化衬底，将其置于物理气相沉积腔室中，利用物理气相沉积法（PVD法）在衬底1上沉积厚度为5埃～350埃的AlN层，形成第一缓冲层21； Step 1: Provide a substrate 1, which can be a sapphire substrate or a silicon substrate, or a patterned substrate, which is placed in a physical vapor deposition chamber, and is deposited on the substrate by physical vapor deposition (PVD) Depositing an AlN layer with a thickness of 5 angstroms to 350 angstroms on the bottom 1 to form a first buffer layer 21;
步骤二：将沉积有第一缓冲层21的衬底置于化学气相沉积（CVD）腔室中，利用CVD法沉积一厚度范围为5埃～1500埃AlxInyGa1-x-yN（0<x≤1，0≤y≤1）层，调节Al组分，使其晶格常数介于AlN层与氮化镓系列层之间，形成第二缓冲层22，生长温度范围为400～1150℃；第二缓冲层22与所述第一缓冲层21组合形成底层2； Step 2: Place the substrate deposited with the first buffer layer 21 in a chemical vapor deposition (CVD) chamber, and deposit an Al x In y Ga 1-xy N (0 <x≤1, 0≤y≤1) layer, adjust the Al composition so that the lattice constant is between the AlN layer and the gallium nitride series layer to form the second buffer layer 22, and the growth temperature range is 400-1150 °C; the second buffer layer 22 is combined with the first buffer layer 21 to form the bottom layer 2;
步骤三：继续在步骤二的CVD腔室中，调节温度、气流等生长参数，在底层2上利用CVD法沉积n型氮化镓层3、发光层4和p型氮化镓系层5。其中，n型氮化镓层3依次为无掺杂氮化镓层31和n型掺杂氮化镓层32组合层；此外n型氮化镓层3亦可直接为n型掺杂氮化镓层32（如图2所示）。 Step 3: Continue to adjust growth parameters such as temperature and gas flow in the CVD chamber of step 2, and deposit n-type gallium nitride layer 3 , light-emitting layer 4 and p-type gallium nitride-based layer 5 on bottom layer 2 by CVD. Among them, the n-type gallium nitride layer 3 is a combination layer of an undoped gallium nitride layer 31 and an n-type doped gallium nitride layer 32 in sequence; in addition, the n-type gallium nitride layer 3 can also be directly an n-type doped gallium nitride layer. Gallium layer 32 (shown in FIG. 2 ).
在本实施例中，利用PVD法沉积第一缓冲层后，如直接进行步骤三在CVD腔室中沉积n型氮化镓层3、发光层4和p型氮化物层5时，由于PVD腔室沉积环境与CVD腔室沉积环境差异较大，其沉积的薄膜晶体状态有较大差异，且AlN层材料与后续氮化物层材料晶格系数有较大差异，从而易造成底层2与后续氮化镓系列层3之间存在一定应力，进而影响发光二极管的整体质量和性能。而当插入AlxInyGa1-x-yN材料的第二缓冲层22时，因AlxInyGa1-x-yN材料与AlN及氮化镓系层之间材料晶格系数差异缩小，晶格匹配度增加，且该层与后续层均在CVD腔室中沉积，沉积方式差异较小，因此可减小n型氮化镓层3及后续层与AlN层之间的应力，改善整体晶体质量。 In this embodiment, after depositing the first buffer layer by the PVD method, if the step 3 is directly performed to deposit the n-type gallium nitride layer 3, the light-emitting layer 4 and the p-type nitride layer 5 in the CVD chamber, due to the PVD chamber The deposition environment of the chamber and the deposition environment of the CVD chamber are quite different, and the crystalline state of the deposited thin film is quite different, and the lattice coefficient of the material of the AlN layer and the material of the subsequent nitride layer is quite different, which is easy to cause the bottom layer 2 and the subsequent nitrogen There is a certain stress between the GaN series layers 3, which further affects the overall quality and performance of the light emitting diode. However, when the second buffer layer 22 of AlxInyGa1 -xyN material is inserted, the difference in lattice coefficient between the AlxInyGa1 -xyN material and the AlN and gallium nitride - based layers is reduced, and the crystal The degree of lattice matching is increased, and this layer and subsequent layers are all deposited in a CVD chamber, and the difference in deposition methods is small, so the stress between the n-type gallium nitride layer 3 and subsequent layers and the AlN layer can be reduced, and the overall crystal structure can be improved. quality.
实施例2Example 2
本实施例与实施例1的区别在于：底层2中包含的第一缓冲层和第二缓冲层可掺杂有n型杂质，优选硅杂质，掺杂浓度为1017~1020/cm3左右。 The difference between this embodiment and Embodiment 1 is that the first buffer layer and the second buffer layer included in the bottom layer 2 can be doped with n-type impurities, preferably silicon impurities, with a doping concentration of about 10 17 ~10 20 /cm 3 .
实施例3Example 3
本实施例与实施例1的区别在于：底层2中包含的第一缓冲层和第二缓冲层可掺杂有p型杂质，优选镁杂质，掺杂浓度为1017~1020/cm3左右。 The difference between this embodiment and Embodiment 1 is that the first buffer layer and the second buffer layer contained in the bottom layer 2 can be doped with p-type impurities, preferably magnesium impurities, and the doping concentration is about 10 17 ~10 20 /cm 3 .
应当理解的是，上述具体实施方案为本发明的优选实施例，本发明的范围不限于该实施例，凡依本发明所做的任何变更，皆属本发明的保护范围之内。 It should be understood that the above specific implementation is a preferred embodiment of the present invention, the scope of the present invention is not limited to this embodiment, and any changes made according to the present invention are within the protection scope of the present invention.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016011810A1 (en) * | 2014-07-24 | 2016-01-28 | 厦门市三安光电科技有限公司 | Method for preparing nitride semiconductor |
| WO2016165558A1 (en) * | 2015-04-15 | 2016-10-20 | 厦门市三安光电科技有限公司 | Nitride light emitting diode structure and preparation method thereof |
| WO2016173359A1 (en) * | 2015-04-29 | 2016-11-03 | 厦门市三安光电科技有限公司 | Light-emitting diode structure and preparation method therefor |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1846310A (en) * | 2003-09-24 | 2006-10-11 | 三垦电气株式会社 | Nitride semiconductor device and manufacturing method thereof |
| CN102832241A (en) * | 2012-09-14 | 2012-12-19 | 电子科技大学 | Gallium-nitride-base heterostructure field effect transistor with transverse p-n junction composite buffering layer structure |
| US20130285065A1 (en) * | 2012-04-26 | 2013-10-31 | Mingwei Zhu | Pvd buffer layers for led fabrication |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100999684B1 (en) * | 2009-10-21 | 2010-12-08 | 엘지이노텍 주식회사 | Light emitting device and manufacturing method |
| KR101903445B1 (en) * | 2012-01-10 | 2018-10-05 | 삼성디스플레이 주식회사 | Semiconductor device and method for manufacturing thereof |
| CN104103720A (en) * | 2014-07-24 | 2014-10-15 | 安徽三安光电有限公司 | Method for preparing nitride semiconductor |
-
2014
- 2014-07-24 CN CN201410354965.0A patent/CN104103720A/en active Pending
-
2015
- 2015-03-02 WO PCT/CN2015/073465 patent/WO2016011810A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1846310A (en) * | 2003-09-24 | 2006-10-11 | 三垦电气株式会社 | Nitride semiconductor device and manufacturing method thereof |
| US20130285065A1 (en) * | 2012-04-26 | 2013-10-31 | Mingwei Zhu | Pvd buffer layers for led fabrication |
| CN102832241A (en) * | 2012-09-14 | 2012-12-19 | 电子科技大学 | Gallium-nitride-base heterostructure field effect transistor with transverse p-n junction composite buffering layer structure |
Cited By (14)
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|---|---|---|---|---|
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| WO2016165558A1 (en) * | 2015-04-15 | 2016-10-20 | 厦门市三安光电科技有限公司 | Nitride light emitting diode structure and preparation method thereof |
| WO2016173359A1 (en) * | 2015-04-29 | 2016-11-03 | 厦门市三安光电科技有限公司 | Light-emitting diode structure and preparation method therefor |
| CN106409996A (en) * | 2016-11-08 | 2017-02-15 | 湘能华磊光电股份有限公司 | Epitaxial growth method capable of improving LED chip property uniformity |
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