CN104090847B - Address distribution method of solid-state storage device - Google Patents

Abstract

The invention discloses an address allocation method of a solid-state storage device, which is suitable for multi-channel solid-state storage devices based on flash memory, belongs to the field of solid-state storage, and solves the problem of conflict between read and write requests existing in existing allocation strategies. Solve the problem that the response time of requests becomes longer in workloads with mixed read and write requests. The method of the invention includes channel weight distribution, physical address distribution and conflict prediction and avoidance mechanism. The invention allocates different weights for read and write requests and garbage collection operations, and the weights can be adjusted according to user needs to meet different read and write performance requirements, fully utilize the parallelism inside solid-state storage devices, and according to load conditions, Choose an appropriate physical address for write requests, reduce read-after-write conflicts and reduce garbage collection operations blocking write requests. Realize the reduction of the read and write response time of the solid-state storage device and the improvement of the performance of the solid-state storage device.

Description

A method for allocating addresses of solid-state storage devices

technical field

The invention belongs to the technical field of solid-state storage, and more particularly relates to an address allocation method of a solid-state storage device.

Background technique

Solid-state storage devices are a new type of computer storage devices that are different from mechanical hard disks. Compared with traditional hard disks, flash-based solid-state storage devices have the characteristics of high density, low energy consumption, no noise, anti-vibration, etc., and it has lower read and write delays and higher throughput rates.

Due to the characteristics of flash media, flash-based solid-state storage devices also have the following drawbacks:

(1) Erase first and then write: the flash memory medium cannot be updated in situ when writing data, and the physical block of the target address needs to be erased first, and then the data is updated. The basic units of the erase operation and the read and write operations are different. The erase operation takes the physical block as the unit, and the read and write operations take the physical page as the unit. Usually, a physical block contains 64 or 128 physical pages.

(2) Speed difference of read, write and erase operations: in flash media, the time for a single read operation is about 15-50 μs, the time for a write operation is about 200 μs, and the time for an erase operation is about 50 ms. The difference in read and write speed will cause the blocking problem of the read operation. When the read request arrives after the write request, the read request will wait for a long time due to the long write request processing time. The wipe operation takes a long time, causing subsequent requests to wait for a long time.

(3) Flash memory life: The life of flash memory particles is calculated according to the number of Program/Erase (programming/erasing). The life of MLC (full name, multi-level storage unit flash memory) is generally 1000-10000 times. Storage unit flash memory) is about 100,000 times.

In order to make full use of the speed advantages of flash memory chips and solve the problems of flash memory chips, a flash conversion layer is added to solid-state storage devices. The flash translation layer mainly provides three functions of address mapping, garbage collection and wear leveling. Address mapping is the core of the flash translation layer, which provides mapping from logical addresses to physical addresses through a mapping table. The function of garbage collection is to reclaim the invalid pages in the solid-state storage device, merge them into clean physical blocks, and increase the available space of the device. Wear leveling is used to ensure the balance of erasing times between physical blocks in the solid-state storage device, and to ensure the life and reliability of the solid-state storage device. Functions such as garbage collection and wear leveling rely on the address mapping table to achieve.

Flash-based solid-state storage usually consists of multiple independent channels, each channel is connected to multiple flash memory chips, and the chip can be divided into wafers, groups, blocks and pages. The read and write speed of a single chip and the transmission speed of a single channel are limited. In order to improve the performance of solid-state storage devices as much as possible, it is necessary to make full use of the parallelism between channels and chips.

In solid-state storage devices, address allocation refers to determining free physical pages for logical pages that need to be written to the device. According to the range of selected physical pages, it is mainly divided into static allocation methods, dynamic allocation methods, and hybrid allocation methods. Different address allocation methods have different utilization methods of parallelism inside the solid-state storage device, so they have different impacts on performance. Under normal circumstances, the read performance of the static allocation method is better than that of the dynamic allocation method, while the write performance is worse than that of the dynamic allocation method.

In the static allocation method, logical pages are allocated to specified channels, chips, wafers, and groups according to predefined rules. According to the different allocation rules, it can be divided into many different static allocation methods. According to the different arrangement and combination sequences of <channel, chip, wafer, group>, it can be arranged into 24 different static allocation methods.

In dynamic allocation, logical pages can select all free physical pages in the device. Considering factors such as channels, chips, wafers, grouping busy and idle, and physical block wear and tear, the specific location of allocation is finally determined. Using a fully dynamic allocation method can effectively improve write performance and allow write requests to be responded in a relatively short period of time.

The hybrid allocation method combines the characteristics of the static allocation method and the dynamic allocation method. The allocation of the four levels of channels, chips, wafers, and groups is partially specified by static rules, and some are specified by dynamic rules. For example, static allocation channels, dynamic allocation of chips, wafers, groups, etc. according to busy or idle.

At present, static address allocation is widely used in solid-state storage devices. Static address allocation can provide better continuous read and write performance, but the performance of random read and write is poor. The request is allocated to the specific location inside the solid-state storage device, which is calculated from the logical address of the request. When the logical address of the request is randomly distributed, there will be a large number of requests for contention for resources such as internal channels of the solid-state storage device, resulting in requests in some channels Very intensive, while some channels request little or no access. In particular, the location of the data accessed by the read request has been determined according to the address. When the write request occupies channel resources, the response time of the read request continues to rise, and the performance of the solid-state storage device decreases significantly.

Dynamic address allocation can improve the write performance of solid-state storage devices, but it cannot effectively reduce conflicts between read and write requests, and the read performance is lower than static address allocation.

Contents of the invention

In view of the above defects or improvement needs of the prior art, the present invention provides an address allocation method based on channel weights, the purpose of which is to realize the scheduling of read and write requests inside the solid state disk, and make full use of the parallelism inside the solid state storage device. This solves the performance degradation caused by the internal resource contention caused by the read and write requests of the solid state storage device in a mixed read and write environment.

In order to achieve the above object, the present invention provides a method for allocating addresses of solid-state storage devices, said method comprising the following steps:

(1) Request receiving step: The solid-state storage device receives the read and write request sent by the upper file system, judges the type of the received request and performs corresponding operations, if it is a write request, directly adds the request to the end of the request queue , waiting for processing; if it is a read request, look up the mapping table according to the logical address of the request to obtain its corresponding physical address, and calculate the channel information corresponding to the request according to the physical address, pre-process the corresponding weight of the read request, according to the known Channel information, add the weight of the read operation to the corresponding channel, and add this request to the end of the request queue, waiting for processing;

(2) Request queue processing steps: the solid-state storage device processes unprocessed requests stored in the request queue in a first-in-first-out manner, and sequentially assigns addresses;

(3) Read request distribution step: if the request taken out from the request queue is a read request, according to the known information of the mapping table in the request receiving step, the request is added to the tail of the channel queue of the corresponding channel, waiting for processing;

(4) Write request allocation step: if the request taken out from the request queue is a write request, then according to the weight of each channel, compare the channel with the smallest weight, and select the chip corresponding to the write request according to the chip busy or idle information. Wafer, packet, physical block and physical page, and calculate the corresponding physical address; add the request to the tail of the channel queue of the corresponding channel, change the weight of the corresponding channel, and wait for processing;

(5) Channel queue processing step: the flash memory controller takes out the request from the channel queue, and performs corresponding operations on the flash memory chip according to the request physical address, request size, and request type information obtained in the request receiving step and the request queue processing step , read the corresponding data information from the flash memory or write the data carried by the request into the physical page of the flash memory corresponding to its physical address; when the read and write operations of the flash memory chip are completed, the flash memory controller returns the completion information to the solid state disk controller, And change the weight of the corresponding channel according to the type of request; when the read operation in the channel is completed, the weight of the corresponding channel is subtracted from the weight of the read operation, and when the write operation is completed, the weight of the corresponding channel is subtracted from the weight of the write operation;

(6) Garbage collection processing steps: when a garbage collection operation is triggered, add the weight of the garbage collection operation to the channel performing the garbage collection operation, and after the garbage collection operation is completed, subtract the weight of the garbage collection operation from the weight of the corresponding channel.

In one embodiment of the present invention, the request receiving step specifically includes:

(1.1) The solid-state storage device receives the read-write request generated by the upper-level file system or the cache of the solid-state storage device, and the read-write request includes at least a logical page address, a request size, and read-write operation information, and performs substep (1.2);

(1.2) Determine whether the request size is greater than the size of a physical page, if greater, the rotor step (1.3); otherwise the rotor step (1.4);

(1.3) Calculate the number n of physical pages that this request needs to occupy, divide it into n requests, each request corresponds to a physical page, rotor step (1.4);

(1.4) Judging the operation type of the request, if it is a write request, the rotor step (1.7); if it is a read request, the rotor step (1.5);

(1.5) According to the logical address of read request, look up the mapping table to obtain the corresponding physical address, the corresponding channel i and chip of this request can be known by the physical address, and i corresponds to a certain channel number in the solid-state storage device, rotor step (1.6);

(1.6) Calculate the channel weight corresponding to channel i W _i =W _i +W _R , W _R is the read request weight, rotor step (1.7);

(1.7) Add requests to the tail of the request queue in order.

In one embodiment of the present invention, the request queue processing step specifically includes:

(2.1) Query the status of the request queue, and judge whether the request queue is empty, if so, the rotor step (2.3), otherwise the rotor step (2.2);

(2.2) Read the requests at the head of the request queue and classify them according to the request operation information. If it is a read request, go to step (3); if it is a write request, go to step (4).

In one embodiment of the present invention, the read request allocation step specifically includes: taking out the read request from the head of the request queue, finding the channel number i corresponding to the request in substep (1.5), and adding the read request to the channel i queue At the end, turn to step (5).

In one embodiment of the present invention, the write request allocation step specifically includes:

(4.1) Take out the write request from the head of the request queue, and carry out the substep (4.2);

(4.2) According to the characteristics of flash memory after erasing first, it can be seen that the write request requires free physical pages for storage, compare the weights W _i of each channel, and find the channel j with the smallest weight, and j corresponds to the channel with the smallest weight in the solid-state storage device at this time , the rotor step (4.3);

(4.3) Judging whether the flash memory conversion layer supports chip selection, if it supports, the rotor step (4.4); if not, add this write request to the tail of the channel j queue, and the rotor step (4.5);

(4.4) Polling to find the chip selection signal R/B of the chip under this channel, find the idle chip k, if all the chips are not idle, then select the first inquired chip k, determine the chip k to be written into the request, and write this The write request is added to the tail of the channel j queue, the rotor step (4.5)

(4.5) Channel j channel weight W _j =W _i +W _W , W _W is the write request weight, go to step (5)

In one embodiment of the present invention, the channel queue processing step specifically includes:

(5.1) Query the channel queue in turn, if the channel i queue is empty, go to step (6) and continue to query the next channel, if not empty, the rotor step (5.2);

(5.2) read channel queue head request, obtain information, rotor step (5.3);

(5.3) process the request of the head of the channel queue, if it is a read request, the rotor step (5.4); if it is a write request, the rotor step (5.5);

(5.4) According to the physical address of the read request, take out the data in the physical page corresponding to the physical address and send it to the upper application. When the read operation is completed, update the chip selection signal R/B and delete this request from the channel queue , at this time W _i =W _i -W _R , rotor step (5.1);

(5.5) According to the known write request channel and chip information, write the data into the corresponding free physical page. After the write operation is completed, update the chip select signal R/B, and delete this request from the channel queue. When W _i =W _i -W _W , the rotor step (5.1).

In one embodiment of the present invention, the channel queue processing step specifically includes:

(6.1) According to the proportion of free physical pages of channel i, determine whether garbage collection operation is required, if garbage collection operation is not required, rotor step (2.1), if garbage collection operation is required, rotor step (6.2);

(6.2) Execute the garbage collection operation in the channel, channel i channel weight W _i =W _i +W _GC , W _GC is the garbage collection weight, rotor step (6.3);

(6.3) The garbage collection operation is completed, the channel i channel weight W _i =W _i -W _GC , go to step (5).

Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

(1) Compared with the traditional static allocation method and dynamic allocation method, the present invention adds channel weights. The channel weight can represent the busyness of the channel. When a write request arrives, an appropriate channel allocation request can be selected according to the comparison of the channel weight, and the parallelism between channels can be fully utilized.

(2) When the present invention performs the garbage collection operation, the weight of the garbage collection operation is added to the corresponding channel, and the write request processing step can be compared according to the channel weight, so as to reasonably avoid the conflict between the garbage collection operation and the write request operation. Requests to allocate appropriate channels to reduce write request response time.

(3) The present invention adds a corresponding read operation weight W _R to the channel corresponding to the request when the read request enters the solid-state storage device instead of the read request being added to the channel queue. Through this step, the operation of the weight value improves the The priority of the read request reduces the possibility of the read request being blocked by the write request and reduces the conflict of read and write operations, thereby improving the performance of the solid-state storage device and reducing the response time of the read and write requests.

(4) The present invention ensures that read and write requests can be processed within a certain period of time through the first-in-first-out strategy of the channel queue, without long-term blocking of read or write requests, ensuring the fairness of read and write requests. Through the setting of the weight and the polling mechanism, the even distribution of write requests among the various channels is also guaranteed. The data is evenly distributed in each channel, which ensures the parallelism and performance of read requests, and at the same time keeps the wear degree of physical blocks in each channel balanced.

(5) The present invention can reasonably customize the weights W _R and W _W of the read and write operations according to the working environment used by the solid-state storage device, thereby controlling the priority of the read and write operations to adapt to the working environment that requires different read and write response times . The higher the ratio of W _R to W _W , the higher the priority of the read request, otherwise the higher the priority of the write request.

Description of drawings

FIG. 1 is a schematic flow diagram of an address allocation method for a solid-state storage device of the present invention;

FIG. 2 is a schematic flowchart of a request receiving step in an embodiment of the present invention;

Fig. 3 is a schematic flow chart of request queue processing steps in an embodiment of the present invention;

FIG. 4 is a schematic flow diagram of a read request allocation step in an embodiment of the present invention;

FIG. 5 is a schematic flow diagram of a write request allocation step in an embodiment of the present invention;

FIG. 6 is a schematic flow chart of channel queue processing steps in an embodiment of the present invention;

FIG. 7 is a schematic flowchart of garbage collection operation steps in an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

In order to understand the present invention clearly, relevant concepts are explained below:

NAND flash memory chip: The flash memory chip technology was invented by Toshiba in 1984. It is an electronic erasable programmable read-only memory. It is characterized by a simple structure and a considerable amount of data storage in a semiconductor per unit area. The side effect of this structure is that erasing and writing cannot be performed in units of bits, but only in large-scale operations in units of physical blocks.

Flash memory controller: manages the data stored in the flash memory chip and provides an access interface.

Channel: Connect the flash memory controller and flash memory chip in the solid-state storage device, and each channel consists of multiple chips;

Physical block: the storage area of the flash memory chip. Each flash memory chip contains several physical blocks, and each physical block contains a constant number of physical pages. The physical block is also the basic unit of the erase operation;

Physical page: The smallest storage unit of a flash memory chip. The physical page is the basic unit for allocating resources for write requests. Depending on the flash memory technology, the physical page size of different chips is different;

Logical page address: the general mechanism for describing the block where the data on the computer storage device is located, refers to the address of a certain data block or the data block pointed to by a certain address, which can be converted by the flash memory conversion layer to obtain the physical address;

Free physical page: the physical page in the solid-state storage device has not been used, that is, when it has no data, the physical page is a free physical page, which can be used for allocation of write requests and garbage collection operations;

Mapping table: It is a data structure that stores the one-to-one correspondence between logical page addresses and physical page addresses.

Garbage collection: The process of garbage collection is generally to transfer the valid data in the selected physical block to other physical blocks, and then perform an erase operation on it. Physical pages are reclaimed by erasing physical blocks with more invalid data.

Request queue: the queue used to store pending requests in the solid-state storage device, this queue is a first-in first-out queue;

Channel queue: the solid-state storage device is used to store requests from the request queue and assigned to each channel through the flash conversion layer. This queue is a first-in-first-out queue;

Read request weight W _R : According to the time required for the solid-state storage device to read a physical page data, it can also be customized by the user;

Write request weight W _W : The value of the time required to write a physical page data according to the solid-state storage device can also be customized according to the user's work needs. The higher the read-write weight ratio, the higher the priority of the read request, and vice versa, the higher the priority of the write request;

Garbage collection weight W _GC : The value is taken according to the time required for garbage collection operations in the channel, and can also be customized according to the user's work needs;

Channel weight: From the read and write request status in the channel queue, according to the calculation and statistics of the read and write request weight, the weight Wi corresponding to channel i at this time can be calculated. Wi can indicate the channel status at this time and perceive that the channel will be busy for a period of time in the future degree.

The address allocation method of a solid-state storage device provided by the present invention adopts a mixed allocation method, calculates and dynamically obtains a target channel through weight calculation, and selects a chip by detecting the R/B signals of each chip connected to the channel. This method is suitable for solid-state storage devices based on flash memory. As shown in Figure 1, the method of the present invention includes the steps of request receiving, request queue processing, read request distribution, write request distribution, channel queue processing and garbage collection operations, including:

(1) Request receiving step: The SSD storage device receives the read and write request sent by the upper file system, which includes the requested logical address, request size, read and write operations and other information. The device adopts different processing strategies for the read and write requests, Judge the received request type and perform corresponding operations. If it is a write request, it will directly add the request to the end of the request queue and wait for processing. If it is a read request, it will search the mapping table according to the logical address of the request to obtain its corresponding Physical address, according to the physical address, the channel information corresponding to the request can be calculated, the weight corresponding to the read request can be processed in advance, and the weight of the read operation can be added to the corresponding channel according to the known channel information, and this request can be added to the request The end of the queue, waiting for processing;

(2) Request queue processing steps: The request queue is the interface between the solid-state disk and the upper layer. Unprocessed requests will be stored in the request queue for processing. The request queue is designed in a first-in-first-out manner, and the requests in the queue are assigned addresses sequentially. ;

(3) Read request distribution steps: the request queue adopts a first-in-first-out queue, and the solid-state disk controller takes out the request at the head of the request queue, and adopts different distribution strategies for read and write requests; if the request is taken out from the request queue, it is received according to the request receiving step Look up the known information in the mapping table, take the request from the head of the request queue, add it to the tail of the channel queue of the corresponding channel, and wait for processing;

(4) Write request allocation step: If the request taken out from the request queue is a write request, then according to the weight of each channel, compare the channel with the smallest weight, and select the chip corresponding to the write request according to the information such as chip busy or idle , wafer, packet, physical block and physical page, and calculate the corresponding physical address; take the request from the head of the request queue, add it to the tail of the channel queue of the corresponding channel, change the weight of the corresponding channel, and wait for processing ;

(5) Channel queue processing step: the flash memory controller takes out the request from the channel queue, and according to the request physical address, request size, request type and other information obtained in the request receiving step and request queue processing step, the flash memory chip is correspondingly processed Operation, read the corresponding data information from the flash memory or write the data carried by the request into the physical page of the flash memory corresponding to its physical address; when the read and write operations of the flash memory chip are completed, the flash memory controller returns the completion information to the SSD controller , and change the weight of the corresponding channel according to the type of request; when the read operation in the channel is completed, the weight of the corresponding channel is subtracted from the weight of the read operation, and when the write operation is completed, the weight of the corresponding channel is subtracted from the weight of the write operation;

(6) Garbage collection processing steps: when the garbage collection operation is triggered, add the weight of the garbage collection operation to the channel for the garbage collection operation. The garbage collection operation takes a long time and the weight is set to be large, which reduces the allocation of write requests to the channel. Priority, after the garbage collection operation is completed, the weight of the corresponding channel minus the weight of the garbage collection operation.

The detailed operation of each step is described in detail below,

(1) The request receiving step, specifically as shown in Figure 2, includes the following sub-steps:

(1.1) The solid-state storage device receives the read-write request generated by the upper-level file system or the cache of the solid-state storage device, and the read-write request includes at least a logical page address, a request size, and read-write operation information, and performs substep (1.2);

(1.2) Determine whether the request size is greater than the size of a physical page, if greater, the rotor step (1.3); otherwise the rotor step (1.4);

(1.3) Calculate the number n of physical pages that this request needs to occupy, divide it into n requests, each request corresponds to a physical page, rotor step (1.4);

(1.4) Judging the operation type of the request, if it is a write request, the rotor step (1.7); if it is a read request, the rotor step (1.5);

(1.5) According to the logical address of the read request, the mapping table is checked to obtain the corresponding physical address, and the corresponding channel i (a certain channel number in the i corresponding solid-state storage device), chip, rotor step (1.6) can be known from the physical address;

(1.6) Calculate channel i corresponding to channel weight W _i =W _i +W _R , rotor step (1.7);

(1.7) Add the request to the tail of the request queue in order, and turn to step (2);

(2) Request queue processing steps, specifically as shown in Figure 3, including the following sub-steps:

(2.1) Query the status of the request queue, and judge whether the request queue is empty, if so, the rotor step (2.3), otherwise the rotor step (2.2);

(2.2) Read the request at the head of the request queue, classify it according to the request operation information, if it is a read request, go to step (3); if it is a write request, go to step (4);

(2.3) end;

(3) The read request allocation step, specifically as shown in Figure 4, includes the following sub-steps:

(3.1) Take out the read request from the head of the request queue, find the channel number i corresponding to the request in substep (1.5), add this read request to the tail of the channel i queue, and turn to step (5);

(4) Write request allocation step, specifically as shown in Figure 5, including the following sub-steps:

(4.1) Take out the write request from the head of the request queue, and carry out the substep (4.2);

(4.2) According to the characteristics of first erase and then write of flash memory, the write request needs to be stored in free physical pages, compare the weights W _i of each channel, and find the channel j with the smallest weight (j corresponds to the channel with the smallest weight in the solid-state storage device at this time ), the rotor step (4.3);

(4.3) Judging whether the flash memory conversion layer supports chip selection, if it supports, the rotor step (4.4); if not, add this write request to the tail of the channel j queue, and the rotor step (4.5);

(4.4) Polling to find the chip selection signal R/B of the chip under this channel, find the idle chip k, if all the chips are not idle, then select the first inquired chip k, determine the chip k to be written into the request, and write this The write request is added to the tail of the channel j queue, the rotor step (4.5)

(4.5) channel j channel weight W _j =W _i +W _W , turn to step (5);

(5) channel queue processing steps, specifically as shown in Figure 6, its sub-steps are as follows:

(5.1) Query the channel queue in turn, if the channel i queue is empty, go to step (6) and continue to query the next channel, if not empty, the rotor step (5.2);

(5.2) read channel queue head request, obtain information, rotor step (5.3);

(5.3) process the request of the head of the channel queue, if it is a read request, the rotor step (5.4); if it is a write request, the rotor step (5.5);

(5.4) According to the physical address of the read request, take out the data in the physical page corresponding to the physical address and send it to the upper application. When the read operation is completed, update the chip selection signal R/B and delete this request from the channel queue , at this time W _i =W _i -W _R , rotor step (5.1);

(5.5) According to the known write request channel and chip information, write the data into the corresponding free physical page. After the write operation is completed, update the chip select signal R/B, and delete this request from the channel queue. When W _i =W _i -W _W , rotor step (5.1);

(6) Garbage collection processing steps, specifically as shown in Figure 7, its sub-steps are as follows:

(6.1) According to the proportion of free physical pages of channel i, determine whether garbage collection operation is required, if garbage collection operation is not required, rotor step (2.1), if garbage collection operation is required, rotor step (6.2);

(6.2) Execute the garbage collection operation in the channel, channel i channel weight W _i =W _i +W _GC , rotor step (6.3);

(6.3) The garbage collection operation is completed, the channel i channel weight W _i =W _i -W _GC , go to step (5);

The solution of the present invention will be described below in conjunction with specific embodiments. The physical capacity of the solid-state storage device in this embodiment is 512GB, and there are 4 channels in the device, and each channel is connected to 4 32GB flash memory chips. Take the MT29F256G08CJAAB chip as an example, the physical page size in the chip is 8KB, and each physical block contains 256 physical pages, and every 2048 physical blocks form a group, two groups are packaged as a wafer, and four wafers form a chip .

Sequential write requests:

When the requests in the request queue are continuous write requests, according to the write request allocation step (4.2), the flash memory controller queries and compares the weights of each channel. At this time, the channel weights are arranged in a fixed order from small to large, such as channel 1<channel 2<channel 3<channel 0. According to the solution of the present invention, the write requests in the request queue are sequentially assigned to the queues of channel 1, channel 2, channel 3 and channel 0, the weight of the corresponding channel is increased and an idle chip is found through the chip selection signal. Because each channel has a write request, the comparison order of the weights of each channel will not change, and the write requests are evenly distributed in the channels 1, 2, 3, and 0 in order. When the read request accesses these continuous data, it can follow the channel Sequential readout makes full use of the parallelism between internal channels of solid-state storage devices.

Random write requests:

When the request in the request queue is a random write request, the processing method of the solution of the present invention is the same as that of the continuous write request, so that the random write performance is equivalent to the continuous write performance.

Sequential read requests:

When the request in the request queue is a continuous read request, according to the request receiving step (1.5), the flash memory controller searches the mapping table according to the read request logical address (lpn) to obtain the corresponding physical address. Since the requested physical address of the read request has been determined, the read request is assigned to a corresponding channel and waits for execution. Most of the data corresponding to the continuous read requests is the data that has been written continuously before. According to the solution of the present invention, the data has been evenly distributed in each channel and chip, and the continuous read request can also make full use of the parallelism of the device.

Random read requests:

Similar to how sequential read requests are handled. If the data requested by the read request is sent to the solid-state storage device within a continuous period of time, then according to the principle of processing random write requests in this solution, the data can also be evenly distributed in each channel and chip. If not, the data requested by random read requests may be distributed in one channel or even one chip. At this time, the subsequent requests need to wait for the previous requests to complete, which cannot take advantage of the parallelism of the flash memory device and the overall performance of the device. decline.

Mixed read and write requests:

When there are many write requests:

When a read-write mixed request appears in the request queue, follow the steps of the patent of the present invention. Assume that all channels are idle at this time, that is, the channel weights are all 0. At this time, write requests 1, 2, 3, 4, and 5 enter the request queue in turn, and write requests 1, 2, 3, and 4 are assigned to channels 0, 1, 2, and 3 in turn, waiting for data to be written to the corresponding flash memory In the chip, the corresponding write request weight W _W is added to the channel weights W0, W1, W2, and W3 at this time. At this time, read requests 1 and 2 enter the request queue. According to the logical address of the read request, directly search the mapping table to obtain the corresponding physical address, and calculate the request data from the physical address corresponding to channel 0 and channel 1. At this time, for channel 0, channel 1 Weight W1, W2 plus the corresponding read request weight W _R is W _W +W _R . At this time, the request at the forefront of the channel queue is a write request 5. According to the request judgment step (2), the request type is a write request, and then go to step (4). Step (4.2) Polling and comparing the weight W of each channel, finding the channel 2 with the smallest channel weight at this time, and assigning this request to the request queue of channel 2. At this time, the weight of channel 2 is W2=W _W +W _W . Continue to process read requests 1 and 2, write request 5 is assigned to channel 2, and read requests 1 and 2 can be directly assigned to channels 0 and 1 to wait for execution without waiting for write request 5 to be executed, resulting in a slowdown in the response time of read requests Increase.

When there are many read requests:

When a read-write mixed request appears in the request queue, follow the steps of the patent of the present invention. Assume that the distribution of requests in the channel queue is as follows: read requests 1, 2, 3, 4, write requests 1, read requests 6, 7, 8, write requests 2, read requests 9, 10, 11, 12, 13, 14, 15, 16. At this time, according to the calculation of multiple steps (1.6), when the write request 1 is at the head of the request queue and enters step (4), the channel weights W0 to W3 are 5*W _R , 3*W _R , 1 respectively *W _R and 8*W _R , at this time the minimum weight W2 corresponding to channel 2 is 1*W _R , according to step (4.2), assign write request 1 to channel 2, and join channel queue 2, by step (4.5) W2=1*W _R +W _W . At this time, continue to process subsequent read requests 6, 7, and 8 until write request 2 reaches the head of the request queue. At this time, read requests 1, 2, 3, and 4 have been completed, and the weights of channels 0 to 3 are 4*W _R , 3*W _R , Ww and 7*W _R , at this time, according to step (4.2), the channel 1 with the smallest weight at this time is obtained, and the weight is 3*W _R . Write request 2 is assigned to channel 1, at this time, the weight of channel 1 is W1=3*W _R +Ww.

Garbage collection operations:

When it is detected that there are not enough free physical pages in the channel i and the garbage collection operation is performed, the weight value W _GC of the garbage collection operation is added to the weight value of the channel i at this time. If there is a write request to access the solid-state storage device at this time, according to the sub-step (4.2), the controller will make a judgment according to the weight, and select the channel with the smallest channel weight. If the weight of other channels is less than the weight of channel i, this The write request will not be assigned to channel i, and the write request does not have to wait for the completion of the garbage collection operation, effectively reducing the response time of the write request.

extreme case:

In the mixed request queue, read requests continuously read the data of the same channel, so that the weight of this channel remains at a high value. At this time, when the flash memory controller allocates write requests, it will not allocate write requests to this channel. In this channel, the blocking between read and write requests is avoided, and the delay of read and write requests is reduced, but the number of channels available for allocation to write requests is reduced, and the parallelism between internal channels of solid-state storage devices is weakened, so that The resources of the solid-state storage device are underutilized. At the same time, this will also affect the wear leveling of the entire solid-state storage device.

Compared with the static allocation method, the scheme of the present invention can flexibly select the channel to which the write request is allocated, and through the setting of the weight value and the priority processing of the read request to the weight value, a certain priority degree of the read request response is guaranteed, and the read rate of each channel is reduced. Write requests interfere with each other, reduce the blocking between read and write requests, and reduce the read and write response time of solid-state storage devices.

In the scheme of the present invention, both the request queue and the channel queue are first-in-first-out (FIFO) queues, and each channel processes requests in parallel, regardless of the order among the requests, and the requests in the request queue and the channel queue are executed sequentially.

Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (7)

1. the address distribution method of a solid storage device, it is characterised in that described method comprises the steps:

(1) request receiving step: solid storage device receives the read-write requests sent by topmost paper system, the request type received is judged and operates accordingly, if write request, then directly request is joined request queue tail of the queue, wait pending；If read request, then search mapping table according to the logical address of request and obtain the physical address of its correspondence, can be calculated, according to physical address, the channel information that request is corresponding, anticipate the weights that read request is corresponding, i.e. read request weights W_R, according to known channel information, give corresponding passage plus read request weights W_R, and this request is joined request queue tail of the queue, wait pending；Described read request weights W_RIt is according to required time value according to solid storage device one number of physical pages of reading, or is needed by user job self-defined；

(2) request queue processes step: solid storage device uses the mode of first in first out to process to leaving untreated request in request queue in, carries out address distribution successively；

(3) read request allocation step: if the request from request queue taking-up is read request, searches channel information known to mapping table according in request receiving step, request is joined the afterbody of the channel queue of respective channel, waits pending；

(4) write request allocation step: if the request from request queue taking-up is write request, then according to the passage weights size of each passage, relatively obtain the passage that weights are minimum, and select corresponding chip, wafer, packet, physical block and the Physical Page of this write request according to chip busy information, and thus calculate the physical address of correspondence；Request is joined the afterbody of the channel queue of respective channel, the passage weights of change respective channel, its W_j=W_i+W_W, wait pending；Wherein, described passage weights refer to, by the read-write requests state in channel queue, count now corresponding for passage i weights Wi, Wi according to read-write requests weight computing and can represent channel status now the passage busy extent in perception a period of time in future；W_WFor write request weights, refer to that writing a number of physical pages according to solid storage device according to required time value or needs self-defined according to user job；

(5) channel queue processes step: flash controller takes out request from channel queue, and according to being processed request physical address, request size, the request type information obtained in step by request receiving step and request queue, flash chip is operated accordingly, from flash memory, reads corresponding data information maybe the data that request is carried are written in the flash memory Physical Page that its physical address is corresponding；After the read-write operation of flash chip completes, flash controller has returned information, and the passage weights of the Type Change respective channel according to request to solid state disk controller；In passage, read operation completes, and the passage weights of respective channel deduct read request weights, and write operation completes, and the passage weights of respective channel deduct write request weights；

(6) garbage reclamation processes step: according to passage i free physical page ratio, it may be judged whether need to carry out garbage collection operation, when triggering garbage collection operation, for carrying out the passage of garbage collection operation plus garbage reclamation weights W_GC, after garbage collection operation completes, the passage weights of respective channel deduct garbage reclamation weights W_GC；Described garbage reclamation weights W_GCRefer to according to the time value carried out in passage needed for garbage collection operation, or need self-defined according to user job.

2. the method for claim 1, it is characterised in that described request receiving step specifically includes:

(1.1) solid storage device receives topmost paper system or the read-write requests of solid storage device caching generation, and described read-write requests, including at least logical page address, request size, read-write operation information, carries out sub-step (1.2)；

(1.2) size asking size whether to be more than a Physical Page, if being more than, rotor step (1.3) are judged；Otherwise rotor step (1.4)；

(1.3) calculate number of physical pages n that this request needs to take, be divided into n request, the corresponding Physical Page of each request, rotor step (1.4)；

(1.4) action type of request is judged, if write request, rotor step (1.7)；If read request, rotor step (1.5)；

(1.5) look into mapping table according to the logical address of read request and obtain the physical address of correspondence, physical address understand the passage i corresponding to this request, chip, a certain channel number in i correspondence solid storage device, rotor step (1.6)；

(1.6) passage i respective channel weights W is calculated_i=W_i+W_R, W_RFor read request weights, rotor step (1.7)；

(1.7) request is sequentially added the afterbody of request queue.

3. method as claimed in claim 1 or 2, it is characterised in that described request queue processes step and specifically includes:

(2.1) inquiry request quene state, it is judged that whether request queue is empty, is then rotor step (2.3), otherwise rotor step (2.2)；

(2.2) read request queue team head request, classifies according to action message, if read request, goes to step (3)；If write request, go to step (4).

4. method as claimed in claim 1 or 2, it is characterized in that, described read request allocation step specifically includes: take out read request from request queue team head, the channel number i corresponding by checking in request in sub-step (1.5), this read request is added passage i queue tail, goes to step (5).

5. method as claimed in claim 1 or 2, it is characterised in that described write request allocation step specifically includes:

(4.1) take out write request from request queue team head, carry out sub-step (4.2)；

(4.2) write attribute after first being wiped from flash memory, write request needs free physical page to store, and compares each passage weights W_i, the passage of weights minimum, rotor step (4.3) in the corresponding now solid storage device of passage j, j finding weights minimum；

(4.3) judge whether flash translation layer (FTL) supports that chip selects, if supporting, rotor step (4.4)；If not supporting, this write request is added passage j queue tail, rotor step (4.5)；

(4.4) chip chip selection signal R/B under poll searches this passage, finds free chip die k, if all chips are the most idle, then select the chip k of first inquiry, determine the chip k that request will write, this write request is added passage j queue tail, rotor step (4.5)；

(4.5) passage j passage weights W_j=W_i+W_W, W_WFor write request weights, go to step (5).

6. method as claimed in claim 1 or 2, it is characterised in that described channel queue processes step and specifically includes:

(5.1) inquire about channel queue successively, if passage i queue is empty, goes to step (6) and continue to inquire about next passage, if not empty, rotor step (5.2)；

(5.2) read channel queue's head request, obtain information, rotor step (5.3)；

(5.3) request for the treatment of channel queue team head, if read request, rotor step (5.4)；If write request, rotor step (5.5)；

(5.4) according to the physical address of read request, take out the data in the Physical Page that physical address is corresponding, and be sent to upper layer application, after read operation completes, update chip chip selection signal R/B, this request is deleted from channel queue, now W_i=W_i-W_R, rotor step (5.1)；

(5.5) according to known write request passage, chip information, write data in the free physical page of correspondence, after write operation completes, update chip chip selection signal R/B, this request is deleted from channel queue, now W_i=W_i-W_W, rotor step (5.1).

7. method as claimed in claim 1 or 2, it is characterised in that described garbage reclamation processes step and specifically includes:

(6.1) according to passage i free physical page ratio, it may be judged whether need to carry out garbage collection operation, if being made without garbage collection operation, rotor step (2.1), if desired carry out garbage collection operation, rotor step (6.2)；

(6.2) garbage collection operation in passage, passage i passage weights W are performed_i=W_i+W_GC, W_GCFor garbage reclamation weights, rotor step (6.3)；

(6.3) garbage collection operation completes, passage i passage weights W_i=W_i-W_GC, go to step (5).