CN104078441A - Integrated inductor structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses an integrated inductance structure and a manufacturing method thereof, wherein the integrated inductance structure comprises the following components: a semiconductor substrate, a plurality of through silicon vias and an inductor. The through silicon vias are formed in the semiconductor substrate and arranged in a specific pattern, and a metal material is filled in the through silicon vias to form a pattern type grounding protection; and the inductor is formed above the semiconductor substrate. The manufacturing method of the integrated inductor structure comprises the following steps: forming a semiconductor substrate; forming a plurality of through silicon vias in the semiconductor substrate, and arranging the plurality of through silicon vias into a specific pattern; filling a metal material in the through silicon vias to form a patterned ground protection; and forming an inductor over the semiconductor substrate.

Description

Integrated inductor structure and method for manufacturing integrated inductor structure

technical field

The present invention relates to an integrated inductance structure and a method for manufacturing the integrated inductance structure, in particular to an integrated inductance structure with an innovative patterned ground shield (Patterned Ground Shield, PGS) and a method for manufacturing the integrated inductance structure .

Background technique

With the development of IC manufacturing towards the system-on-a-chip (SoC), passive components such as integrated inductors have been widely integrated into high-frequency integrated circuits. Since IC manufacturing generally uses a silicon substrate structure, integrated inductors have a low quality factor (Q-factor) problem due to substrate loss.

Therefore, it has been proposed to use a patterned ground shield (PGS) made of polysilicon (polysilicon) metal to reduce the electromagnetic eddy current (eddy current) of the integrated inductor, so as to improve the quality factor. For example, please refer to Figure 1 1 is a schematic cross-sectional view of an integrated inductor structure 50 disclosed in US Pat. No. 8,106,479. As shown in FIG. 1 , the patterned ground guard 22 is formed between the inductor 30 and the gate oxide layer 24. However, such a patterned ground guard 22 has a very good blocking effect on the electromagnetic eddy current formed in the deep layer of the semiconductor substrate 10. Poor, and the material of the patterned grounding protection 22 in FIG. 1 is polysilicon, which cannot effectively reduce the electromagnetic eddy current.

Contents of the invention

In view of this, the main purpose of the present invention is to provide an integrated inductance structure and a manufacturing method of the integrated inductance structure, which has an innovative patterned ground shield (Patterned GroundShield, PGS), which can reduce electromagnetic eddy current (eddy current) and Improve the quality factor (Q-factor).

According to the present invention, an integrated inductor structure is disclosed, and the integrated inductor structure includes: a semiconductor substrate, a plurality of through silicon vias (Through Silicon Via, TSV) and an inductor. The plurality of through-silicon vias are formed in the semiconductor substrate and arranged in a specific pattern, and a metal material is filled in the plurality of through-silicon vias to form a patterned ground shield (Patterned Ground Shield, PGS); and the inductor formed on the semiconductor substrate.

According to the present invention, a method for manufacturing an integrated inductance structure is also disclosed. The method for manufacturing an integrated inductance structure includes: forming a semiconductor substrate; forming a plurality of through-silicon vias (Through Silicon Via, TSV) in the semiconductor substrate; A plurality of TSVs are arranged in a specific pattern; a metal material is filled in the TSVs to form a Patterned Ground Shield (PGS); and an inductor is formed above the semiconductor substrate.

In summary, compared with the prior art, the integrated inductance structure and the manufacturing method of the integrated inductance structure disclosed in the present invention have an innovative patterned ground shield (Patterned GroundShield, PGS), which can block the deep electromagnetic eddy current in the semiconductor substrate (eddy current) formation, and can block the possible path of electromagnetic eddy current, the blocking effect is more thorough, and the quality factor (Q-factor) is improved.

Description of drawings

FIG. 1 is a schematic cross-sectional view of an integrated inductor structure disclosed in US Pat. No. 8,106,479.

FIG. 2 is a schematic cross-sectional view of an integrated inductor structure according to a first embodiment of the present invention.

FIG. 3 is a structural top view of the integrated inductor structure according to the first embodiment of the present invention.

FIG. 4 is a flow chart illustrating a first embodiment of a method for manufacturing an integrated inductor structure according to the integrated inductor structure according to the first embodiment of the invention.

FIG. 5 is a schematic cross-sectional view of an integrated inductor structure according to a second embodiment of the present invention.

FIG. 6 is a structural top view of the integrated inductor structure according to the second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of an integrated inductor structure according to a third embodiment of the present invention.

FIG. 8 is a structural top view of the integrated inductor structure according to the second embodiment of the present invention.

FIG. 9 is a flow chart illustrating a second embodiment of the manufacturing method of the integrated inductor structure of the present invention according to the integrated inductor structure of the second embodiment of the present invention described above.

FIG. 10 is a schematic cross-sectional view of an integrated inductor structure according to a fourth embodiment of the present invention.

FIG. 11 is a structural top view of the integrated inductor structure of the fourth embodiment of the present invention.

FIG. 12 is a simplified schematic diagram of the integrated inductor structure applied to the flip chip technology according to the fourth embodiment of the present invention.

FIG. 13 is a flow chart illustrating a fourth embodiment of the method for manufacturing an integrated inductor structure according to the fourth embodiment of the invention.

FIG. 14 is a schematic cross-sectional view of an integrated inductor structure 900 according to a fifth embodiment of the present invention.

FIG. 15 is a bottom top view of the integrated inductor structure according to the fifth embodiment of the present invention.

FIG. 16 is a simplified schematic diagram of an integrated inductor structure applied to a 3D chip according to a fifth embodiment of the present invention.

FIG. 17 is a flow chart illustrating a fifth embodiment of the method for manufacturing the integrated inductor structure of the present invention according to the integrated inductor structure of the fifth embodiment of the present invention.

FIG. 18 is a simplified schematic diagram of an integrated inductor structure applied to a three-dimensional chip according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

10: Semiconductor substrate

22: Pattern ground protection

24: Gate oxide layer

30: inductance

50: Integrated inductor structure

200: Integrated inductor structure

202: Semiconductor substrate

204: deep groove

206: Inductance

208: Patterned ground protection

500: Integrated inductor structure

502: Semiconductor substrate

504: TSV

506: Inductance

508: Patterned Ground Guard

510: masking metal layer pattern

700: Integrated inductor structure

702: Semiconductor substrate

704: Redistribute metal layer

706: Inductance

708: Patterned Ground Guard

720: first chip

730: second chip

900: Integrated inductor structure

902: Semiconductor substrate

904: TSV

906: Inductance

908: Patterned Ground Guard

910: Backside Redistribution Metal Layer

920: 3D chip

930: First chip

940: Silicon Insert

950: second chip

1120: 3D chip

1130: first chip

1140: Silicon Insert

1150: second chip

Detailed ways

Please refer to FIG. 2 , which is a schematic cross-sectional view of an integrated inductor structure 200 according to a first embodiment of the present invention. As shown in FIG. 2 , the integrated inductor structure 200 includes: a semiconductor substrate 202 , a plurality of deep trenches 204 and an inductor 206 . The plurality of deep trenches 204 are formed in the semiconductor substrate 202 and arranged in a specific pattern (for example, as shown in FIG. 3 , which is a structural top view of the integrated inductor structure 200, but the present invention is not limited thereto), and The plurality of deep trenches 204 are filled with a metal material (such as copper, aluminum or gold or their alloys, etc.) to form a patterned ground shield (Patterned Ground Shield, PGS) 208, wherein the plurality of deep trenches 204 The width may be less than 20 microns, and the depth of the plurality of deep trenches 204 may be, eg, less than 100 microns but greater than 20 microns, and the inductor 206 is formed above the semiconductor substrate 202 . In addition, in the present invention, there may not be any redundant patterned ground protection between the inductor 206 and the semiconductor substrate 202 . Please note that the above-mentioned embodiment is only used as an illustration of the present invention, and is not a limitation of the present invention. For example, the patterned grounding shield 208 can also be grounded in addition to further reduce electromagnetic eddy current (eddy current) and improve the quality factor (Q-factor). Referring to FIGS. 2 and 3 , preferably, the patterned ground guard 208 is substantially below the inductor 206 and is orthogonal (perpendicular) thereto.

Different from the past, because the current advanced semiconductor process technology can produce deep trenches with extremely small widths, the present invention can thereby produce deep trenches 204 with this specific pattern in the semiconductor substrate 200, and the deep trenches 204 The metal material is filled in to form an innovative patterned ground shield, which is used to replace the patterned ground shield with polysilicon placed between the inductor and the gate oxide layer in the traditional technology (please refer to Figure 1).

Please refer to FIG. 4 . What FIG. 4 depicts is a flow chart of a first embodiment of the method for manufacturing an integrated inductance structure of the present invention based on the above-mentioned integrated inductance structure 200. If substantially the same result can be obtained, the process flow The steps in FIG. 4 do not necessarily need to be executed in the order shown in FIG. 4 , nor do they need to be continuous, that is, other steps can be inserted between these steps. The first embodiment of the method for manufacturing an integrated inductor structure of the present invention includes the following steps:

Step 400: Form a semiconductor substrate.

Step 402: Form a plurality of deep trenches in the semiconductor substrate, and arrange the plurality of deep trenches into a specific pattern.

Step 404 : Fill a metal material in the plurality of deep trenches to form a patterned ground shield.

Step 406 : Form an inductor over the semiconductor substrate.

Please note that the above-mentioned embodiments are only used as illustrations of the present invention, and are not limitations of the present invention. For example, the steps of the manufacturing method of the integrated inductor structure of the present invention may further include: grounding the patterned ground shield. Preferably, the patterned ground shield is substantially orthogonal (perpendicular) to the inductor below it.

Please refer to FIG. 5 , which is a schematic cross-sectional view of an integrated inductor structure 500 according to a second embodiment of the present invention. As shown in FIG. 5 , the integrated inductor structure 500 includes: a semiconductor substrate 502 , a plurality of through silicon vias (Through Silicon Via, TSV) 504 and an inductor 506 . The plurality of TSVs 504 are formed in the semiconductor substrate 500 and arranged in a specific pattern (for example, as shown in FIG. 6 , which is a structural top view of the integrated inductor structure 500, but the present invention is not limited thereto), And the multiple TSVs 504 are filled with a metal material (such as copper, aluminum or gold, etc.) to form a patterned ground shield (Patterned Ground Shield, PGS) 508, wherein the multiple TSVs 504 width It can be smaller than 20 microns, and the inductor 506 is formed above the semiconductor substrate 502 . Please note that in the present invention, there may not be any redundant patterned ground protection between the inductor 506 and the semiconductor substrate 502 . In addition, the integrated inductor structure 500 of the present invention can be used as a silicon interposer (Si Interposer) in a three-dimensional chip (3D IC). Please note that the above-mentioned embodiment is only used as an illustration of the present invention, and is not a limitation of the present invention. For example, the patterned grounding shield 508 can also be grounded in addition to greatly reduce the electromagnetic eddy current (eddy current) and improve Quality factor (Q-factor). In addition, in a third embodiment of the present invention, the integrated inductor structure 500 may further include: a shielding metal layer pattern 510, connecting the plurality of TSVs 504 according to the specific pattern, as shown in FIG. 7 , Moreover, the shielding metal layer pattern 510 and the plurality of TSVs 504 can form a patterned ground guard 508 together, as shown in FIG. 8 ; and preferably, the shielding metal layer pattern 510 of the patterned ground guard 508 is substantially Below the inductor 506 it is orthogonal (perpendicular) to it. Wherein, the metal layer can be formed, for example, by using the first layer of metal (metal1) in the semiconductor process.

Different from the past, because the current advanced semiconductor process technology can produce TSVs with extremely small widths, the present invention can use this to fabricate TSVs 504 with the specific pattern in the semiconductor substrate 500, and in TSVs. The metal material is filled in the TSV 504 to form an innovative patterned ground shield, which is used to replace the patterned ground shield formed by polysilicon disposed between the inductor and the gate oxide layer in the conventional technology (please refer to FIG. 1 ).

Please refer to FIG. 9. What FIG. 9 depicts is a flow chart of a second embodiment of the method for manufacturing an integrated inductance structure of the present invention based on the above-mentioned integrated inductance structure 500. If substantially the same result can be obtained, the process flow The steps in FIG. 9 do not necessarily need to be executed in the order shown in FIG. 9 , nor do they need to be continuous, that is, other steps can be inserted between these steps. The second embodiment of the integrated inductor structure manufacturing method of the present invention includes the following steps:

Step 600: Form a semiconductor substrate.

Step 602: Form a plurality of TSVs in the semiconductor substrate, and arrange the plurality of TSVs in a specific pattern.

Step 604 : Fill a metal material in the plurality of TSVs to form a patterned ground shield.

Step 606: Form an inductor over the semiconductor substrate.

Please note that the above-mentioned embodiments are only used as illustrations of the present invention, and are not limitations of the present invention. For example, the steps of the manufacturing method of the integrated inductor structure of the present invention may further include: grounding the patterned ground shield. In addition, in a third embodiment of the present invention, the method for manufacturing the integrated inductor structure of the present invention may further include: connecting a shielding metal layer pattern to the plurality of TSVs according to the specific pattern. And preferably, the plurality of shielding metal layer patterns of the patterned ground shield are substantially orthogonal (perpendicular) to the inductor under the inductor. Wherein, the metal layer can be formed, for example, by using the first layer of metal (metal1) in the semiconductor process.

Please refer to FIG. 10 , which is a schematic cross-sectional view of an integrated inductor structure 700 according to a fourth embodiment of the present invention. As shown in FIG. 10 , the integrated inductor structure 700 includes: a semiconductor substrate 702 , a redistribution layer (RDL) 704 and an inductor 706 . The inductor 706 is formed on the semiconductor substrate 702; and the redistribution metal layer 704 is formed on the inductor 706 and has a specific pattern (for example, as shown in FIG. 11, FIG. 11 is a structural top view of the integrated inductor structure 700, but this The invention is not limited thereto) to form a patterned ground shield (Patterned Ground Shield, PGS) 708, wherein the material of the redistribution metal layer 704 can be aluminum. Please note that in the present invention, there may not be any redundant patterned ground protection between the inductor 706 and the semiconductor substrate 702 . In addition, the integrated inductor structure 700 of the present invention can be applied to an integrated passive device (Integrated Passive Device, IPD) in a three-dimensional chip (3D IC). The integrated inductor structure 700 of this embodiment can be applied to the flip chip technology (Flip Chip), please refer to FIG. 12 , which shows the application of the integrated inductor structure 700 according to the fourth embodiment of the present invention to the flip chip technology. A simplified schematic diagram, as shown in FIG. 12 , when a first chip 720 including the integrated inductor structure 700 is turned upside down, the patterned ground protection 708 formed by the upper redistributed metal layer 704 in the integrated inductor structure 700 Not only can the electromagnetic eddy current (eddy current) be reduced and the quality factor (Q-factor) can be improved, but also the inductive magnetic field flow in the upper layer of the first chip 720 can be more effectively prevented from affecting the signal of the lower layer of a second chip 730 . Please note that the above-mentioned embodiment is only used as an illustration of the present invention, and is not a limitation of the present invention. For example, the patterned grounding shield 708 can also be grounded in addition to further reduce electromagnetic eddy current (eddy current) and improve the quality factor (Q-factor). As shown in FIGS. 10 and 11 , preferably, the pattern in which the RDM layer 704 is substantially above the inductor 706 is orthogonal (perpendicular) thereto.

Please refer to FIG. 13. What FIG. 13 depicts is a flow chart of a fourth embodiment of an integrated inductance structure manufacturing method of the present invention based on the above-mentioned integrated inductance structure 700. If substantially the same result can be obtained, the process flow The steps in FIG. 13 do not necessarily need to be executed in the order shown in FIG. 13 , nor do they need to be continuous, that is, other steps can be inserted between these steps. The fourth embodiment of the integrated inductor structure manufacturing method of the present invention includes the following steps:

Step 800: Form a semiconductor substrate.

Step 802: Form an inductor over the semiconductor substrate.

Step 804 : Form a redistributed metal layer with a specific pattern on the inductor to form a patterned ground shield.

Please note that the above-mentioned embodiments are only used as illustrations of the present invention, and are not limitations of the present invention. For example, the steps of the manufacturing method of the integrated inductor structure of the present invention may further include: grounding the patterned ground shield. Preferably, the pattern of the redistribution metal layer is substantially above and perpendicular to the inductor.

Please refer to FIG. 14 , which is a schematic cross-sectional view of an integrated inductor structure 900 according to a fifth embodiment of the present invention. As shown in FIG. 14 , the integrated inductor structure 900 includes: a semiconductor substrate 902, a plurality of through silicon vias (Through Silicon Via, TSV) 904, an inductor 906, and a back side redistribution layer (back side redistribution layer, back side RDL) 910. An inductor 906 is formed above the semiconductor substrate 902 , and the plurality of TSVs 904 are formed in the semiconductor substrate 902 . The backside redistribution metal layer 910 is formed on the bottom of the semiconductor substrate 902 and connected to the plurality of TSVs 904, and the backside redistribution metal layer 910 has a specific pattern (for example, as shown in FIG. 15, FIG. 15 is A bottom plan view of the integrated inductor structure 900, but the present invention is not limited thereto) to form a patterned ground shield (Patterned Ground Shield, PGS) 908, wherein the material of the rear redistribution metal layer 904 can be aluminum. Please note that in the present invention, there may not be any redundant patterned ground protection between the inductor 906 and the semiconductor substrate 902 . In addition, the integrated inductor structure 900 of the present invention can be applied to a silicon interposer (SiInterposer) in a three-dimensional chip (3D IC). Please refer to FIG. 16, which shows the integration according to the fifth embodiment of the present invention A simplified schematic diagram of the inductance structure 900 applied to a three-dimensional chip 920. As shown in FIG. , and the patterned ground protection 908 formed by the lower backside redistribution metal layer 910 in the integrated inductor structure 900 can not only reduce the electromagnetic eddy current and improve the quality factor (Q-factor), but also can more effectively avoid the silicon plug 940 The current of the inductor magnetic field affects the signal of a second chip 950 on the lower layer. Please note that the above-mentioned embodiment is only used as an illustration of the present invention, and is not a limitation of the present invention. For example, the patterned grounding shield 908 can also be additionally grounded to further reduce electromagnetic eddy current (eddy current) and improve the quality factor (Q-factor).

Please refer to FIG. 17 . What FIG. 17 depicts is a flow chart of a fifth embodiment of the integrated inductance structure manufacturing method of the present invention based on the above-mentioned integrated inductance structure 900. If the same result can be obtained substantially, the process flow The steps in FIG. 17 do not necessarily need to be executed in the order shown in FIG. 17 , nor do they need to be continuous, that is, other steps can be inserted between these steps. The fifth embodiment of the method for manufacturing an integrated inductor structure of the present invention includes the following steps:

Step 1000: Form a semiconductor substrate.

Step 1002: Form a plurality of TSVs in the semiconductor substrate.

Step 1004: Form an inductor over the semiconductor substrate.

Step 1006 : forming a backside redistribution metal layer with a specific pattern on the bottom of the semiconductor substrate, and connecting the backside redistribution metal layer to the plurality of TSVs to form a patterned ground shield.

Please note that the above-mentioned embodiments are only used as illustrations of the present invention, and are not limitations of the present invention. For example, the steps of the manufacturing method of the integrated inductor structure of the present invention may further include: grounding the patterned ground shield.

In addition, the integrated inductor structure of the present invention can be applied to a silicon interposer (Si Interposer) in a three-dimensional chip (3D IC). Please refer to FIG. 18, which shows the integrated inductor according to the foregoing embodiment of the present invention. The structure is applied to a simplified schematic diagram of a three-dimensional chip 1120. As shown in FIG. The inductor structure has a TSV and a rear redistribution metal layer or redistribution metal layer.

In summary, compared with the prior art, the integrated inductance structure and the manufacturing method of the integrated inductance structure disclosed in the present invention have innovative patterned ground protection, which can block the formation of deep electromagnetic eddy currents in the semiconductor substrate, and can block The path where the electromagnetic eddy current may occur, the blocking effect is more thorough, and the quality factor is improved, and it can be applied to 3D chip or flip chip technology.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the patent claims of the present invention shall fall within the scope of the present invention.

Claims (13)

1. An integrated inductor structure, comprising: a semiconductor substrate; A plurality of TSVs are formed in the semiconductor substrate and arranged in a specific pattern, and the TSVs are filled with a metal material to form a patterned ground shield; and An inductor is formed above the semiconductor substrate. 2. The integrated inductor structure as claimed in claim 1, further comprising: A masking metal layer pattern is formed on the semiconductor substrate to connect the plurality of TSVs according to the specific pattern to jointly form the patterned ground protection. 3. The integrated inductor structure of claim 2, wherein the masking metal layer pattern is substantially orthogonal to the inductor below the inductor. 4. The integrated inductor structure as claimed in claim 1, wherein the patterned ground shield is grounded. 5. The integrated inductor structure as claimed in claim 1, wherein the TSV has a width less than 20 microns. 6. The integrated inductor structure as claimed in claim 1, which is applied to a silicon interposer in a three-dimensional chip. 7. The integrated inductor structure as claimed in claim 1, wherein the metal material is copper, aluminum or gold. 8. The integrated inductor structure as claimed in claim 1, further comprising: A backside redistribution metal layer pattern is formed under the semiconductor substrate to connect the plurality of TSVs according to the specific pattern to jointly form the patterned ground protection. 9. The integrated inductor structure of claim 8, wherein the backside redistribution metal layer pattern is substantially orthogonal to the inductor below the inductor. 10. A manufacturing method for an integrated inductor structure, comprising: forming a semiconductor substrate; forming a plurality of through-silicon vias in the semiconductor substrate, and arranging the plurality of through-silicon vias in a specific pattern; filling a metal material in the TSV to form a patterned ground shield; and An inductor is formed above the semiconductor substrate. 11. The manufacturing method of an integrated inductor structure as claimed in claim 10, further comprising: A shielding metal layer pattern is connected to the plurality of TSVs according to the specific pattern to jointly form the patterned ground protection, wherein the shielding metal layer pattern is formed on the semiconductor substrate. 12. The method of fabricating an integrated inductor structure as claimed in claim 11, wherein the masking metal layer pattern is substantially perpendicular to the inductor below the inductor. 13. The manufacturing method of an integrated inductor structure as claimed in claim 10, further comprising: A backside redistribution metal layer pattern is connected to the plurality of TSVs according to the specific pattern to jointly form the patterned ground protection, and the backside redistribution metal layer pattern is formed under the semiconductor substrate.