CN104078361B - Method for manufacturing MOS transistor - Google Patents

Abstract

A method for manufacturing a MOS transistor, comprising: providing a semiconductor substrate; forming a plurality of gate structures on the semiconductor substrate; forming first sidewalls on both sides of the gate structures; using the first sidewalls as a mask to Perform ion implantation on the semiconductor substrate to form a source-drain ion implantation region; remove the first sidewall; form a second sidewall layer on the semiconductor substrate and around the gate structure and on the upper surface; perform isotropic etching for the second The side wall layer is formed as a second side wall on both sides of the gate structure, the second side wall is a triangle with a narrow top and a wide bottom, and the bottom width of the second side wall is greater than the bottom width of the first side wall; An interlayer dielectric layer is deposited on the semiconductor substrate, the second sidewall and the gate structure, and the upper surface of the interlayer dielectric layer is flush with the gate structure. The second sidewall makes the opening formed by the second sidewall between adjacent gate structures and the semiconductor substrate into an open shape with a wide top and a narrow bottom, which is convenient for filling the dielectric layer.

Description

MOS transistor manufacturing method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a MOS transistor.

Background technique

In the CMOS large-scale integrated circuit process, the source and drain of the MOS transistor are generally formed by a self-aligned process. In the Chinese patent application document with the publication number CN102569087A, a method for forming source and drain electrodes using a self-alignment process is disclosed.

The specific process is shown in Figure 1 to Figure 4:

Referring to FIG. 1 , a semiconductor substrate 10 is provided, and several gate structures are formed on the semiconductor substrate 10 , here, adjacent gate structures 21 and 22 are taken as examples. A spacer layer 30 is formed on the surface of the semiconductor substrate 10 and the surfaces of the gate structures 21 and 22 .

Referring to FIG. 2 , the sidewall layer 30 is etched by plasma dry etching to form sidewalls 31 on both sides of the gate structure 21 and the gate structure 22 . Meanwhile, the spacer 31 between the adjacent gate structures 21 , 22 and the semiconductor substrate 10 form the opening 7 .

Referring to FIG. 3 , using the gate structures 21, 22 and sidewalls 31 as masks, ion implantation is performed on the semiconductor substrate 10, and source-drain ion implantation is formed in the semiconductor substrate 10 on both sides of the gate structures 21, 22. District 9.

Referring to FIG. 4 , an interlayer dielectric layer 50 is deposited between the semiconductor substrate 10 and the gate structures 21 , 22 . However, as the CMOS large-scale integrated circuit technology develops toward the direction of smaller and smaller feature sizes, the distance between adjacent gate structures 21 and 22 is also reduced, and the aspect ratio of the corresponding opening 7 is also increased. The deposition of the interlayer dielectric layer 50 in the opening 7 tends to be uneven and even have voids.

Contents of the invention

The problem to be solved by the present invention is to provide a method for manufacturing a MOS transistor, so as to solve the problem that the sidewalls between adjacent gate structures and the aspect ratio of openings formed between the semiconductor substrates become larger as the feature size decreases. Filling the interlayer dielectric layer between the adjacent gate structures and the semiconductor substrate has the problem of uneven filling and even voids.

In order to solve the above problems, the present invention provides a method for manufacturing a MOS transistor,

Provide semiconductor substrates;

forming a plurality of gate structures on the semiconductor substrate;

forming first spacers on both sides of the gate structure;

Using the first sidewall as a mask, performing ion implantation on the semiconductor substrate to form a source-drain ion implantation region;

remove the first side wall;

forming a second spacer layer on the semiconductor substrate, and the second spacer layer covers the gate structure;

The second sidewall layer is etched by an isotropic etching method to form second sidewalls on both sides of the gate structure, the second sidewalls are right-angled triangles, and the width of the bottom of the second sidewalls is greater than the bottom width of the first side wall;

An interlayer dielectric layer is deposited on the semiconductor substrate, the second sidewall and the gate structure.

Optionally, in the isotropic etching process, the etchant used is a mixed gas of CHF ₃ , CH ₂ F ₂ , CH ₃ F and O ₂ , wherein the flow rate of CHF ₃ is 10-500 sccm , the flow rate of CH ₂ F ₂ is 10-500 sccm, the flow rate of CH ₃ F is 10-500 sccm, the flow rate of O ₂ is 10-500 sccm, and the etching time is 10 secs-600 secs.

Optionally, in the isotropic etching process, the pressure in the etching chamber is set to 10-100 mTorr, the source power is 100-1000 W, and the bias power is 100-500 W.

Optionally, the material of the second sidewall material layer is silicon nitride.

Optionally, one right-angled side of the right-angled triangle coincides with the upper surface of the semiconductor substrate, and the other right-angled side coincides with the side of the gate structure.

Optionally, the bottom angle of the second side wall ranges from 30° to 60°.

Optionally, the height of the second sidewall is lower than that of the gate structure.

Optionally, the height of the second sidewall is lower than half of the gate structure.

Optionally, after forming the second spacer and before depositing the interlayer dielectric layer, a step is further included: forming a stress layer on the surface of the semiconductor substrate and the gate structure.

Optionally, after forming the interlayer dielectric layer, it further includes: forming a contact hole in the interlayer dielectric layer on the source-drain ion implantation region, and the right-angled side of the second sidewall coincident with the semiconductor substrate and the contact The edges of the holes are not touching.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The second side wall is a right triangle, and the bottom width of the second side wall is larger than the bottom width of the first side wall. Since the bottom of the second sidewall is wider, it can fill the bottom corners of the gap between adjacent gate structures, which solves the problem that the bottom corners of the gap between adjacent gate structures are not easily filled by the interlayer dielectric layer. Therefore, there will be a problem of voids; and the second side wall also has an obviously inclined outer surface, so that the opening formed by the second side wall and the semiconductor substrate is an open shape with a wide top and a narrow bottom. The bottom of the opening with such a shape needs to be filled with fewer interlayer dielectric layers, and it is not easy for the top of the opening to be sealed when the bottom of the opening is not fully filled.

Further, the process arrangement of removing the first sidewall and then re-forming the second sidewall makes it possible to ignore the need for subsequent filling of the interlayer dielectric layer when forming the first sidewall, and only need to adapt to the source-drain ion implantation process. Need to form a thinner first sidewall; after the source-drain ion implantation, before forming the second sidewall layer, remove the first sidewall, which can eliminate the thickness of the first sidewall and reduce the gap between adjacent gate structures. Influenced by the spacing, avoiding the first sidewall from increasing the aspect ratio of the gap between the gate structures; when forming the second sidewall, since the ion implantation has been completed, it can be formed without the limitation of the ion implantation on the thickness of the sidewall. The second sidewall whose bottom is thicker than the first sidewall ensures that the opening formed by the second sidewall and the semiconductor substrate is conveniently filled into the interlayer dielectric layer.

Further, when the bottom angle of the second sidewall is 30°-60°, the inclination of the outer surface of the second sidewall is more appropriate, neither tends to be steep, nor tends to be horizontal. The change of the shape of the gap between them is relatively obvious, so that the opening formed between the second sidewall between the adjacent gate structures and the semiconductor substrate is convenient for filling. Further, the height of the second sidewall is lower than that of the gate structure, and the transistor formed by depositing a stress layer on the surface of the semiconductor substrate, the second sidewall, and the gate structure is similar to the application of general dual stress liners (Dual stress liners, Compared with the MOS transistor formed by DSL) technology, the stress layer formed in it is closer to the channel, which can better apply stress to the channel, and can greatly improve the mobility of MOS transistor channel carriers. This technique of forming a stress layer in a MOS transistor is exactly a stress proximity technique (Stressproximity technique, SPT).

Description of drawings

1 to 4 are schematic diagrams of processes for forming MOS transistors in the prior art;

5 to 10 are schematic diagrams of the process of forming a MOS transistor in Embodiment 1 of the present invention;

11 to 12 are schematic diagrams of the process of forming a MOS transistor in Embodiment 2 of the present invention.

detailed description

In the existing process, the sidewalls on both sides of the gate are mainly used as masks for the subsequent source-drain ion implantation, which will be very thin, and the width of the bottom is generally And the side wall is generally flush with the gate structure, and the height is The outer side of the sidewall with such a shape is almost perpendicular to the semiconductor substrate, and correspondingly, the bottom angle of the opening formed by the sidewall between adjacent gate structures is almost at right angles to the semiconductor substrate. In the case that the aspect ratio of the opening is large, it is difficult to fill the opening with the interlayer dielectric layer to the bottom corner of the opening, so that a void appears at the bottom corner of the opening; and when filling the opening into the interlayer In the case of a dielectric layer, molecules of the interlayer dielectric layer tend to gather at the steps on both sides of the top of the opening to form protrusions. When the lower portion of the opening is not filled, the protrusions on both sides of the top of the opening have been connected together, sealing the surface of the opening, hindering the continuous filling of the interlayer dielectric layer, thereby causing voids in the opening.

Therefore, the technical solution of the present invention provides a method for manufacturing a MOS transistor, comprising: after forming the gate structure and the first sidewall, performing ion implantation using the gate structure and the first sidewall as a mask to form source-drain ion implantation area, and then remove the first sidewall layer to form a second sidewall layer, and then use isotropic etching to form the second sidewall layer into a second sidewall layer. The second side wall is a right-angled triangle with a narrow top and a wide bottom, and the bottom width of the second side wall is much larger than the bottom width of the first side wall. Such a shape of the second side wall will fill in the adjacent The bottom corner of the gap formed by the gate structure, and the opening formed by the second side wall between adjacent gate structures and the semiconductor substrate is an open shape with a wide top and a narrow bottom, which is convenient for filling the dielectric layer.

In the technical solution of the present invention, the height of the second sidewall is lower than the gate structure, and a stress layer is subsequently deposited on the semiconductor substrate, the second sidewall and the gate structure, and the stress layer can directly contact the grid structure. Compared with the MOS transistor with a stress layer formed by the general application of dual stress liners (DSL) technology, the stress layer in the MOS transistor formed by the technical solution of the present invention is closer to the channel, and can better apply stress to the channel. The channel can greatly improve the mobility of carriers in the channel of the MOS transistor. The stress technique adopted by the technical solution of the present invention is called stress proximity technique (Stress proximity technique, SPT).

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment one

The process of forming the MOS transistor with the second sidewall of the right triangle in the first embodiment will be described in detail below with reference to FIG. 5 to FIG. 10 .

As shown in FIG. 5 , a semiconductor substrate 100 is provided, several gate structures are formed on the semiconductor substrate 100 , and a first spacer layer 300 is formed on the surface of the semiconductor substrate 100 and the gate structures. Wherein, FIG. 5 only shows two adjacent gate structures 210 and 220 for illustration.

In this embodiment, the gate structures 210 and 220 include a gate insulating layer and a gate electrode layer (not shown) on the gate insulating layer. Wherein, the gate insulating layer is silicon oxide, and the gate material layer is polysilicon.

In this embodiment, the process of forming the gate structure 210 and the gate structure 220 is: forming a gate insulating layer on the semiconductor substrate by using a deposition process or a thermal oxidation process; then forming a gate electrode layer on the gate insulating layer by using a deposition process; A photoresist layer is formed on the gate electrode layer, and the photoresist layer has a gate electrode pattern; using the photoresist layer as a mask, the gate insulating layer and the polysilicon layer are selectively etched to form a gate structure 210 and 220.

In this embodiment, the material of the first sidewall layer 300 is silicon nitride, which is formed by a deposition process. In other implementation manners, the first sidewall layer 300 may also be a composite layer structure of a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

As shown in FIG. 6, an anisotropic etching process is used to remove the top of the gate structures 210, 220 and the first sidewall layer 300 on the semiconductor substrate 100 to form a The first side wall 310 of. The first spacer 310 between the gate structures 210 and 220 and the semiconductor substrate 100 form the first opening 17 .

Specifically, in this embodiment, the etching mainly includes two steps:

First, the first etching is performed on the first sidewall layer 300, the etching gas used in the first etching is a mixed gas of CF ₄ , CHF ₃ , O ₂ and Ar, CF ₄ , CHF ₃ , O ₂ The volume ratio of V(CF ₄ ):V(CHF ₃ ):V(O ₂ ):V(Ar) to Ar is 40:80:30:250. In the first etching, the semiconductor substrate 100 and the first spacer layer 300 on top of the gate structures 210 and 210 are mainly etched. Generally, the first etching leaves a small amount of the first spacer layer 300 on top of the semiconductor substrate 100 and the gate structures 210 , 220 .

Next, a second etching is performed on the first sidewall layer 300. In the second etching, the etching rate of the etching gas for the first sidewall layer 300 is lower than that of the etching gas for the first sidewall layer 300 in the first etching. The etch rate of the sidewall layer 300. The etching gas used is CH ₃ F, O ₂ and Ar, wherein the volume ratio V(CH ₃ F):V(O ₂ ):V(Ar) of CH ₃ F, O ₂ and Ar is 20:80 :100. In the second etching, on the one hand, the remaining first sidewall layer 300 on the top of the semiconductor substrate 100 and the gate structure 210, 220 is removed; The side wall layer 300 is to a predetermined size. After the second etching, the first sidewall layer 300 is formed into a first sidewall 310 .

As shown in FIG. 7 , the semiconductor substrate 100 is implanted with ions using the gate structures 210 , 220 and the first sidewall layer 310 as a mask to form the source-drain doped region 19 of the MOS transistor in the semiconductor substrate 100 .

As shown in FIG. 8 , the first spacer 310 is removed, and then the second sidewall layer 400 is formed on the surfaces of the semiconductor substrate 100 , the first spacer 310 and the gate structures 210 , 220 .

In this embodiment, the process of removing the first sidewall 310 is wet etching, which can be performed by using hot phosphoric acid.

In this step, the first sidewall 310 is removed, and the influence of the thickness of the first sidewall 310 on reducing the distance between the gate structures 210 and 220 can be eliminated, which can prevent the first sidewall 310 from increasing the gate structure 210, The aspect ratio of the gap between 220.

In this embodiment, the thickness of the second sidewall layer 400 is much greater than the thickness of the first sidewall layer 300, and its specific thickness is 1/3 to 1/2 of the distance between adjacent gate structures 210 and 220 , usually

In this embodiment, the material of the second sidewall layer 400 is silicon nitride. The way of formation is plasma enhanced chemical vapor deposition. The gas sources used during deposition are SiH ₄ , NH ₃ and N ₂ . Wherein, the flow rate of SiH ₄ is 100 sccm, the flow rate of NH ₃ is 100 sccm, and the flow rate of N ₂ is 30 sccm. The pressure is set to 50Pa, the power is set to 20W, and the temperature is set to 200°C to 350°C.

As shown in FIG. 9 , isotropic etching is used to remove the tops of the gate structures 210 , 220 and the second spacer layer 400 on the semiconductor substrate 100 to form the second spacer 410 . The second side wall 410 is a triangle with a narrow top and a wide bottom, and its bottom width is greater than that of the first side wall 310 in FIGS. 6 to 7 . The second spacer 410 between the gate structures 210 and 220 and the semiconductor substrate 100 form the second opening 18 .

In this embodiment, in the isotropic etching, the etchant used is a mixed gas of CHF ₃ , CH ₂ F ₂ , CH ₃ F and O ₂ , wherein the flow rate of CHF ₃ is 10-500 sccm, CH The flow rate of ₂ F ₂ is 10-500 sccm, the flow rate of CH ₃ F is 10-500 sccm, and the flow rate of O ₂ is 10-500 sccm. During the etching process, the pressure in the etching chamber is set to 10mTorr-100mTorr, the source power is 100W-1000W, and the bias power is 100W-500W. Among them, the source power is used to generate and maintain the plasma, and the bias power is used to control the etching rate.

The time for the isotropic etching is specifically determined by the required width of the second sidewall 410 . In this embodiment, the etching time of the isotropic etching is: 10 secs-600 secs.

After isotropic etching, the formed second sidewall 410 has an obviously inclined outer surface, forming a right triangle on both sides of the gate structure 210, 220, one right angle side of the right triangle coincides with the upper surface of the semiconductor substrate, The other right-angle side coincides with the side of the gate structure. The shape of the second side wall 410 makes the second opening 18 an open shape with a wide top and a narrow bottom.

The wider the width of the bottom of the second sidewall 410 is, the more the corners at the bottom of the gap between adjacent gate structures are filled, and the problem of insufficient filling is less likely to occur; but the second sidewall 410 also It should not be too wide. Because in the subsequent process, it is necessary to fill the second opening 18 with an interlayer dielectric layer material, and then use an etching process to etch the interlayer dielectric layer to form a contact hole on the source-drain doped region 19 . The material of the second side wall 410 is silicon nitride, and the material of the interlayer dielectric layer is generally silicon oxide, and the materials of the two are different. If the second sidewall 410 exceeds the edge of the contact hole to be formed, the second sidewall 410 will block the etching of the bottom of the contact hole when the interlayer dielectric layer is etched by an etching process to form a contact hole. . Therefore, the right-angled side of the second sidewall 410 coincident with the upper surface of the semiconductor substrate 100 does not touch the edge of the contact hole to be formed later.

After several tests, when the bottom angle a formed by the outer surface of the second sidewall 410 and the upper surface of the semiconductor substrate 100 ranges from 30° to 60°, the inclination of the outer surface of the second sidewall is more appropriate. , neither tends to be steep, nor tends to be horizontal, and the shape change of the gap between adjacent gate structures is relatively obvious, so that the second opening 18 is easy to fill. When the base angle a is 45°, the second opening 18 is most convenient to fill.

As shown in FIG. 10 , an interlayer dielectric layer 600 is formed on the surface of the semiconductor substrate 100 , the gate structures 210 , 220 and the second spacer 410 .

In this embodiment, the interlayer dielectric layer 600 is made of silicon oxide and formed by chemical vapor deposition.

The bottom of the second sidewall 410 is wider and can fill the corners at the bottom of the gap between adjacent gate structures, thereby avoiding the gap at the bottom of the gap when filling the gap between adjacent gate structures with the interlayer dielectric layer. The corners are not easily filled to form a cavity; and the second side wall 410 also has a significantly inclined outer surface, which can improve the shape of the first opening 17 in FIG. 6 , so that in FIG. 10 the second side wall 410 and The second opening 18 formed by the semiconductor substrate 100 has an open shape with a wide top and a narrow bottom. The bottom of the second opening 18 with such a shape requires less interlayer dielectric layer 600 to be filled, and the problem that the top of the second opening 18 is sealed before the bottom of the second opening 18 is not filled is not easy to occur.

In this step, the interlayer dielectric layer 600 filled in the second opening 18 has good uniformity without voids.

Moreover, in this embodiment, the process arrangement of removing the first sidewall 310 and then re-forming the second sidewall 410 makes it possible to ignore the need for subsequent filling of the interlayer dielectric layer 600 when forming the first sidewall 310, and only need to To adapt to the requirements of the source-drain ion implantation process, a thinner first sidewall 310 is formed; after the source-drain ion implantation and before forming the second sidewall layer 300, the first sidewall 310 can be removed to eliminate the first sidewall 310 The influence of the thickness of the thickness on reducing the spacing between the gate structures 210, 220, avoiding the first spacer 310 from increasing the aspect ratio of the gap between the gate structures; when forming the second spacer 410, since the ion implantation has been completed , the second sidewall 410 with a thicker bottom can be formed without being limited by the thinner sidewall required by ion implantation, and the shape of the second sidewall 410 can be ensured so that the second opening 18 can be easily filled into the interlayer dielectric layer 600 .

Embodiment two

In this embodiment, a stress layer needs to be formed on the semiconductor substrate 100 and the gate structures 210 , 220 . The situation of Embodiment 2 will be described in detail below with reference to FIGS. 11 to 12 .

Generally, the technology of forming stress layers of different stress types on different types of MOS transistors is a dual stress layer (Dual stress liners, DSL) technology. DSL technology can apply stress to the channel of MOS transistors, thereby causing lattice strain, improving the mobility of carriers (electrons or holes), and ensuring that integrated circuits can maintain better performance at lower operating voltages. To meet the development trend that the operating voltage of integrated circuits is continuously reduced with the continuous reduction of process feature size.

Another stress technology based on DSL is: after removing the top part of the sidewall on both sides of the gate and then depositing a stress layer, this stress technology is called stress proximity technique (SPT). Compared with the general DSL technology, the stress layer in SPT can directly contact the gate structure, and the stress layer will be closer to the channel, which can better apply stress to the channel, and can greatly improve the channel carrier of MOS transistors. the mobility.

As shown in FIG. 11 , after forming the second spacer 410 and before filling the interlayer dielectric layer 600 , a stress layer 500 is formed on the surfaces of the semiconductor substrate 100 , the second spacer 410 and the gate structures 210 , 220 .

In this embodiment, the material of the stress layer 500 is silicon nitride, and the type of stress is determined by the type of transistor where the gate structure 210 or the gate structure 220 is located. Generally, the stress layer 500 formed on the NMOS transistor is a tensile stress layer, and the stress layer 500 formed on the PMOS transistor is a compressive stress layer. The stress type of the stress layer 500 is determined by the specific process conditions for depositing silicon nitride.

In this embodiment, the second side wall 410 needs to meet the requirements for the bottom angle a and the bottom width of the second side wall 410 similar to those in the first embodiment. When these requirements are met, the height of the second sidewall 410 will be lower than the height of the gate structures 210 , 220 . And generally, the height of the second sidewall 410 will not exceed half of the height of the gate structures 210 and 220 .

In this case, after the stress layer 500 is formed, it can directly contact the gate structure, can apply stress to the channel well, and can greatly improve the mobility of carriers in the channel of the MOS transistor.

In the process for manufacturing MOS transistors provided in this embodiment, the stress proximity technique (SPT) can be applied without adding a special process to remove the upper part of the sidewall as in the process of general MOS transistors.

As shown in FIG. 12 , an interlayer dielectric layer 600 is formed on the surface of the stress layer 500 .

In this embodiment, the material of the interlayer dielectric layer 600 is silicon oxide. The process of forming the interlayer dielectric layer 600 is to deposit a silicon oxide layer, and then use chemical mechanical polishing to smooth the surface of the silicon oxide layer.

The surface topography of the stress layer 500 is determined by the surface profile jointly formed by the gate structures 210 , 220 , the second sidewall 410 and the semiconductor substrate 100 . Due to the relatively large inclination of the outer surface of the second side wall 410, in this embodiment, the interior of the opening 16 formed by the stress layer 500 between the adjacent gate structures 210 and 220 is still an open shape that is wide at the top and narrow at the bottom. , to facilitate the filling of the dielectric layer in the subsequent process. In this step, the formed interlayer dielectric layer 600 has good uniformity and no voids.

However, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. a kind of manufacture method of MOS transistor, it is characterised in that include：

Semiconductor substrate is provided；

Multiple grid structures are formed on the semiconductor substrate；

The first side wall is formed in the both sides of the grid structure；

Using the first side wall as mask, ion implanting is carried out to the Semiconductor substrate, form source and drain ion implanted region；

Remove the first side wall；

The second side wall layer is formed on the semiconductor substrate, and second side wall layer covers grid structure, second side Wall layers are different from interlayer dielectric layer material to be deposited；

Second side wall layer is etched using isotropic etching method, in the both sides of grid structure the second side wall is formed, described the Two side walls are right angled triangle, and the bottom width of second side wall is more than the bottom width of first side wall；

The interlayer dielectric layer on the Semiconductor substrate, the second side wall and grid structure.

2. manufacture method as claimed in claim 1, it is characterised in that in the technique of the isotropic etching, adopted Etching agent be CHF₃、CH₂F₂、CH₃F and O₂Mixed gas, wherein CHF₃Flow be 10-500sccm, CH₂F₂Flow be 10-500sccm, CH₃The flow of F is 10-500sccm, O₂Flow be 10-500sccm, etch period is 10secs- 600secs。

3. manufacture method as claimed in claim 2, it is characterised in that in the technique of the isotropic etching, arranges and carves Erosion within the chamber pressure is 10-100mTorr, and source power is 100-1000W, and bias power is 100-500W.

4. manufacture method as claimed in claim 1, it is characterised in that the material of the second spacer material layer is silicon nitride.

5. manufacture method as claimed in claim 1 a, it is characterised in that right-angle side of the right angled triangle and semiconductor Substrate top surface overlaps, and another right-angle side overlaps with grid structure side.

6. manufacture method as claimed in claim 5, it is characterised in that the second side wall base angle scope is 30 °~60 °.

7. manufacture method as claimed in claim 1, it is characterised in that the height of second side wall is tied less than the grid Structure.

8. manufacture method as claimed in claim 7, it is characterised in that the height of second side wall is less than the grid structure Half.

9. manufacture method as claimed in claim 1, it is characterised in that after forming the second side wall, before interlayer dielectric layer, Also include step：Stressor layers are formed on the surface of the Semiconductor substrate and grid structure.

10. manufacture method as claimed in claim 5, it is characterised in that after interlayer dielectric layer is formed, also include：Institute State and formed in the interlayer dielectric layer on source and drain ion implanted region contact hole, the right angle that second side wall overlaps with Semiconductor substrate Side and the edge noncontact of contact hole.