CN104064618A - A kind of p-i-n structure CdTe battery and its preparation method - Google Patents

Abstract

A pin structure CdTe solar cell, its structure from bottom to top is: substrate, transparent conductive electrode layer, CdS n-type semiconductor layer, CdTe intrinsic light absorption layer, wide bandgap ternary II-VI semiconductor p ⁺ layer, ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer, metal electrode layer. The CdTe solar cell of the present invention is prepared by low-temperature magnetron sputtering.

Description

A kind of p-i-n structure CdTe battery and its preparation method

technical field

The invention relates to a CdTe solar cell and a preparation method thereof.

Background technique

As a clean energy, solar energy is rich, easy to obtain, renewable and non-polluting. The effective use of solar energy, especially the effective use of photovoltaic solar cells, is expected to solve global energy shortages, environmental pollution, and climate warming. And other issues. If solar cells are to replace traditional energy sources, costs must be reduced. Thin-film solar cells have the advantages of less material consumption, low cost, and easy large-scale production, and have become a key research and development and production cell for the solar photovoltaic industry. Among the thin-film solar cells, the ones that have reached industrial scale production are mainly amorphous silicon (a-Si), copper indium gallium selenide (CIGS) and cadmium telluride (CdTe) solar cells. CdTe solar cells are currently one of the most promising, high-efficiency, and low-cost photovoltaic technologies for thin-film solar cells. The production cost of CdTe modules is US$0.55/W, which is the lowest production cost among known large-scale application photovoltaic technologies. The highest efficiency of CdTe commercial modules of First Solar in the United States is 17.0%, and the highest energy conversion efficiency of laboratory small-area CdTe cells is 20.4%, which is still far behind the theoretical efficiency of single-junction CdTe (28-29%) . It can be seen that there is still room for improvement in the conversion efficiency of CdTe batteries, and the potential for technological development is still great. CdTe is a II ^B -VI ^A binary compound, a direct bandgap semiconductor material, with room temperature direct bandgap width Eg=1.5eV, high optical absorption coefficient (visible light range>5×10 ⁵ cm ^-1 , 2μm thick CdTe film can absorb more than 99% of the incident light at 600nm), high stability, low power temperature coefficient (~-0.21%/℃), good weak light characteristics, no intrinsic photoinduced Excellent properties such as attenuation effect and environmental friendliness. In the entire life cycle, including raw material extraction, purification, component preparation, component use, component treatment, and component recycling, the cadmium emission of CdTe solar cells is only 0.3646g/GWh, which is far lower than the 4.900g/GWh of coal power. GWh.

According to the current average level of conversion efficiency of large-area modules, every 1% increase in conversion efficiency is equivalent to a 10% reduction in production costs on the existing basis, and it is expected that CdTe cells will first become photovoltaics that can compete with traditional electricity costs. technology to promote the large-scale application of photovoltaic clean energy. Therefore, improving the conversion efficiency of CdTe photovoltaic devices not only has important scientific significance, but also has direct economic benefits, and will win my country's leading position in the field of compound semiconductor thin-film photovoltaic technology. At present, many scientific research units such as the Institute of Electrical Engineering, Chinese Academy of Sciences have launched research on CdTe thin-film solar cells. Since the Institute of Electrical Engineering of the Chinese Academy of Sciences launched the magnetron sputtering method to prepare CdTe thin film batteries in 2010, it has achieved a conversion efficiency of 14.26% on 2 μm thick CdTe polycrystalline thin film batteries.

At present, the main research purpose of CdTe battery device is to improve its conversion efficiency. To improve its conversion efficiency, the open circuit voltage (Voc) of CdTe battery must be increased, because the open circuit voltage is a key factor determining the conversion efficiency. The band gap of CdTe is 1.50eV, and the band gap of GaAs is 1.47eV, which are almost the same. However, the open circuit voltage of CdTe polycrystalline thin film battery is nearly 230mV lower than that of GaAs polycrystalline thin film battery. Low open circuit voltage reduces the conversion efficiency of CdTe polycrystalline thin film solar cells. The low open circuit voltage is mainly due to the low carrier lifetime (close to 1ns), low hole concentration (close to 10 ¹⁴ cm ^-3 ) and back contact barrier of CdTe.

Due to the self-compensation effect of CdTe, it is difficult to obtain highly doped p-type CdTe (usually the hole concentration of copper-doped CdTe thin film cells is only ~10 ¹⁴ -10 ¹⁵ cm ^-3 , close to the intrinsic state). The p-type doping of CdTe is often achieved by diffusing impurities such as Cu and Sb from the back contact layer to the inside of CdTe. Metal Cu is usually used, but metal Cu often causes battery stability problems. Metal is deposited on the surface of CdTe as a current collector. Since the work function of CdTe is as high as 4.86eV, there are very few metals that form a good ohmic contact with it. Therefore, the commonly used back contact layer tends to form a Schottky barrier opposite to the CdS/CdTe junction, reducing the open circuit voltage of the cell. The theoretical open-circuit voltage of CdTe solar cells can reach 1.2V, but currently its highest open-circuit voltage is only over 900mV, which is still far from the theoretical open-circuit voltage. Therefore, it is necessary to increase the open circuit voltage of CdTe polycrystalline thin film cells.

In 2006, James Sites, Jun Pan [Strategies to increase CdTe solar-cell voltage, Thin Solid Films2007, 515, 6099-6102] proposed that the open circuit voltage of CdTe can be increased by two methods: one is to increase the carrier concentration of CdTe and Another method is to add an electronic reflective layer to the back contact. To increase the carrier concentration and lifetime of CdTe needs to start with materials, so the technical route to improve the Voc of CdTe batteries is often to conduct in-depth research on the absorber layer materials to obtain p-type CdTe with high doping concentration. The open-circuit voltage of battery devices can be increased by starting with CdTe polycrystalline materials and increasing the CdTe carrier concentration and lifespan. Increasing the carrier life can increase the open circuit voltage and fill factor. The fill factor of CdTe battery devices with large carrier life is close to that of GaAs batteries, and the diode quality factor is equivalent, but the open circuit voltage is subject to the separation of quasi-Fermi levels. Increasing the carrier concentration has limitations in increasing the open circuit voltage. Therefore, the open-circuit voltage cannot be raised to a very high value only by the improvement of the carrier lifetime. On the other hand, the open circuit voltage can be increased by increasing the carrier density, but increasing the carrier concentration will reduce the width of the space charge region, and the reduced space charge region width requires a large diffusion length and a high carrier lifetime in order to be able to Reasonable collection of photogenerated carriers. Simultaneously increasing carrier density and carrier lifetime requires decreasing recombination centers. However, in CdTe battery devices, interfacial recombination is unavoidable due to defects at the interface between CdS and CdTe. It can be seen that it is difficult to improve the open circuit voltage of CdTe battery from the perspective of materials alone, and it is not easy to realize.

At present, the traditional CdTe solar cell structure is a p-n junction structure, as shown in Figure 1, the traditional CdTe solar cell has a substrate, a transparent conductive electrode layer, a CdS n-type semiconductor layer, a CdTe light absorbing layer, and is also a p layer. metal electrode layer. When the traditional p-n junction structure CdTe solar cell works, light enters the CdTe light absorbing layer from the side of the CdS semiconductor layer. CdS is an n-type semiconductor, and CdTe is a p-type semiconductor. The minority carrier lifetime in polycrystalline CdTe thin film is short (τ<10ns), so that the thickness of the CdTe semiconductor layer of the traditional p-n junction structure CdTe polycrystalline thin film battery is usually 2-10 μm, which is dozens of times the thickness of the n-type CdS semiconductor layer. And because the p-type of the CdTe semiconductor layer in the battery is very weak, usually the space charge region can extend to 3-4 μm, so that the region where the photogenerated carriers are generated is in the depletion region. That is to say, the collection of photogenerated carriers in CdTe is achieved by electric field drift rather than diffusion.

On the other hand, tellurium Te is one of the least abundant elements in the earth's crust, which is another bottleneck restricting the rapid development of CdTe solar cells. At present, the supply of tellurium is almost entirely extracted from the by-products of the copper ore and lead ore refining process. In 2008, the total global Te production was only 480 tons. tons/year or so. Various analyzes have come to different conclusions on the estimation of the production scale limit of CdTe photovoltaic technology. Martin Green's most conservative estimate is about 10GWp/year, while the more optimistic estimate is 20-100GWp/year, and according to the current The growth rate will start to stop increasing after 2020.

The use of CdTe can be reduced by reducing the thickness of CdTe. CdTe is an ideal light-absorbing semiconductor, with a visible light absorption rate of 10 ⁴ -10 ⁵ cm ^-1 , and only needs 0.1 μm to absorb at least 63% of visible light (wavelength <826nm). Univ.of Toledo in the United States used magnetron sputtering to prepare CdTe batteries with a thickness of only 0.5 μm and 0.75 μm, and the conversion efficiency reached 11% and 12.5% respectively.

However, there is a fundamental physical problem in ultrathin CdTe solar cells, which is the weak diode effect due to the spatial non-uniformity of CdTe semiconductor layer thickness or composition. This is because the p-type CdTe semiconductor layer and the n-type CdS semiconductor layer forming the junction field in the battery are both polycrystalline thin films, and the entire device is equivalent to many miniature photodiodes arranged side by side and connected in parallel. There is a certain microscopic non-uniformity in the thickness of the polycrystalline film, which will randomly cause the distance between the front and rear electrode layers and the junction interface to be closer than other places in a certain part of the battery, and form a miniature weak diode in a local area. Since the opening voltage of the miniature weak diode is smaller than that of the normal diode, when the voltage of the surrounding normal photodiode in parallel with it is at the maximum power point, the weak diode in the same voltage state is just in the forward conduction state. In conventional 2–10 μm thick CdTe cells, photocurrents within the surrounding 1mm to 1m range can be swallowed. The range of influence exceeds 10 ³ -10 ⁶ times its own size. It is also an important microcosmic mechanism that causes the open circuit voltage drop of CdTe solar cells.

It can be seen that if the thickness of the CdTe semiconductor layer is simply reduced, although the use of the CdTe semiconductor can be reduced, the open circuit voltage of the CdTe solar cell will often be reduced. Professor James Sites of Colorado State Univ., USA [Kuo-Jui Hsiao, James R. Sites, "ELECTRON REFLECTOR STRATEGY FOR CdTe SOLAR CELLS", Proceedings of 34th IEEE Photovoltaic Specialist Conference, 001846-001850, 2009; K.-J.Hsiao, JRSites, "Electron reflector to enhance photovoltaic efficiency: application to thin-film CdTe solar cells", Prog. Photovolt: Res. Appl., 20, 486–489, 2012.] recently proposed to use between the CdTe light absorbing layer and the metal electrode layer The structure of electron back reflection potential barrier can be formed, and the structure of reducing the thickness of CdTe semiconductor layer can improve battery efficiency. Through a large number of device simulation studies, they found that if an electronic back reflection barrier with a height of 0.2eV is formed at the contact interface between the CdTe semiconductor layer and the metal electrode layer of the CdTe solar cell, the open circuit voltage of the CdTe solar cell with a thickness of 10 μm can be reduced from the current ~860mV is increased to 900mV; further reducing the thickness of the CdTe light-absorbing semiconductor layer to 2μm can increase the open circuit voltage to above 940mV. If the thickness of the CdTe light-absorbing semiconductor layer is further reduced to about 1 μm, and an optical back-reverse structure with 100% reflectance is used, the open-circuit voltage may be increased to 1V even if the hole concentration of the CdTe light-absorbing semiconductor layer is less than 10 ¹⁴ cm ^-3 , the conversion efficiency reaches 20%.

Although James Site proposed the use of Cd _1-x Zn _x Te, Cd _1-x Mg _x Te wide-bandgap ternary II-VI semiconductors to obtain a suitable electronic back reflection barrier and reduce the thickness of the CdTe light-absorbing layer. To obtain a higher open-circuit voltage, but no substantive suggestions were made on the actual process technology route and the physical problems to be faced.

As the thickness of the CdTe light-absorbing layer decreases, the probability of forming pinholes in the CdTe light-absorbing layer becomes larger; and the weak diode effect caused by the non-uniformity of the CdTe light-absorbing layer thickness becomes more prominent. Therefore, to prepare a CdTe light-absorbing layer with a thickness below 1.0 μm, it is necessary to obtain polycrystalline particles whose size is much smaller than the average thickness. Traditional p-n junction CdS/CdTe solar cells are currently used in the production and scientific research of physical vapor deposition and near-space sublimation technology. The substrate temperature of these two deposition technologies is about 600 ° C. It is a high-temperature deposition technology. CdTe usually obtained The crystal grains of the light-absorbing layer film are all between 5-10 μm. Another commonly used method is magnetron sputtering technology. The substrate temperature is lower than 600°C, but the conversion efficiency and open circuit voltage close to those of physical vapor deposition and near-space sublimation technology can be obtained. In the process of low-temperature magnetron sputtering deposition technology, there is plasma bombardment on the surface of the semiconductor layer, which can make low-temperature atoms gain enough kinetic energy to move to low-energy positions. The grain size of the polycrystalline film of the semiconductor layer sputtered by magnetron is only 0.5 μm, and the grains prepared by magnetron sputtering film can achieve the microscopic flatness of the surface of the polycrystalline film of the CdTe light-absorbing layer with a thickness of less than 1 μm, thus greatly reducing the weak diode effect The probability of occurrence has obvious advantages over physical vapor deposition and near-space sublimation deposition methods.

Patent CN102891204A proposes a CdTe thin-film solar cell with n-i-p structure, but it is a lower substrate structure, and both the intrinsic light absorption layer and the p-type semiconductor layer are CdTe, and the thickness of CdTe is relatively thick.

Contents of the invention

The purpose of the present invention is to propose a p-i-n structure CdTe solar cell and its preparation method in order to overcome the shortcomings of the existing p-n junction CdTe structure solar cell with low open circuit voltage and conversion efficiency and the thickness of the used CdTe semiconductor layer.

The CdTe solar cell with the p-i-n structure of the present invention can reduce the thickness of the CdTe intrinsic light absorbing layer to less than 1 μm, but can still achieve an open circuit voltage of more than 1V and a conversion efficiency of more than 20%. The invention realizes the preparation of the n-type semiconductor layer, the intrinsic semiconductor layer and the p-type semiconductor layer in the p-i-n battery structure through the magnetron sputtering preparation method, and can improve the performance of the CdTe solar cell while reducing the thickness of the CdTe intrinsic light-absorbing layer. Open circuit voltage and conversion efficiency. Moreover, the magnetron sputtering preparation method of the present invention can further reduce the cost of the CdTe solar cell.

The CdTe solar cell structure of the p-i-n structure of the present invention is as follows:

The CdTe battery includes a transparent conductive electrode layer, a CdS n-type semiconductor layer, a CdTe intrinsic light absorption layer, a wide bandgap ternary II-VI group semiconductor p ⁺ layer, ZnO:Al or In ₂ O ₃ :Sn n ⁺ Anti-tunneling layer, and metal electrode layer. Above the substrate is a transparent conductive electrode layer, on the transparent conductive electrode layer is a CdS n-type semiconductor layer, on the CdS n-type semiconductor layer is a CdTe intrinsic light absorption layer, and on the CdTe intrinsic light absorption layer is a wide bandgap three Elementary II-VI group semiconductor p ⁺ layer, wide-gap ternary II-VI group semiconductor p ⁺ layer is ZnO:Al or In ₂ O ₃ :Sn n+ anti-increasing tunneling layer, ZnO:Al or In ₂ O ₃ : On the Sn n+ anti-increasing tunneling layer is a metal electrode layer.

The wide bandgap ternary II-VI semiconductor is, for example: Cd _1-x Zn _x Te or Cd _1-x Mg _x Te.

The CdTe intrinsic light absorbing layer of the CdTe cell has a thickness of 0.1-1.0 μm, and photogenerated carriers are generated inside it under light.

The CdS in the CdTe battery is an n-type semiconductor layer, and the wide bandgap ternary II-VI group semiconductor is a p-type semiconductor layer, such as: Cd _1-x Zn _x Te, Cd _1-x Mg _x Te. The CdS n-type semiconductor layer and the wide-bandgap II-VI semiconductor p-type layer provide a pn junction and provide functions such as separation and transport of photo-generated carriers generated in the CdTe intrinsic light-absorbing layer.

The pin structure CdTe solar cell of the present invention can obtain a better light trapping structure from two aspects. The efficiency loss of traditional pn structure CdTe devices with CdTe intrinsic light absorbing layer thickness less than 1.0 μm mainly comes from the recombination near the back metal electrode layer and the incomplete absorption of the near-infrared band. In pin solar cell devices, in addition to selecting a suitable electron (minority carrier) back reflection field structure and reducing the recombination at the back metal electrode, it is also necessary to use an appropriate light trapping structure to reduce deep absorption loss. This is the key to improving the open-circuit voltage of ultra-thin CdTe batteries and minimizing the short-circuit current loss of ultra-thin batteries. First, the pin structure CdTe solar cell of the present invention adopts the method of magnetron sputtering to prepare CdS n-type semiconductor layer, CdTe intrinsic light absorption layer, wide bandgap ternary II-VI semiconductor p ⁺ layer, ZnO:Al or In ₂ O ₃ : Sn n ⁺ increased anti-tunneling layer. A porous CdS/CdTe interface can be obtained by magnetron sputtering. Before entering the CdTe intrinsic light absorbing layer, it is scattered, increasing the optical path in the absorbing layer. Secondly, in the pin structure CdTe solar cell of the present invention, n-type ZnO:Al or In ₂ O ₃ is inserted between the wide bandgap ternary II-VI semiconductor p ⁺ layer and the metal electrode layer that is both an electrode layer and a reflective layer: Sn n ⁺ increases the anti-tunneling layer, which further realizes a good light trapping effect.

In the CdTe solar cell with a pin structure of the present invention, a wide-bandgap ternary II-VI group semiconductor is used in the middle of the metal electrode layer of the CdTe intrinsic light-absorbing layer to cooperate with ZnO:Al or In ₂ O ₃ :Sn n ⁺ anti-increasing tunneling layer Composite structures, such as: Cd _1-x Zn _x Te or Cd _1-x Mg _x Te/ZnO:Al or In ₂ O ₃ :Sn, can simultaneously obtain the functions of electronic back reflection field and back reflection light trapping structure. Wide-bandgap II-VI semiconductors, such as: ZnTe is a wide-bandgap II-VI semiconductor with a bandgap width of 2.26eV, which is transparent to visible light, and forms a wide-bandgap II-VI semiconductor with CdTe, such as: Cd _1-x Zn _x Te semiconductor, a semiconductor with a band gap between 1.5-2.26eV can be obtained. This ternary semiconductor layer is used as the back contact transition layer of the CdTe intrinsic light absorbing layer, and can play the role of increasing and reverse tunneling layer. More importantly, the work function of ZnTe is very close to that of CdTe, which are 5.79eV and 5.72eV, which are almost the same. Therefore, for wide-bandgap II-VI semiconductors, such as: the p-type doping of the ZnTe layer will directly lead to the rise of the top of its valence band relative to CdTe, and form a back reflection barrier relative to CdTe in the conduction band, which is used for reflective light generation. electronic. This can effectively avoid carrier recombination near the back metal electrode, and improve the open circuit voltage and fill factor. ZnTe is a II-VI semiconductor that is easy to do p-type doping. Adding Zn to CdTe semiconductor can improve the doping ability of CdTe semiconductor, and it is easier to obtain p-type semiconductor. Alternative p-type doping elements include shallow-level acceptor impurities in CdTe and ZnTe such as N and P, and p-type impurities commonly used in CdTe batteries such as Cu, Sb, Bi, and P. Nitrogen N and phosphorus P doping can be achieved by mixing an appropriate proportion of nitrogen _N2 or phosphine _PH3 in the RF magnetron sputtering working gas Ar, while other elements can be obtained by sputtering targets containing these impurities Corresponding doping, such as doping Cu, P, Sb, Bi and other elements. The contact between CdTe and wide-bandgap ternary II-VI semiconductors, such as: Cd _1-x Zn _x Te, Cd _1-x Mg _x Te can effectively reduce the lattice mismatch at the interface and reduce the concentration of recombination centers near the back electrode.

In the CdTe solar cell with pin structure of the present invention, n-type ZnO:Al or In ₂ O ₃ :Sn is inserted between the p-type wide bandgap ternary II-VI semiconductor layer and the metal reflective layer that is also an electrode. wear layers. In terms of optical performance, the highest near-infrared light reflectance can be obtained at the back metal electrode interface by adjusting the thickness of the ZnO:Al or In ₂ O ₃ :Sn antireflective tunneling layer. A p + /n + type double-layer tunneling structure is formed between the n-type ZnO:Al or In ₂ O ₃ :Sn anti-increasing tunneling layer and the p ^{- type} wide bandgap ternary II-VI group material layer, which helps holes from Transport of CdTe across the back electrode interface to the metal electrode layer.

Although the thickness of the CdTe battery of the invention is only 0.1-1.0 μm, the open circuit voltage can still reach more than 1V, and the conversion efficiency can reach more than 20%. The cost of the CdTe battery can be greatly reduced, and the conversion efficiency of the CdTe polycrystalline thin film battery can be improved.

During the magnetron sputtering process of the present invention, a gas containing N and P is mixed into the incoming Ar gas to prepare a CdTe battery. The magnetron sputtering method can realize low-temperature growth, can well control the growth rate, effectively control the grain size of the polycrystalline film, and control the surface roughness of the polycrystalline film. The crystal grains of magnetron sputtering polycrystalline film can ensure the microscopic flatness of the surface of ultra-thin CdTe intrinsic light-absorbing layer film with a thickness of ≤1 μm, thus greatly reducing the probability of weak diode effect, compared with vapor transport deposition and near-space sublimation The deposition method has clear advantages.

The solar cell preparation method of the present invention is specifically described as follows:

1. Clean the substrate;

2. Growing a transparent conductive electrode layer on the substrate;

3. Growing a CdS n-type semiconductor layer and a CdTe intrinsic light-absorbing semiconductor layer sequentially on the transparent conductive electrode layer on the substrate;

4. Carry out annealing treatment to the prepared CdS n-type semiconductor layer and CdTe intrinsic light-absorbing semiconductor layer in an atmosphere of _CdCl2 vapor;

5. On the CdTe intrinsic light-absorbing semiconductor layer after CdCl ₂ annealing, deposit a wide bandgap II-VI semiconductor p ⁺ layer and ZnO:Al or In ₂ O ₃ :Sn n ⁺ antireflection in sequence by magnetron sputtering method Then through the layer. During the magnetron sputtering process, the gas containing N and P is mixed in the incoming Ar, and nitrogen (N) or phosphorus (P) is doped in the wide bandgap II-VI semiconductor p ⁺ wide bandgap layer, or after using The way of diffusion is to dope p-type impurities such as copper (Cu) or phosphorus (P) or dysprosium (Sb) or bismuth (Bi) in the wide bandgap II-VI semiconductor wide bandgap layer.

6. Depositing a metal conductive electrode layer on the surface of the ZnO:Al or In ₂ O ₃ :Sn n ⁺ enhancement tunneling layer.

So far, the p-i-n structure CdTe solar cell is produced.

In the step 1, the substrate may be a rigid substrate or a flexible substrate.

The step 2 is to grow a transparent conductive electrode layer, which is used to export electrons. The transparent conductive film can be In ₂ O ₃ :Sn or ZnO:Al or ZnO:B or In ₂ O ₃ :Mo or In:ZnO or graphene or SnO ₂ :F or Cd ₂ SnO ₄ and so on. The process of growing transparent conductive thin film can adopt magnetron sputtering method, pulsed laser deposition technology, ultrasonic spray pyrolysis method, molecular beam epitaxy method, colloidal gel method, chemical vapor deposition method. The thickness of the conductive electrode layer is 0.3-1500nm.

The operation method of described step 3 is: put the substrate that has prepared transparent conductive electrode layer on the position that magnetron sputtering furnace places substrate, cover the lid of magnetron sputtering furnace, to magnetron sputtering furnace The chamber is evacuated and heated to maintain the substrate temperature at 25-600°C. When the background vacuum reaches below 10 ^-3 Pa, start to sputter the CdS semiconductor layer. The sputtering conditions of the CdS semiconductor layer are as follows: the substrate temperature is 25-600°C, high-purity Ar gas is introduced into the magnetron sputtering furnace chamber, the gas flow rate is 10-100 sccm, and the magnetron sputtering furnace chamber pressure is 0.1-10Pa. When the thickness of the sputtered CdS semiconductor layer on the substrate is 10-100 nm, the preparation of the CdS semiconductor layer is stopped. Turn the substrate to the position facing the CdTe target, and start sputtering the CdTe semiconductor layer. The sputtering conditions of the CdTe semiconductor layer are as follows: the substrate temperature is 25-600°C, high-purity Ar gas is introduced into the magnetron sputtering furnace chamber, the gas flow rate is 10-100 sccm, and the magnetron sputtering furnace chamber pressure is 0.1-10Pa. When the thickness of the sputtered CdTe semiconductor layer on the substrate reaches a set thickness of 0.1-1 μm, the thickness of the CdTe layer is measured by an online film thickness measuring device. The preparation of the CdTe semiconductor layer is stopped, and the heating of the substrate is stopped at the same time. When the temperature of the substrate is lowered to room temperature, the substrate deposited with the CdS and CdTe semiconductor layers is taken out.

In step 4, the prepared CdS and CdTe semiconductor layers are annealed in a CdCl ₂ atmosphere, and the CdS n-type semiconductor layer and the CdTe intrinsic light-absorbing semiconductor layer are annealed at 300-500° C. for 5-120 minutes. Annealing can be done by wet or dry methods. The process of wet annealing is as follows: the saturated methanol solution of CdCl ₂ is evenly dropped on the CdTe intrinsic light-absorbing semiconductor layer, and the CdTe intrinsic light-absorbing semiconductor layer is annealed. The process of dry annealing is as follows: place _CdCl evenly on the glass sheet, and then place a substrate with a CdTe intrinsic light-absorbing semiconductor layer, a CdSn type semiconductor layer and a transparent conductive electrode layer at a distance of 1-5 mm from the glass sheet. The CdTe semi-intrinsic light-absorbing conductor layer is facing the glass sheet with CdCl ₂ , and then the CdSn type semiconductor layer and the CdTe intrinsic light-absorbing semiconductor layer are annealed.

The operation method of the step 5 is: put the substrate covered with the transparent conductive electrode layer, the CdS n-type semiconductor layer, the CdTe intrinsic light absorbing layer on the position where the substrate is placed in the magnetron sputtering furnace, cover the magnetron The furnace cover of the sputtering furnace, vacuumize the magnetron sputtering furnace chamber, and raise the temperature to keep the substrate temperature at 25-600°C with a transparent conductive electrode layer, CdS n-type semiconductor layer, and CdTe intrinsic light absorption layer scope. When the background vacuum reaches below 10 ^-3 Pa, start sputtering the p ⁺ layer of the wide bandgap ternary II-VI semiconductor. The sputtering conditions for the wide bandgap ternary II-VI semiconductor p ⁺ layer are: the substrate temperature is 25-600°C, and high-purity Ar, or Ar and N ₂ , or Ar and PH ₃ are introduced into the magnetron sputtering chamber , gas flow rate 10-100sccm, chamber pressure 0.1-10Pa. When the thickness of the p ⁺ layer of the wide bandgap ternary II-VI group semiconductor is 1-100 nm, the preparation of the wide bandgap ternary II-VI group semiconductor p ⁺ layer is stopped. Or after sputtering the wide-bandgap ternary II-VI semiconductor p ⁺ layer, cover with transparent conductive electrode layer, CdS n-type semiconductor layer, CdTe intrinsic light absorption layer, wide-bandgap ternary II-VI semiconductor p ⁺ layer substrate, and then grow 1-20nm Cu or P or Sb ₂ Te ₃ or Bi ₂ Te ₃ on the wide bandgap ternary II-VI semiconductor p ⁺ layer by electron beam or thermal evaporation, and then rapidly Diffusion is carried out in a furnace at a temperature range of 50-600°C, and the diffusion time is 0.1-120min. Turn the substrate to the position facing the ZnO:Al or In ₂ O ₃ :Sn target, and start sputtering the ZnO:Al or In ₂ O ₃ :Snn ⁺ layer. The sputtering conditions of ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer are: the substrate temperature is 25-600°C, high-purity Ar gas is introduced into the magnetron sputtering chamber, the gas flow rate is 10-100sccm, and the magnetron sputtering The injection chamber pressure is 0.1-10Pa. When the thickness of the sputtered ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer on the substrate reaches the set thickness of 1-100nm, stop the preparation of the ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer, At the same time, stop heating the substrate, and take out the substrate when the temperature of the substrate drops to room temperature.

Or put the substrate covered with transparent conductive electrode layer, CdS n-type semiconductor layer, CdTe intrinsic light absorbing layer on the position where the substrate is placed in the magnetron sputtering furnace, cover the furnace cover of the magnetron sputtering furnace, to The chamber of the magnetron sputtering furnace is evacuated, and the temperature is raised to keep the temperature of the substrate with the transparent conductive electrode layer, the CdS n-type semiconductor layer, and the CdTe intrinsic light absorption layer at 25-600°C. When the background vacuum reaches below 10 ^-3 Pa, start sputtering the p ⁺ layer of the wide bandgap ternary II-VI semiconductor. The sputtering condition of the wide bandgap ternary II-VI semiconductor p ⁺ layer is: the target material is a wide bandgap ternary II-VI semiconductor layer doped with Cu or P or Sb or Bi, such as: Cd _1-x Zn _x Te or Cd _1-x Mg _x Te, the substrate temperature is 25-600°C, the flow rate of high-purity Ar gas is 10-100sccm, and the chamber pressure is 0.1-10Pa, into the magnetron sputtering chamber. When the thickness of the p ⁺ layer of the wide bandgap ternary II-VI group semiconductor is 1-100 nm, the preparation of the wide bandgap ternary II-VI group semiconductor p ⁺ layer is stopped. Turn the substrate to the position facing the ZnO:Al or In ₂ O ₃ :Sn target, and start sputtering the ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer. The sputtering conditions of ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer are: the substrate temperature is 25-600°C, high-purity Ar gas is introduced into the magnetron sputtering chamber, the gas flow rate is 10-100sccm, and the magnetron sputtering The injection chamber pressure is 0.1-10Pa. When the thickness of the sputtered ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer on the substrate reaches the set thickness of 1-100nm, stop the preparation of the ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer, At the same time, stop heating the substrate, and take out the substrate when the temperature of the substrate drops to room temperature.

The operation method of the step 6 is: by thermal evaporation or electron beam on the ZnO:Al or In ₂ O ₃ :Sn n ⁺ layer enhancement and reflection tunneling layer, a metal electrode layer with a thickness greater than 5nm is evaporated, and the thickness of the metal electrode layer is Measured with a quartz crystal oscillator.

So far, the p-i-n structure CdTe solar cell described in the present invention is obtained.

The CdTe solar cell of the p-i-n structure of the present invention has the following advantages compared with the traditional p-n structure CdTe polycrystalline thin film solar cell:

The intrinsic layer of the battery structure used in the present invention is CdTe, and the intrinsic thickness of CdTe light absorption is only 0.1-1.0 μm, and the thickness is obtained by online film thickness measurement equipment, which greatly reduces the use of CdTe materials.

The battery structure adopted in the present invention is a p-i-n structure, and the preparation method is a magnetron sputtering method, which can obtain sufficiently small semiconductor layer thin film grains, and can characterize the structure of the semiconductor layer thin film grains by SEM to ensure the intrinsic i-layer thin film. The quality can guarantee the microscopic flatness of the surface of the ultra-thin CdTe (≤1μm) light-absorbing layer, thus greatly reducing the probability of the weak diode effect, which has obvious advantages over physical vapor deposition and near-space sublimation technology.

The invention adopts low-temperature magnetron sputtering to prepare the pin structure, which can obtain a good light-trapping structure. The semiconductor layers of pin are prepared by magnetron sputtering, and a porous CdS/CdTe interface can be obtained. The cross-section is processed by FIB and observed by SEM. Before the light enters the CdTe light-absorbing intrinsic layer, it is scattered and added in the absorbing layer. light path. Secondly, insert a ZnO:Al or In ₂ O ₃ :Snn+ type anti-increasing tunneling layer between the wide-bandgap ternary II-VI semiconductor p ⁺ layer and the metal layer that is both an electrode and a reflective layer, and the anti-increasing tunneling layer It can play a good light trapping effect, and further achieve an effective light trapping effect.

The CdTe solar cell with the pin structure of the present invention uses reactive sputtering to dope nitrogen (N) or phosphorus (P) into the wide bandgap ternary II-VI group semiconductor p ⁺ layer, or uses post-diffusion to dope copper ( Cu) or phosphorus (P) or dysprosium (Sb) or bismuth (Bi) and other p-type impurities.

The open-circuit voltage of the CdTe solar cell with p-i-n structure used in the present invention is expected to reach more than 1V, and the conversion efficiency is expected to reach more than 20%.

Description of drawings

Figure 1 is a schematic diagram of the structure of a CdTe thin film solar cell with a traditional p-n junction structure. In the figure: 1-1 substrate, 1-2 transparent conductive electrode layer, 1-3CdS n-type semiconductor layer, 1-4CdTe intrinsic light absorption layer, 1-5 metal electrode layers.

Fig. 2 is the structural representation of the CdTe solar cell of pin structure of the present invention, among the figure: 2-1 substrate, 2-2 transparent conductive electrode layer, 2-3CdS n-type semiconductor layer, 2-4CdTe intrinsic light absorption layer, 2 -5 wide bandgap ternary II-VI semiconductor p ⁺ layers, 2-6 ZnO:Al or In ₂ O ₃ :Sn n ⁺ layers, 2-7 metal electrode layers.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

The CdTe battery includes a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, a CdTe intrinsic light absorption layer 2-4, a wide bandgap ternary II-VI group semiconductor p ⁺ layer 2-5, ZnO : Al or In ₂ O ₃ : Sn n ⁺ anti-increasing tunneling layer 2-6, and metal electrode layer 2-7. On the substrate 2-1 is a transparent conductive electrode layer 2-2, on the transparent conductive electrode layer 2-2 is a CdS n-type semiconductor layer 2-3, on the CdS n-type semiconductor layer 2-3 is a CdTe intrinsic Light absorbing layer 2-4, CdTe intrinsic light absorbing layer 2-4 is a wide bandgap ternary II-VI group semiconductor p ⁺ layer 2-5, wide bandgap ternary II-VI group semiconductor p ⁺ layer 2-5 The anti-reflection tunneling layer _2-6 is ZnO:Al or In ₂ O 3 :Sn n+, and the metal electrode layer 2-7 is on the ZnO:Al or In ₂ O ₃ :Sn n+ anti-reflection tunneling layer 2-6.

Example 1

First, the 99.999% high-purity ZnO: Al target is installed on the target position of the magnetron sputtering equipment, and then the glass substrate 2-1 cleaned with micro-90 according to step 1 is sent to the magnetron sputtering equipment. The vacuum chamber is heated to 200°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, the radio frequency power supply is turned on, and the output power of the power supply is adjusted to 180W, the distance between the target and the glass substrate The distance between them is 11 cm, and a 1.0 μm thick ZnO:Al transparent conductive electrode layer (TCO) 2-2 is deposited by sputtering under this process. Then put the glass substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 250°C. Evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3 Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 40W, and the distance between the target and the glass substrate is 11cm, under this process A 10 nm thick CdS n-type semiconductor layer 2-3 was sputter deposited. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the distance between the target and the glass substrate The distance between them is 11 cm, and a 100 nm thick CdTe semiconductor layer 2-4 is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. Perform Cl treatment on the battery multilayer film structure according to step 4, the Cl treatment temperature is 300° C., and the treatment time is 5 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber is heated to 250°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2Pa, the radio frequency power is turned on, and the output power of the power supply is adjusted to 60W, the target and the glass substrate The distance between 2-1 is 11cm. Under this process, a 1nm-thick Cd _1-x Zn _x Te semiconductor layer 2-5 is deposited by sputtering, and then the position of the substrate is turned to ZnO:Al, and the vacuum chamber pressure is maintained at 2Pa. The output power of the RF power supply is 60W, and the distance between the target and the glass substrate is 11cm. Under this process, a 1nm-thick ZnO:Al n ⁺ layer 2-6 is deposited by sputtering. So far, the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5, ZnO:Al n ⁺ Layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , ZnO:Aln ⁺ layer taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait for the vacuum of the chamber to be below 10 ^-4 Pa, start to deposit Mg metal electrode layer 2-7 with a thickness of 200nm on the surface of ZnO:Al n ⁺ layer 2-6. So far, the preparation of the pin structure CdTe solar cell polycrystalline thin film cell is completed.

Example 2

First install the 99.999% high-purity ZnO:B target on the target position of the magnetron sputtering equipment, and then send the glass substrate 2-1 cleaned with micro-90 into the vacuum chamber of the magnetron sputtering equipment , and keep it at 25°C; evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 2 Pa, and the flow rate of Ar is 10 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 140W, the target and the glass The distance between the substrates 2-1 is 11 cm, and a 1.0 μm thick ZnO:B transparent conductive electrode layer (TCO) 2-2 is deposited by sputtering under this process. Then put the glass substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and keep it at 25°C. Evacuate the vacuum chamber to be lower than 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3 Pa, and the Ar flow rate is 10 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the distance between the target and the glass substrate 2-1 The distance is 11 cm, and a 10 nm thick CdS n-type semiconductor layer 2-3 is deposited by sputtering under this process. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, and the Ar flow rate is 10 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the target The distance from the glass substrate 2-1 is 11 cm, and a 500 nm thick CdTe semiconductor layer 2-4 is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made. Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. According to step 4, perform Cl treatment on the battery multilayer thin film structure, the Cl treatment temperature is 500° C., and the treatment time is 5 minutes. After completing the Cl treatment process, cool the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The substrate temperature is kept at 25°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, the flow rate of Ar gas is 10 sccm, the radio frequency power supply is turned on, and the output power of the power supply is adjusted to 60W, the distance between the target and the glass substrate 2-1 is 11cm. Under this process, a 1nm thick Cd _1-x Zn _x Te semiconductor layer 2-5 is deposited by sputtering, and then the position of the substrate 2-1 is turned to In ₂ O ₃ : Sn target, the pressure of the vacuum chamber is maintained at 2Pa, the output power of the RF power supply is 60W, the distance between the target and the glass substrate 2-1 is 11cm, and 1nm thick In ₂ O is deposited by sputtering under this process ₃ : Snn ⁺ layers 2-6. So far, a substrate with a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, a CdTe semiconductor layer 2-4, a Cd _1-x Zn _x Te semiconductor layer 2-5, and an In ₂ O ₃ :Sn n ⁺ layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , In ₂ O ₃ :Sn n ⁺ layers 2-6 are taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait for the vacuum of the chamber to be below 10 ^-4 Pa, start to deposit a Ni metal conductive electrode layer with a thickness of 200nm on the surface of In ₂ O ₃ : Sn n ⁺ layer 2-6 2-7. So far, the preparation of the pin structure CdTe polycrystalline thin film battery is completed.

Example 3

The surface of mica substrate 2-1 cleaned with micro-90 was prepared by chemical vapor deposition method to prepare graphene transparent conductive electrode layer 2-2. The graphene growth method is as follows: prepare graphene in a tube furnace by chemical vapor deposition, put a 0.5mm thick Cu foil into the tube furnace, then heat the tube furnace to 1000°C, and feed methane and hydrogen, Keep at 1000°C for 15 minutes to obtain the desired graphene. Then graphene is transferred to polymethyl methacrylate (PMMA) by a solution of ferric chloride and hydrochloric acid, and graphene is put on the mica substrate 2-1, and polymethyl methacrylate is dissolved by acetone Then, a transparent conductive electrode layer 2-2 with a thickness of 0.3 nm was obtained on the mica substrate 2-1. Then put the mica substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 600°C. Evacuate the vacuum chamber to be lower than 10 ^-4 Pa, fill the vacuum chamber with argon gas to 10 Pa, and the Ar flow rate is 100 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 100W, and the distance between the target and the mica substrate 2-1 The distance is 11 cm, and a 100 nm thick CdS n-type semiconductor layer 2-3 is deposited by sputtering under this process. Then turn the substrate 2-1 to the position facing the CdTe target, start sputtering the CdTe intrinsic light-absorbing semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, and the Ar flow rate is 100 sccm, turn on the radio frequency power supply, adjust the The output power of the power supply is 120W, and the distance between the target and the substrate 2-1 is 11cm. Under this process, a 1000nm thick CdTe intrinsic light-absorbing semiconductor layer 2-4 is deposited by sputtering. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. According to step 4, perform Cl treatment on the battery multilayer thin film structure, the Cl treatment temperature is 400° C., and the treatment time is 30 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber is heated to 600°C; the vacuum chamber is evacuated to below 10 ^-4 Pa, the vacuum chamber is filled with argon and N ₂ to 10Pa, the gas flow rate is 100 sccm, turn on the radio frequency power supply, and adjust the output power of the power supply For 160W, the distance between the target and the glass 2-1 substrate is 11cm. Under this process, a 100nm thick Cd _1-x Mg _x Te semiconductor p ⁺ layer 2-5 is deposited by sputtering, and then the substrate 2-1 The position is turned to the In ₂ O ₃ :Sn target, the pressure of the vacuum chamber is kept at 10Pa, the output power of the RF power supply is 160W, and the distance between the target and the mica substrate 2-1 is 11cm. Under this process, a 100nm thick In ₂ O ₃ :Sn n ⁺ augmentation and reverse tunneling layers 2-6. So far, the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Mg _x Te semiconductor p ⁺ layer 2-5, In ₂ O ₃ :Sn n ⁺ augments and reverses tunneling layers 2-6. After it is cooled to room temperature, the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Mg _x Te semiconductor p ⁺ layer 2 -5. In ₂ O ₃ : Sn n ⁺ augmentation-reverse tunneling layer 2-6 is taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait for the vacuum of the chamber to be below 10 ^-4 Pa, start to deposit Al with a thickness of 500nm on the surface of In ₂ O ₃ : Sn n ⁺ augmentation and reflection tunneling layer 2-6 Metal conductive electrode layers 2-7. So far, the preparation of the pin structure CdTe polycrystalline thin film battery is completed.

Example 4

First install the 99.999% high-purity In ₂ O ₃ :Mo target on the target position of the magnetron sputtering equipment, and then send the glass substrate 2-1 cleaned with micro-90 into the magnetron sputtering equipment Vacuum chamber, and keep it at 270°C; evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 2Pa, the Ar flow rate is 40sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 80W, the target The distance from the glass substrate 2-1 is 11 cm, and a 1.5 μm thick In ₂ O ₃ : Mo transparent conductive electrode layer (TCO) 2-2 is deposited by sputtering under this process. Then put the glass substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and keep it at 270°C. Evacuate the vacuum chamber to be lower than 10 ^-4 Pa, fill the vacuum chamber with argon gas to 0.1Pa, the Ar flow rate is 10sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and place a gap between the target and the glass substrate 2-1 The distance is 11 cm, and a 40 nm thick CdS n-type semiconductor layer 2-3 is deposited by sputtering under this process. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 0.1Pa, and the Ar flow rate is 10 sccm, turn on the radio frequency power supply, and adjust the output power of the power supply to 60W. The distance between the target and the glass substrate 2-1 is 11 cm, and a 900 nm thick CdTe semiconductor layer 2-4 is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. Perform Cl treatment on the battery multilayer film structure according to step 4, the Cl treatment temperature is 390° C., and the treatment time is 10 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment In a vacuum chamber, the substrate temperature is heated to 250°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon and pH ₃ to 2Pa to 2Pa, the gas flow rate is 40 sccm, turn on the radio frequency power supply, and adjust the The output power of the power supply is 60W, and the distance between the target and the glass substrate 2-1 is 11cm. Under this process, a 10nm thick Cd _1-x Zn _x Te semiconductor layer 2-5 is deposited by sputtering, and then the substrate 2- The position of 1 turns to the Al ₂ O ₃ :Zn target, the pressure of the vacuum chamber is maintained at 2Pa, the output power of the RF power supply is 60W, and the distance between the target and the glass substrate 2-1 is 11cm, and the thickness of 100nm is deposited by sputtering under this process Al ₂ O ₃ :Znn ⁺ layers 2-6. So far, a substrate with substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5, Al ₂ O ₃ :Znn ⁺ layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , Al ₂ O ₃ :Znn ⁺ layers 2-6 were taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait for the vacuum of the chamber to be below 10 ^-4 Pa, start to deposit Au metal conductive electrode layer with a thickness of 100nm on the surface of Al ₂ O ₃ :Zn n ⁺ layer 2-6 2-7. So far, the preparation of the pin structure CdTe polycrystalline thin film battery is completed.

Example 5

First install the 99.999% high-purity In ₂ O ₃ :Sn target on the target position of the magnetron sputtering equipment, and then send the glass substrate 2-1 cleaned with micro-90 according to step 1 into the magnetron sputtering The vacuum chamber of the injection equipment is heated to 300°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, the radio frequency power is turned on, and the output power of the power supply is adjusted to 120W, the target and the glass The distance between the substrates was 11 cm, and a 1.0 μm thick In ₂ O ₃ : Sn transparent conductive electrode layer (TCO) 2-2 was deposited by sputtering under this process. Then put the glass substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 250°C. Evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3 Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 40W, and the distance between the target and the glass substrate is 11cm, under this process A 50 nm thick CdS n-type semiconductor layer 2-3 was deposited by sputtering. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the distance between the target and the glass substrate The distance between them is 11 cm, and a CdTe semiconductor layer 2-4 with a thickness of 600 nm is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. According to step 4, perform Cl treatment on the battery multilayer thin film structure, the Cl treatment temperature is 380° C., and the treatment time is 30 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber is heated to 250°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, and the other flow rate is 100 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and target The distance to the glass substrate 2-1 is 11 cm, and a 50 nm thick Cd _1-x Zn _x Te semiconductor layer 2-5 is deposited by sputtering under this process. Stop heating, then wait for the substrate covered with transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 to cool to room temperature, Take it out of the chamber and put it into the vacuum chamber of electron beam and thermal evaporation. After the chamber is vacuumed below 10 ^-4 Pa, start to deposit Cu with a thickness of 20nm by electron beam, and then heat it in a rapid annealing furnace at 600°C. Diffuse for 0.1 min.

Then have substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5, Cd _1-x The substrate with Cu on the Zn _x Te semiconductor layer 2-5 is placed in a sputtering vacuum chamber and heated to 320°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, and the vacuum chamber is filled with argon to 2Pa , turn the position of the substrate to the Al ₂ O ₃ :Zn target, keep the pressure of the vacuum chamber at 2Pa, the output power of the RF power supply is 60W, and the distance between the target and the glass substrate is 11cm. Al ₂ O ₃ :Zn n ⁺ layers 2-6. So far, a substrate with substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5, Al ₂ O ₃ : Structure of Zn n ⁺ layers 2-6. After it is cooled to room temperature, the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , Al ₂ O ₃ :Zn n ⁺ layers are taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait until the chamber is vacuumed below 10 ^-4 Pa, start to deposit Au metal electrode layer 2 with a thickness of 50nm on the surface of Al ₂ O ₃ : Zn n ⁺ layer 2-6 -7. So far, the preparation of the pin structure CdTe solar cell polycrystalline thin film cell is completed.

Example 6

First, the 99.999% high-purity ZnO: Al target is installed on the target position of the magnetron sputtering equipment, and then the glass substrate 2-1 cleaned with micro-90 according to step 1 is sent to the magnetron sputtering equipment. The vacuum chamber is heated to 200°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, the radio frequency power supply is turned on, and the output power of the power supply is adjusted to 150W. The distance between the target and the glass substrate The distance between them is 11 cm, and a 1.0 μm thick ZnO:Al transparent conductive electrode layer (TCO) 2-2 is deposited by sputtering under this process. Then put the glass substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 250°C. Evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3 Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 40W, and the distance between the target and the glass substrate is 11cm, under this process A 50 nm thick CdS n-type semiconductor layer 2-3 was deposited by sputtering. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the distance between the target and the glass substrate The distance between them is 11 cm, and a CdTe semiconductor layer 2-4 with a thickness of 600 nm is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. According to step 4, perform Cl treatment on the battery multilayer thin film structure, the Cl treatment temperature is 380° C., and the treatment time is 30 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber was heated to 250°C; the vacuum chamber was evacuated to less than 10 ^-4 Pa, the vacuum chamber was filled with argon gas to 2 Pa, the other flow rate was 100 sccm, the radio frequency power was turned on, and the output power of the power supply was adjusted to 60W. The distance between the Cd _1-x Mg _x Te target doped with Sb elements and the glass substrate 2-1 is 11 cm, and a 20 nm thick Sb-doped Cd _1-x Mg _x Te semiconductor layer 2- 5. Stop heating, then wait for the substrate covered with transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Mg _x Te semiconductor layer 2-5 to cool to room temperature, Remove from chamber. Then put the substrate 2-1 with transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd1 _{- xMgxTe} semiconductor layer 2-5 into the sputtering chamber chamber, and heated to 200°C; evacuate the vacuum chamber to less than 10 ^-4 Pa, fill the vacuum chamber with argon gas to 2Pa, turn the position of the substrate to the Al ₂ O ₃ : Zn target, and keep the pressure of the vacuum chamber at 2Pa , the output power of the RF power supply is 60W, and the distance between the target and the glass substrate is 11cm. Under this process, a 50nm thick Al ₂ O ₃ :Zn n ⁺ layer 2-6 is deposited by sputtering. So far, a substrate with a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, a CdTe semiconductor layer 2-4, a Cd _1-x Mg _x Te semiconductor layer 2-5, and an Al ₂ O ₃ : Structure of Zn n ⁺ layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Mg _x Te semiconductor layer 2-5 , Al ₂ O ₃ :Zn n ⁺ layers are taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait for the vacuum of the chamber to be below 10 ^-4 Pa, start to deposit Au metal electrode layer 2 with a thickness of 150nm on the surface of Al ₂ O ₃ :Zn n ⁺ layer 2-6 -7. So far, the preparation of the pin structure CdTe solar cell polycrystalline thin film cell is completed.

Example 7

First install the 99.999% high-purity SnO ₂ :F target on the target position of the magnetron sputtering equipment, and then send the glass substrate 2-1 cleaned with micro-90 according to step 1 into the magnetron sputtering equipment The vacuum chamber is heated to 300°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2Pa, the radio frequency power is turned on, and the output power of the power supply is adjusted to 120W, the target and the glass substrate The distance between them is 11 cm. Under this process, a 1.0 μm thick SnO ₂ :F transparent conductive electrode layer (TCO) 2-2 is deposited by sputtering. Then put the glass substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 250°C. Evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3 Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 40W, and the distance between the target and the glass substrate is 11cm, under this process A 50 nm thick CdS n-type semiconductor layer 2-3 was deposited by sputtering. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the distance between the target and the glass substrate The distance between them is 11 cm, and a CdTe semiconductor layer 2-4 with a thickness of 600 nm is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. According to step 4, perform Cl treatment on the battery multilayer thin film structure, the Cl treatment temperature is 380° C., and the treatment time is 30 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber is heated to 250°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, and the other flow rate is 100 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and target The distance to the glass substrate 2-1 is 11 cm, and a 50 nm thick Cd _1-x Zn _x Te semiconductor layer 2-5 is deposited by sputtering under this process. Stop heating, then wait for the substrate covered with transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 to cool to room temperature, Take it out of the chamber and put it into the vacuum chamber of electron beam and thermal evaporation. After the chamber is vacuumed below 10 ^-4 Pa, start to deposit Cu with a thickness of 20nm by electron beam, and then heat it in a rapid annealing furnace at 450℃. Diffusion for 1 min.

Then have substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5, Cd _1-x The substrate with Cu on the Zn _x Te semiconductor layer 2-5 is placed in a sputtering vacuum chamber and heated to 320°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, and the vacuum chamber is filled with argon to 2Pa , turn the position of the substrate to the Al ₂ O ₃ :Zn target, keep the pressure of the vacuum chamber at 2Pa, the output power of the RF power supply is 60W, and the distance between the target and the glass substrate is 11cm. Al ₂ O ₃ :Zn n ⁺ layers 2-6. So far, a substrate with substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5, Al ₂ O ₃ : Structure of Zn n ⁺ layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , Al ₂ O ₃ :Zn n ⁺ layers are taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait for the vacuum of the chamber to be below 10 ^-4 Pa, start to deposit Au metal electrode layer 2 with a thickness of 200nm on the surface of Al ₂ O ₃ :Zn n ⁺ layer 2-6 -7. So far, the preparation of the pin structure CdTe solar cell polycrystalline thin film cell is completed.

Example 8

First install the 99.999% high-purity Zn ₂ SnO ₄ target on the target position of the magnetron sputtering equipment, and then send the polyimide substrate 2-1 cleaned with micro-90 according to step 1 into the magnetron The vacuum chamber of the sputtering equipment is heated to 200°C; the vacuum chamber is evacuated to below 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 5 Pa, the radio frequency power is turned on, and the output power of the power supply is adjusted to 80W. The distance between the polyimide substrates was 11 cm, and a 1.0 μm thick Zn ₂ SnO ₄ transparent conductive electrode layer (TCO) 2-2 was deposited by sputtering under this process. Then put the mica substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 250°C. Evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 40W, and the distance between the target and the polyimide substrate is 11cm. In this process, a 70 nm thick CdS n-type semiconductor layer 2-3 is deposited by sputtering. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, the target and polyimide The distance between the substrates is 11 cm, and an 800 nm thick CdTe semiconductor layer 2-4 is sputter-deposited under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. Perform Cl treatment on the battery multilayer film structure according to step 4, the Cl treatment temperature is 300° C., and the treatment time is 120 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature.

Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber is heated to 250°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon and NH ₃ to 2Pa, the gas flow rate is 60 sccm, the radio frequency power is turned on, and the output power of the power supply is adjusted to 60W, the distance between the target and the polyimide substrate 2-1 is 11cm, under this process, a 20nm thick Cd _1-x Zn _x Te semiconductor layer 2-5 is deposited by sputtering. Then the position of the substrate 2-1 was turned to the In ₂ O ₃ :Sn target, the vacuum chamber pressure was maintained at 2Pa, the output power of the RF power supply was 60W, and the distance between the target and the polyimide 2-1 substrate was 11cm. In this process, a 50nm thick In ₂ O ₃ :Snn ⁺ reflection enhancing layer 2-6 was sputter deposited. So far, the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, the CdTe semiconductor layer 2-4, the Cd _1-x Zn _x Te semiconductor layer 2-5, and In ₂ O ₃ are obtained: Sn augments the structure of tunneling layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , In ₂ O ₃ : Sn anti-increasing tunneling layer 2-6 polycrystalline thin film take out chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait until the chamber is vacuumed below 10 ^-4 Pa, start to deposit Au metal electrode layer with a thickness of 50nm on the surface of In ₂ O ₃ : Snn ⁺ reflection enhancing layer 2-6 2-7. So far, the preparation of the pin structure CdTe solar cell polycrystalline thin film cell is completed.

Example 9

First install the 99.999% high-purity Cd ₂ SnO ₄ target on the target position of the magnetron sputtering equipment, and then send the mica substrate 2-1 cleaned with micro-90 according to step 1 into the magnetron sputtering equipment The vacuum chamber is heated to 200°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 5Pa, the RF power is turned on, and the output power of the power supply is adjusted to 180W, the target and the mica substrate The distance between them is 11 cm. Under this process, a 500 nm thick Cd ₂ SnO ₄ transparent conductive electrode layer (TCO) 2-2 is deposited by sputtering. Then put the mica substrate 2-1 deposited with the transparent conductive electrode layer 2-2 into the vacuum chamber of the magnetron sputtering equipment, and heat it to 250°C. Evacuate the vacuum chamber to below 10 ^-4 Pa, fill the vacuum chamber with argon gas to 3Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 40W, and the distance between the target and the mica substrate is 11cm, under this process A 20 nm thick CdS n-type semiconductor layer 2-3 was sputter deposited. Then turn the substrate to the position facing the CdTe target, start sputtering the CdTe semiconductor layer 2-4, fill the vacuum chamber with argon gas to 2Pa, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and the distance between the target and the mica substrate The distance between them is 11 cm, and a 100 nm thick CdTe semiconductor layer 2-4 is deposited by sputtering under this process. A solar cell multilayer film structure composed of a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, and a CdTe semiconductor layer 2-4 is made.

Stop heating the substrate 2-1, and when the temperature of the substrate 2-1 drops to room temperature, take out the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2. -4 solar cell multilayer thin film structure. According to step 4, perform Cl treatment on the battery multilayer thin film structure, the Cl treatment temperature is 500° C., and the treatment time is 5 minutes. After the Cl treatment process is completed, the solar cell multilayer film composed of the substrate 2-1, the transparent conductive electrode layer 2-2, the CdS n-type semiconductor layer 2-3, and the CdTe semiconductor layer 2-4 is cooled to room temperature. Then put the solar cell multilayer film made of substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4 into magnetron sputtering after Cl treatment The vacuum chamber is heated to 250°C; the vacuum chamber is evacuated to less than 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2 Pa, and the other flow rate is 100 sccm, turn on the radio frequency power supply, adjust the output power of the power supply to 60W, and target The distance from the mica substrate 2-1 is 11 cm, and a Cd _1-x Zn _x Te semiconductor layer 2-5 with a thickness of 20 nm is deposited by sputtering under this process. Stop heating, then wait for the substrate covered with transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 to cool to room temperature, Take it out from the chamber, put it into the vacuum chamber of electron beam and thermal evaporation, wait until the chamber is vacuumed below 10 ^-4 Pa, start to deposit 1nm thick Bi ₂ Se ₃ with electron beam.

Then diffuse in a rapid annealing furnace at 50 °C for 120 min. Then put the substrate with substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 into The sputtering vacuum chamber is heated to 100°C; the vacuum chamber is evacuated to below 10 ^-4 Pa, the vacuum chamber is filled with argon gas to 2Pa, and the position of the substrate is turned to In ₂ O ₃ : Sn, the vacuum chamber The pressure was maintained at 2Pa, the output power of the RF power supply was 60W, and the distance between the target and the mica substrate was 11cm. In this process, a 50nm-thick In ₂ O ₃ :Sn n ⁺ layer 2-6 was deposited by sputtering. So far, a substrate with a substrate 2-1, a transparent conductive electrode layer 2-2, a CdS n-type semiconductor layer 2-3, a CdTe semiconductor layer 2-4, a Cd _1-x Zn _x Te semiconductor layer 2-5, and an In ₂ O ₃ : Structure of Sn n ⁺ layers 2-6. After it is cooled to room temperature, put the substrate 2-1, transparent conductive electrode layer 2-2, CdS n-type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd _1-x Zn _x Te semiconductor layer 2-5 , In ₂ O ₃ :Sn n ⁺ layers are taken out of the chamber. Put it into the vacuum chamber of electron beam and thermal evaporation, wait until the chamber is vacuumed below 10 ^-4 Pa, start to deposit Au metal electrode layer 2 with a thickness of 5nm on the surface of In ₂ O ₃ :Sn n ⁺ layer 2-6 -7. So far, the preparation of the pin structure CdTe solar cell polycrystalline thin film cell is completed.

Claims (10)

1. a p-i-n structure C dTe solar cell, it is characterized in that, described p-i-n structure C dTe battery comprises substrate (2-1), transparency conductive electrode layer (2-2), CdS N-shaped semiconductor layer (2-3), CdTe intrinsic light absorbing zone (2-4), the broad-band gap ternary II-VI semiconductor p of family ⁺layer (2-5), ZnO:Al or In ₂o ₃: Sn n ⁺layer (2-6), metal electrode layer (2-7); On described substrate (2-1), be that transparency conductive electrode layer (2-2), transparency conductive electrode layer (2-2) are above CdS N-shaped semiconductor layer (2-3), CdS N-shaped semiconductor layer (2-3) is upper is CdTe intrinsic light absorbing zone (2-4), and CdTe intrinsic light absorbing zone (2-4) is upper is the broad-band gap ternary II-VI semiconductor p of family ⁺layer (2-5), the broad-band gap ternary II-VI semiconductor p of family ⁺layer (2-5) is upper is ZnO:Al or In ₂o ₃: Sn n+ increases anti-tunnelling (2-6), ZnO:Al or In layer by layer ₂o ₃: it is metal electrode layer (2-7) that Sn n+ increases anti-tunnel layer (2-6) upper; The described broad-band gap ternary II-VI semiconductor p of family ⁺layer (2-5) is Cd _1-xzn _xte or Cd _1-xmg _xte.

2. the preparation method of p-i-n structure C dTe battery claimed in claim 1, is characterized in that, described preparation method is magnetron sputtering method, and concrete steps are:

(1) clean substrate (2-1);

(2) at the upper growth of substrate (2-1) transparency conductive electrode layer (2-2);

(3) on transparency conductive electrode layer (2-2), grow successively CdS N-shaped semiconductor layer (2-3) and CdTe intrinsic light absorption semiconductor layer (2-4);

(4) described having CdCl ₂in the atmosphere of steam, CdS N-shaped semiconductor layer (2-3) and the CdTe intrinsic light absorption semiconductor layer (2-4) of step 3 preparation are carried out to annealing in process; Through CdCl ₂on CdTe intrinsic light absorption semiconductor layer (2-4) after annealing in process, deposit successively broad-band gap II-VI semiconductor p ⁺layer (2-5) and ZnO:Al or In ₂o ₃: Sn n ⁺increase and instead then wear layer (2-6);

(5) in magnetron sputtering process, pass into Ar gas, in Ar gas, sneak into the gas containing N and P; At the semiconductor p of broad-band gap II-VI family ⁺layer (2-5) mixes nitrogen or phosphorus, or the mode of diffusion after adopting is at the semiconductor p of broad-band gap II-VI family ⁺in layer, mix copper or phosphorus or dysprosium or bismuth;

(6) at ZnO:Al or In ₂o ₃: Sn n ⁺increase and instead then wear layer (2-6) surface deposition metallic conduction electrode layer (2-7);

So far make the CdTe solar cell of described p-i-n structure.

3. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, in described step (2), transparency conducting layer is In ₂o ₃: Sn or ZnO:Al or ZnO:B or In ₂o ₃: Mo or In:ZnO or Graphene or SnO ₂: F or Cd ₂snO ₄, the thickness of described transparency conductive electrode layer is 0.3-1500nm.

4. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, the method of operation of described step 3 is: the substrate of having prepared transparency conductive electrode layer is put in the position of placing substrate at magnetron sputtering stove, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and intensification makes underlayer temperature remain on 25-600 ℃; When back end vacuum arrives 10 ^-3below Pa, start sputter CdS semiconductor layer; The sputtering condition of CdS semiconductor layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering furnace chamber pressure 0.1-10Pa in magnetron sputtering furnace chamber; When the thickness of the CdS semiconductor layer of institute's sputter is 10-100nm on substrate, stop the preparation of CdS semiconductor layer, substrate is turned to over against the position of CdTe target, start sputter CdTe semiconductor layer; The sputtering condition of CdTe semiconductor layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering furnace chamber pressure 0.1-10Pa in magnetron sputtering furnace chamber; When the CdTe semiconductor layer thickness of institute's sputter on substrate reaches the thickness 0.1-1 μ m of setting, stop the preparation of CdTe semiconductor layer, stop, to substrate heating, when underlayer temperature is reduced to room temperature, taking out the substrate that has deposited CdS and CdTe semiconductor layer simultaneously.

5. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, described step 4 is at CdCl ₂in atmosphere, the CdS of preparation and CdTe semiconductor layer are carried out annealing method and are, at 300-500 ℃ to CdSn type semiconductor layer and CdTe intrinsic light absorption semiconductor layer annealing in process 5-120min; Annealing adopts wet method or dry method; The technical process of wet method annealing is as follows: CdCl ₂saturated methanol solution evenly drop on CdTe intrinsic light absorption semiconductor layer, CdTe intrinsic light absorption semiconductor layer is carried out to annealing in process.The technical process of dry method annealing is as follows: CdCl ₂evenly be placed on sheet glass, then apart from this sheet glass 1-5mm place, placing the substrate with CdTe intrinsic light absorption semiconductor layer, CdSn type semiconductor layer and transparency conductive electrode layer, CdTe half intrinsic light absorption conductor layer is over against there being CdCl ₂sheet glass, then CdSn type semiconductor layer and CdTe intrinsic light absorption semiconductor layer are carried out to annealing in process.

6. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, the method of operation of described step 5 is: on the position of magnetron sputtering stove placement substrate, put the substrate that is coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and heat up make to there is transparency conductive electrode layer, the underlayer temperature of CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone remains on the scope of 25-600 ℃; When back end vacuum arrives 10 ^-3below Pa, start the sputter broad-band gap ternary II-VI semiconductor p of family ⁺layer; The broad-band gap ternary II-VI semiconductor p of family ⁺the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar or Ar and N in magnetron sputtering chamber ₂, or Ar and PH ₃, gas flow rate 10-100sccm, chamber pressure 0.1-10Pa; As the broad-band gap ternary II-VI semiconductor p of family ⁺when the thickness of layer is 1-100nm, stop the broad-band gap ternary II-VI semiconductor p of family ⁺the preparation of layer; Or the complete broad-band gap ternary of the sputter II-VI semiconductor p of family ⁺after layer, being coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, the broad-band gap ternary II-VI semiconductor p of family ⁺the substrate of layer takes out, and then passes through electron beam or thermal evaporation at the broad-band gap ternary II-VI semiconductor p of family ⁺cu or P or the Sb of growth 1-20nm on layer ₂te ₃or Bi ₂te ₃, then in quick anneal oven, 50-600 ℃ of temperature range, to spread, the time of diffusion is 0.1-120min; Substrate is turned to over against ZnO:Al or In ₂o ₃: the position of Sn target, starts sputter ZnO:Al or In ₂o ₃: Snn ⁺layer; ZnO:Al or In ₂o ₃: Sn n ⁺the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering chamber pressure 0.1-10Pa in magnetron sputtering chamber; ZnO:Al or the In of institute's sputter on substrate ₂o ₃: Sn n ⁺when the thickness of layer reaches the thickness 1-100nm of setting, stop ZnO:Al or In ₂o ₃: Sn n ⁺the preparation of layer stops, to substrate heating, when underlayer temperature is reduced to room temperature, taking out substrate simultaneously.

7. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, in described step 5, on the position of magnetron sputtering stove placement substrate, put the substrate that is coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and heat up make to there is transparency conductive electrode layer, the substrate temperature of CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone remains on 25-600 ℃; When back end vacuum arrives 10 ^-3below Pa, start the sputter broad-band gap ternary II-VI semiconductor p of family ⁺layer; The broad-band gap ternary II-VI semiconductor p of family ⁺the sputtering condition of layer is: target is the broad-band gap ternary II-VI family semiconductor layer that mixes the materials such as Cu or P or Sb or Bi, such as: Cd _1-xzn _xte or Cd _1-xmg _xte, underlayer temperature 25-600 ℃ passes into high-purity Ar gas flow rate 10-100sccm, chamber pressure 0.1-10Pa in magnetron sputtering chamber; As the broad-band gap ternary II-VI semiconductor p of family ⁺when the thickness of layer is 1-100nm, stop the broad-band gap ternary II-VI semiconductor p of family ⁺the preparation of layer; Substrate is turned to over against ZnO:Al or In ₂o ₃: the position of Sn target, starts sputter ZnO:Al or In ₂o ₃: Sn n ⁺layer; ZnO:Al or In ₂o ₃: Sn n ⁺the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering chamber pressure 0.1-10Pa in magnetron sputtering chamber; ZnO:Al or the In of institute's sputter on substrate ₂o ₃: Sn n ⁺when the thickness of layer reaches the thickness 1-100nm of setting, stop ZnO:Al or In ₂o ₃: Sn n ⁺the preparation of layer stops, to substrate heating, when underlayer temperature is reduced to room temperature, taking out substrate simultaneously.

8. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, the method for operation of described step 6 is: by thermal evaporation or electron beam at ZnO:Al or In ₂o ₃: Sn n ⁺layer increases instead wears the metal electrode layer that layer upper evaporation thickness is greater than 5nm then, and the thickness of metal electrode layer records by quartz crystal.

9. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, adopt the method for magnetron sputtering to prepare N-shaped CdS semiconductor layer, intrinsic CdTe light absorbing zone, broad-band gap ternary II-VI semiconductor p ⁺layer; Magnetically controlled sputter method can obtain the CdS/CdTe interface of porous, before light enters CdTe absorbed layer, is scattered, and increases the light path of light in CdTe absorbed layer, reaches the effect that falls into light; At the broad-band gap ternary II-VI semiconductor p of family ⁺the n inserting between layer and metal electrode layer ⁺type ZnO:Al or In ₂o ₃: layer is instead worn in Sn increasing then can play light trapping effect.

10. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, described substrate is rigid substrate, or flexible substrate.