CN104064474B - Fin structure manufacturing method of double patterned fin transistor - Google Patents

Abstract

The invention discloses a kind of fin structure manufacture method of Dual graphing fin transistor; the second silicon nitride layer is protected using silica is deposited; the thickness loss of the second silicon nitride layer will not be caused when then removing nitrogen-free anti-reflecting layer at the top of the second amorphous carbon layer; avoid pattern caused by existing method and critical size control problem; so as to expand subsequent patterning process window; the control of the critical size and pattern of fin structure is more beneficial for, realizes the raising of device electric property index.

Description

Fin structure manufacturing method of double patterned fin transistor

technical field

The invention relates to the technical field of manufacturing technology of semiconductor integrated circuits, in particular to a method for manufacturing a fin structure of a double patterned fin transistor using sidewall self-alignment.

Background technique

According to the prediction of the international semiconductor technology roadmap development blueprint, in order to follow Moore's law and obtain the required short channel effect, improve the control of the gate to the channel, a new transistor structure is proposed, that is, the fin field effect transistor FinFET (Fin Field Effect Transistor, referred to as fin transistor). The formation of the fins in the active area is a very challenging process, because the fin field effect transistors at 22nm and below have a fin width of about 10-15nm, and such a small pattern size has exceeded the current immersion photonics. The resolution limit of the engraving machine, for this reason, it is necessary to use side wall self-alignment double patterning technology to achieve. That is, firstly, a sacrificial core pattern (sacrificial core pattern) is generated by immersion lithography and etching technology on the silicon wafer on which various mask materials have been deposited, and then deposited on the core pattern by atomic layer deposition technology. A layer of spacer material, and then anisotropic dry etching is used to form sidewalls, and then the sacrificial core pattern is removed, thus forming a fin (FIN) mask pattern with half the required pitch (pitch) , where the width of the FIN hard mask is determined by the thickness of the atomic deposition layer, and then the hard mask pattern is used as the protective layer to continue etching to form the fin (FIN) of the fin field effect transistor.

1A to FIG. 1H show the existing method of forming fins with sidewall self-alignment double pattern. specifically:

First, as shown in FIG. 1A, on a silicon substrate 101 of a semiconductor active device, a silicon dioxide insulating layer 102, a silicon nitride layer 103, a first layer of amorphous carbon layer 104, A silicon nitride etch stop layer 105 , a second layer of amorphous carbon layer 106 and a nitrogen-free anti-reflection layer 107 . Wherein, the silicon nitride layer 103 is an etching hard mask for the formation of the final fin structure.

Then, as shown in FIG. 1B , an organic anti-reflection layer 108 and a photoresist 109 are spin-coated on top of the layer 107 , and then a core layer (core layer) photolithography is performed.

Next, as shown in Figure 1C, the sacrificial core layer line pattern of the second amorphous carbon layer 106 is formed by dry etching using the photoresist 109 as a mask, so far the amorphous carbon sacrificial core pattern and the nitrogen-free nitrogen layer on the top have been formed. Anti-reflection layer 107. The amorphous carbon sacrificial core pattern lines formed here cannot form a completely vertical sidewall morphology due to process limitations, and damage caused by etching may occur near the top of the second amorphous carbon layer 106 in the pattern; The damage will lead to changes in the morphology of the subsequent sidewall isolation hard mask near the amorphous carbon side, thus affecting the subsequent pattern definition.

After a corresponding cleaning process, as shown in FIG. 1D , a silicon oxide thin film hard mask layer 110 is deposited on the amorphous carbon sacrificial core pattern and the nitrogen-free anti-reflection layer 107 .

As shown in FIG. 1E , the silicon oxide thin film hard mask layer is etched using an anisotropic dry method, and stops above the silicon nitride etch stop layer 105 to form silicon oxide spacers 110 .

After that, as shown in FIG. 1F , the nitrogen-free anti-reflective layer 107 on the top of the line pattern of the sacrificial core layer is removed by plasma dry etching process, so that the amorphous carbon of the sacrificial core layer under the nitrogen-free anti-reflective layer 107 is exposed. In this step, since the etching stop layer 105a is also exposed to plasma during the process of removing the nitrogen-free anti-reflection layer 107, the etching stop layer 105a will be lost in this step.

As shown in FIG. 1G , the sacrificial core layer is removed by a dry stripping process, so that the underlying etch stop layer 105 b is exposed. At this time, the thicknesses of the etch stop layers 105a and 105b are different due to the different times of exposure to the plasma. The film thickness at the etch stop layer 105a continues to decrease, while the film thickness at the etch stop layer 105b Still remaining unchanged, the further enlargement of the difference in thickness between the two will result in a further enlargement of the final topography difference between the inner and outer sidewalls after the silicon oxide sidewall 110 hard mask lines are used for pattern transfer.

As shown in FIG. 1H , continue to use dry etching to use the silicon dioxide sidewall 110 hard mask as a mask to remove the silicon nitride etch stop layer 105, the first amorphous carbon layer 104 and the bottommost The silicon nitride layer 103 forms a silicon nitride hard mask 113 line pattern whose pitch is halved, and the etching stops above the silicon dioxide insulating layer 102 .

After the necessary wet cleaning process is completed, as shown in FIG. 1I, the fin line top cutting photolithography process is carried out, that is, the photolithography planarization layer 114, the photolithography anti-reflection layer 115 and the silicon nitride hard mask 113 are spin-coated. The photoresist layer 116 is exposed and developed to form the pattern to be cut.

As shown in FIG. 1J, the silicon nitride lines to be cut are removed by using a dry etching process using the photoresist 116, the photolithographic anti-reflection layer 115 and the flat layer 114 as a mask, and the etching stops at the silicon dioxide insulating layer. 102 on. Afterwards, the amorphous carbon hard mask above the silicon nitride hard mask 113 is removed by a dry stripping process, so that the silicon nitride hard mask 113 layer is completely exposed.

After that, as shown in FIG. 1K and FIG. 1L , using the silicon nitride hard mask 113 as a hard mask, the silicon dioxide insulating layer 102 and the silicon substrate 101 are etched to form fin structures 117 .

In summary, the existing methods for forming fish fin structures have the following defects:

1. During the APF etching process of the sacrificial core pattern, it is difficult for the core layer pattern to form lines with high verticality (close to 90 degrees), because if the verticality of the sidewall of the core layer pattern is not straight enough, it will make the subsequent sidewall hard mask The inner wall forms an inclined angle (less than 90 degrees) along the shape of the side wall of the core layer, and at the same time forms an inverted trapezoidal side wall shape on the inner side of the side wall, which will affect the shape of the subsequent graphics during the subsequent graphics transfer. The appearance and the control of critical dimensions of subsequent patterns, such as the inclined silicon nitride hard mask lines in Figure 1H. The fin shape and critical dimensions are crucial to the definition of the electrical performance of FinFETs.

2. After the silicon oxide sidewall dry etching is completed, the sacrificial core layer pattern needs to be removed. Generally, due to the need for patterning, there is a nitrogen-free anti-reflective layer (NFDARC) on the top of the sacrificial core layer. Therefore, in order to remove the sacrificial core layer APF, it is necessary to remove the nitrogen-free anti-reflective layer on the top first, while not having any negative impact on the generated sidewall hard mask pattern, and causing minimal damage to the exposed substrate film ; If an over-etch (OE) is applied directly after the sidewall dry etching step to remove the nitrogen-free anti-reflective layer, it will cause the loss of the medium below the outside of the sidewall, resulting in the removal of the core layer. The thickness of the dielectric substrate material is much greater than the thickness of the position outside the sidewall that was not originally covered by the core layer. Therefore, when the sidewall is used as a mask to transfer graphics down, it will cause morphology and critical dimension control problems, and at the same time May damage the topography of the side wall or the height of the side wall.

Contents of the invention

The purpose of the present invention is to make up for the above-mentioned deficiencies in the prior art, to provide a method for manufacturing a fin structure of a double-patterned fin transistor, so as to avoid the loss of the etch stop layer when removing the nitrogen-free anti-reflection layer, and reduce the loss due to the sacrificial core The influence of layer sidewall inclination on subsequent graphics, thereby controlling the morphology and key dimensions of the fin structure, and improving the electrical performance index of the device.

In order to achieve the above object, the present invention provides a method for manufacturing a fin structure of a double-patterned fin transistor, which includes the following steps:

Step S01, providing a semiconductor device substrate, and sequentially depositing a first silicon dioxide layer, a first silicon nitride layer, a first amorphous carbon layer, and a second silicon nitride layer on the substrate from bottom to top , a second amorphous carbon layer and an antireflection layer;

Step S02, coating photoresist on the top anti-reflection layer, and completing the photolithography step of the core sacrificial layer pattern through the exposure and development process;

Step S03, using photoresist as a mask to etch the anti-reflection layer and the second amorphous carbon layer to form a core sacrificial layer pattern with the second amorphous carbon layer and its top anti-reflection layer;

Step S04, depositing a second silicon dioxide layer on the core sacrificial layer pattern;

Step S05, etching and removing the second silicon dioxide layer on the top of the core sacrificial layer pattern to expose the anti-reflection layer, while retaining the second silicon dioxide layer on both sides of the core sacrificial layer pattern;

Step S06, etching and removing the anti-reflection layer on the top of the core sacrificial layer pattern;

Step S07, etching and removing the second silicon dioxide layer;

Step S08, depositing a third silicon dioxide layer on the core sacrificial layer pattern;

Step S09, using anisotropic etching on the third silicon dioxide layer to expose the second amorphous carbon layer in the core sacrificial layer pattern, forming the silicon dioxide sidewall of the core sacrificial layer pattern, and then removing the core sacrificial layer pattern the second amorphous carbon layer within;

Step S10, using the silicon dioxide sidewall as a mask to etch the second silicon nitride layer, the first amorphous carbon layer and the first silicon nitride layer to form hard mask lines with silicon nitride at the bottom, and removing the first amorphous carbon layer above the first silicon nitride layer in the hard mask line;

Step S11 , using the silicon nitride lines formed by the first silicon nitride layer in the hard mask lines as a mask to etch the first silicon dioxide layer and the substrate to form fin structures.

Further, step S03 is dry etching, step S05 is plasma dry reverse etching (etchback), step S06 is dry etching, step S07 is wet etching, and silicon dioxide is formed in step S09 The sidewalls are etched using anisotropic plasma dry method. In step S09, removing the second amorphous carbon layer in the pattern of the core sacrificial layer is a glue removal process. In step S10, forming hard mask lines is using anisotropic plasma. Bulk dry etching, removing the amorphous carbon above the silicon nitride in the second hard mask line in step S10 is a glue removal process, and step S11 is dry etching.

Further, step S06 also includes over-etching to remove part of the second amorphous carbon layer under the anti-reflection layer.

Further, the anti-reflection layer includes a lower nitrogen-free anti-reflection layer and an upper layer anti-reflection layer.

Further, step S04 is to spin-coat the second silicon dioxide layer.

Further, the etching gas medium in step S05 is CF ₄ or a mixed gas of CF ₄ and Ar.

Further, the flow rate of the CF ₄ is 50 sccm-200 sccm, the flow rate of the Ar is 50 sccm-300 sccm, the power of the radio frequency source is 200 watts to 700 watts, the bias voltage is 50 volts to 400 volts, and the air pressure is 5 millitorr to 12 millitorr .

Further, in step S10 , the pitch of the silicon nitride lines in the hard mask lines is halved.

Further, steps S10 and S11 also include, step S101, sequentially coating a carbon hard mask layer, a silicon-containing anti-reflection layer, and photoresist on the silicon nitride lines, and through the exposure and development process, the photoresist The pattern to be cut is made on the above; step S102, the silicon nitride line to be cut is removed by dry etching, and the amorphous carbon above the remaining silicon nitride line is removed by a dry stripping process to expose the silicon nitride line.

Further, the anti-reflection layer is a nitrogen-free anti-reflection layer.

The method for manufacturing the fin structure of the double-patterned fin transistor provided by the present invention utilizes deposited silicon dioxide to protect the second silicon nitride layer, so that no nitrogen-free anti-reflection layer at the top of the second amorphous carbon layer is removed. It will cause the thickness loss of the second silicon nitride layer, avoid the shape and critical dimension control problems caused by the existing method, thereby expanding the subsequent patterning process window, and more conducive to the critical dimension and shape of the fin structure. control, and realize the improvement of the electrical performance index of the device.

Description of drawings

In order to understand the purpose, features and advantages of the present invention more clearly, preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

Fig. 1A-Fig. 1L are the schematic diagrams of each step of the existing method for forming double pattern fins;

2 is a schematic flow diagram of a method for manufacturing a fin structure of a double-patterned fin transistor of the present invention;

3A-3N are schematic diagrams of each step of the manufacturing method of the present invention.

detailed description

Please refer to FIG. 2 and FIG. 3A to FIG. 3N at the same time. The method for manufacturing the fin structure of the double-patterned fin transistor in this embodiment includes the following steps:

In step S01, as shown in FIG. 3A, a semiconductor device substrate 201 is provided, and a first silicon dioxide layer 202, a first silicon nitride layer 203, a first non- The crystalline carbon layer 204 , the second silicon nitride layer 205 , the second amorphous carbon layer 206 and the nitrogen-free anti-reflection layer 207 .

Step S02, as shown in FIG. 3B, deposits an organic anti-reflection layer 208 on the top nitrogen-free anti-reflection layer 207, and coats a photoresist 209 on the organic anti-reflection layer 208. Through the exposure and development process, the photoresist 209, the pattern of the core sacrificial layer to be prepared is produced, and the photolithography step of the pattern of the core sacrificial layer is completed.

Step S03, as shown in FIG. 3C, etching the organic anti-reflection layer 208, the nitrogen-free anti-reflection layer 207 and the second amorphous carbon layer 206 with the photoresist 209 as a mask, and finally forming the second amorphous carbon layer 206 And the core sacrificial layer pattern of the nitrogen-free anti-reflection layer 207 on the top.

Wherein, this step is dry etching, and conventional means in the art and gas medium can be used.

Step S04 , as shown in FIG. 3D , spin-coating a second silicon dioxide layer 210 on the core sacrificial layer pattern. The thickness of the second silicon dioxide layer 210 is preferably slightly greater than the top of the nitrogen-free anti-reflection layer 207 .

Step S05, as shown in FIG. 3E, etching and removing the second silicon dioxide layer 210 on the top of the core sacrificial layer pattern to expose the nitrogen-free anti-reflection layer 207, while retaining the second silicon dioxide layer on both sides of the core sacrificial layer pattern 210.

Wherein, this step is reverse etching by plasma dry method, and the etching gas is preferably CF ₄ or a mixed gas of CF ₄ and Ar, wherein the flow rate of CF ₄ is 50 sccm-200 sccm, and the flow rate of Ar is 50 sccm-300 sccm, The power of the radio frequency source is 200 watts to 700 watts, the bias voltage is 50 volts to 400 volts, and the air pressure is 5 millitorr to 12 millitorr.

Step S06 , as shown in FIG. 3F , etching and removing the nitrogen-free anti-reflection layer 207 on the top of the core sacrificial layer pattern.

Wherein, this step is dry etching, and conventional methods and gases in this field can be used. Wherein, step S06 also preferably includes over-etching to remove part of the second amorphous carbon layer under the anti-reflection layer. Remove the damage layer caused by etching on the top of the second amorphous carbon layer, which can adjust the height of the second amorphous carbon layer to expand the critical dimension of the top and avoid the critical dimension of the top being too small due to insufficient verticality It is more conducive to the transmission of subsequent graphics.

Step S07 , as shown in FIG. 3G , etching and removing the spin-coated second silicon dioxide layer 210 .

Wherein, this step is wet etching, and conventional methods and media in this field can be used. This step uses wet etching to remove the remaining spin-coated silicon dioxide, which can maintain a higher etching selectivity, and will not cause the second amorphous carbon layer 206 in the core sacrificial layer pattern and the second amorphous carbon layer 206 on both sides of the core sacrificial layer pattern. The silicon nitride layer 205 is lost to ensure the morphology and critical dimensions of subsequent patterns.

Step S08 , as shown in FIG. 3H , depositing a third silicon dioxide layer 211 on the core sacrificial layer pattern.

In step S09, as shown in FIG. 3I, the third silicon dioxide layer 211 is anisotropically etched to expose the second amorphous carbon layer 206 of the core sacrificial layer pattern, and form silicon dioxide sidewalls 218 of the core sacrificial layer pattern, Afterwards, the second amorphous carbon layer 206 in the core sacrificial layer pattern is removed, that is, the entire core sacrificial layer pattern has been removed.

Among them, the formation of silicon dioxide sidewalls in this step is to use anisotropic plasma dry etching, and conventional methods and gases in this field can be used; removing the second amorphous carbon layer of the core sacrificial layer is a glue removal process, which can be Use conventional means and gas medium in this field.

In step S10, as shown in FIG. 3J, the second silicon nitride layer 205, the first amorphous carbon layer 204, and the first silicon nitride layer 203 are etched using the silicon dioxide sidewall 218 as a mask to form a nitride layer at the bottom. A hard mask line of amorphous carbon is formed above the silicon and silicon nitride, and the first amorphous carbon layer above the first silicon nitride layer in the hard mask line is removed.

Among them, forming the hard mask lines in this step is to use anisotropic plasma dry etching, and conventional methods and gases in this field can be used; removing the amorphous carbon above the silicon nitride in the hard mask lines is a deglue process, Conventional means and gases in this field can be used.

Wherein, the pitch of the silicon nitride lines in the hard mask lines formed after this step is halved.

Step S11, as shown in FIG. 3M , using the silicon nitride line formed by the first silicon nitride layer in the hard mask line as a mask to etch the first silicon dioxide layer 202 and the silicon substrate 201 to form a fin structure, The two sidewalls 216 and 217 of the silicon groove 215 of the fin structure are symmetrical, and the critical dimension is uniform.

Wherein, this step is dry etching, and conventional methods and gases in this field can be used.

In practical applications, it is necessary to perform a top-cutting process on the fin lines. Steps S10 and S11 also include step S101, as shown in FIG. 3K, sequentially coating the silicon nitride lines formed by the first silicon nitride layer Carbon hard mask layer 212, silicon-containing anti-reflection layer 213 and photoresist 214, through the exposure and development process, make the pattern to be cut on the photoresist 214; step S102, as shown in Figure 3L, use dry etching The silicon nitride lines formed by the first silicon nitride layer that need to be cut are removed by etching, and the amorphous carbon above the remaining silicon nitride lines is removed by a dry stripping process to expose the silicon nitride lines. The fin structure formed in the final step S09 is shown in FIG. 3N .

Claims (9)

1. a kind of fin structure manufacture method of Dual graphing fin transistor, it is characterised in that it comprises the following steps：

Step S01, there is provided semiconductor device substrate, and deposit successively from bottom to top over the substrate the first silicon dioxide layer, First silicon nitride layer, the first amorphous carbon layer, the second silicon nitride layer, the second amorphous carbon layer and anti-reflecting layer；

Step S02, the coating photoresist on top layer anti-reflecting layer, by exposure imaging technique, complete core and sacrifice layer pattern light Carve step；

Step S03, using photoresist as mask etching anti-reflecting layer and the second amorphous carbon layer, formed with the second amorphous carbon layer and The core of its top anti-reflective layer sacrifices layer pattern；

Step S04, sacrificed in the core and one layer of second silicon dioxide layer is deposited above layer pattern；

Step S05, etching remove the second silicon dioxide layer at the top of core sacrifice layer pattern, to expose anti-reflecting layer, and protected Core is stayed to sacrifice the second silicon dioxide layer of layer pattern both sides；

Step S06, etching remove the anti-reflecting layer at the top of core sacrifice layer pattern；

Step S07, etching remove second silicon dioxide layer；

Step S08, sacrificed in the core and one layer of the 3rd silicon dioxide layer is deposited above layer pattern；

Step S09, using the silicon dioxide layer of anisotropic etching the 3rd, expose the second amorphous carbon in core sacrifice layer pattern Layer, the silicon dioxide side wall that core sacrifices layer pattern is formed, afterwards, remove the second amorphous carbon layer in core sacrifice layer pattern；

Step S10, using the silicon dioxide side wall as mask etching second silicon nitride layer, the first amorphous carbon layer and the first nitridation Silicon layer, form bottom and be the hard mask lines of silicon nitride, and remove in the hard mask lines first above the first silicon nitride layer Amorphous carbon layer；

Step S11, the silicon nitride lines formed using the first silicon nitride layer in the hard mask lines is mask etchings the one or two Silicon oxide layer and substrate, form fin structure.

2. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterised in that：Step S03 is dry etching, and for step S05 reversely to be etched using plasma dry, step S06 is dry etching, and step S07 is wet Method etches, and it is to utilize anisotropic plasma dry etch that silicon dioxide side wall is formed in step S09, in step S09 It is degumming process to sacrifice the second amorphous carbon layer in layer pattern except core, formed in step S10 hard mask lines for utilization it is each to The plasma dry etch of the opposite sex, removes in the second hard mask lines that amorphous carbon is work of removing photoresist above silicon nitride in step S10 Skill, step S11 are dry etching.

3. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：Step S06 also includes over etching, to remove the amorphous carbon layer of part second below anti-reflecting layer.

4. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：This is anti- Reflecting layer includes lower floor's nitrogen-free anti-reflecting layer and upper strata organic antireflection layer, and step S03 core, which is sacrificed at the top of layer pattern, is Nitrogen-free anti-reflecting layer.

5. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：Step S04 is the silicon dioxide layer of spin coating second.

6. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：Step S05 etching gas medium is CF₄Or CF₄With Ar mixed gas.

7. the fin structure manufacture method of Dual graphing fin transistor according to claim 6, it is characterised in that：The CF₄ Flow be 50sccm~200sccm, the flow of the Ar is 50sccm~300sccm, and RF source power is 200 watts~700 watts, Bias as 50 volts~400 volts, air pressure is the millitorr of 5 millitorrs~12.

8. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterised in that：Step Silicon nitride lines pitch in S10 in hard mask lines halves.

9. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterised in that：Step Also include between S10 and S11, step S101, carbon hard mask is coated with successively on the silicon nitride lines that the first silicon nitride layer is formed Layer, siliceous anti-reflecting layer and photoresist, by exposure imaging technique, produce the figure to be cut off on a photoresist；Step Rapid S102, the silicon nitride lines for needing the first silicon nitride layer cut off to be formed are removed using dry etching, and removed photoresist using dry method Technique removes the amorphous carbon above remaining silicon nitride lines, exposes silicon nitride lines.