CN104051450B - Semiconductor package - Google Patents

Abstract

The present invention provides a semiconductor package, including a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first component attachment surface and a first bump attachment surface relative to the first component attachment surface. The second semiconductor package is bonded to the first component attachment surface of the first semiconductor package, and includes a second substrate, a dynamic random access memory component, a decoupling capacitor, and a plurality of conductive structures. The second substrate has a second component attachment surface and a second bump attachment surface relative to the second component attachment surface. The dynamic random access memory component is fixedly connected to the second component attachment surface. The decoupling capacitor is fixedly connected to the second component attachment surface. A plurality of conductive structures are arranged on the second bump attachment surface and connected to the first component attachment surface. The semiconductor package disclosed by the present invention can enable the first semiconductor package and the second semiconductor package in the semiconductor package to maintain the original package size without the need to provide additional area for the decoupling capacitor.

Description

semiconductor packaging

technical field

The present invention relates to a semiconductor package, in particular to a package on package (POP) semiconductor package.

Background technique

A package on package (POP) semiconductor package is an integrated circuit package that vertically combines a system-on-chip (SOC) package and a memory package (memory package). In the package-on-package semiconductor package, two or more packages can be stacked on each other through a standard interface to transmit signals between the two. Package-on-package semiconductor packaging can increase the component density of devices such as mobile phones, personal digital assistants, and digital cameras.

Due to the increased number of input/output (I/O) connections of the bottom SoC package of the package-on-package semiconductor package, the height between the memory package on the top and the SoC package on the bottom will be limited. Therefore, it is difficult to design additional electronic components in the traditional package-on-package semiconductor package to enhance the performance of the SoC package.

Therefore, there is a need in the art for an improved package-on-package semiconductor package.

Contents of the invention

In view of this, the object of the present invention is to provide an improved semiconductor package.

An embodiment of the invention provides a semiconductor package. The semiconductor package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first component attaching surface and a first bump attaching surface opposite to the first component attaching surface. The second semiconductor package is bonded to the first component attaching surface of the first semiconductor package, and includes a second substrate, a dynamic random access memory component, a decoupling capacitor and a plurality of conductive structures. The second base has a second component attaching surface and a second bump attaching surface opposite to the second component attaching surface. The dynamic random access memory element is fixed on the second element attaching surface. The decoupling capacitor is fixedly connected to the attaching surface of the second component. A plurality of conductive structures are disposed on the second bump attachment surface and connected to the first component attachment surface.

Another embodiment of the present invention provides a semiconductor package. The semiconductor package includes a base, a dynamic random access memory package and an external power supply. The dynamic random access memory package is bonded to the base, wherein the dynamic random access memory package includes: a substrate; a dynamic random access memory element fixed on the substrate; and a decoupling capacitor fixed connected to the substrate and separated from the dynamic random access memory element. The external power supply is arranged on the base and separated from the package of the DRAM.

Yet another embodiment of the present invention provides a semiconductor package. The semiconductor package includes: a base; a system-on-a-chip package bonded to the base; a memory package bonded to the system-on-a-chip package, wherein the memory package includes a decoupling capacitor fixedly connected to the memory package; And an external power supply is arranged on the base and separated from the system one chip package.

The semiconductor package disclosed in the present invention can provide additional decoupling capacitors, and can maintain the original package size of the system-on-chip package and the memory package in the semiconductor package without requiring additional area for the decoupling capacitors.

Various objects of the present invention will be apparent to those skilled in the art who have read the following preferred embodiments shown by the accompanying drawings and contents.

Description of drawings

FIG. 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a top view of a semiconductor package according to an embodiment of the present invention.

detailed description

Certain terms are used in the claims and description to refer to particular components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The claims and description do not use the difference in names as the way to distinguish components, but use the difference in function of the components as the criterion for distinguishing. The "comprising" mentioned in the claims and the specification is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. .

In order to make the objects, features, and advantages of the present invention more comprehensible, the following specific examples are given together with accompanying drawings for a detailed description. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, not for limiting the present invention. In addition, part of the symbols in the figures in the embodiments are repeated for the purpose of simplifying the description, and do not imply the relationship between different embodiments.

FIG. 1 is a cross-sectional view of a semiconductor package 500 according to an embodiment of the present invention. FIG. 2 is a top view of a semiconductor package 500 according to an embodiment of the invention. In this embodiment, the semiconductor package 500 is a package on package (POP) semiconductor package. In an embodiment of the present invention, the package-on-package semiconductor package 500 includes at least two vertically stacked wafer-level semiconductor packages. The above-mentioned package-on-package semiconductor package 500 includes a system-on-chip (SOC) package and a memory package (memory package) stacked on the SOC package, wherein the SOC package is, for example, a logic package (logic package), and the memory package is, for example, Packaged for dynamic random access memory (DRAM). Because the design rules for memory packages are usually larger than those for SOC packages, the memory package can have enough space for the memory and decoupling capacitors to be affixed thereto to enhance power delivery to the DRAM components of the memory package. Network (power delivery network, PDN), or even strengthen the power delivery network of the central processing unit (central processing unit, CPU) and graphics processing unit (graphic processing unit, GPU) packaged in SOC. Also, each semiconductor package of the above-mentioned semiconductor package 500 may be a flip chip package, and the above-mentioned flip chip package uses a conductive structure such as copper pillar bumps to connect the semiconductor element to the base. .

Referring to FIG. 1 , a semiconductor package 500 includes a base 200 , a first semiconductor package 206 fixed on the base 200 , and a second semiconductor package 232 stacked and fixed on the first semiconductor package 206 . In an embodiment of the present invention, the above-mentioned base 200 is, for example, a printed circuit board (print circuit board, PCB), which may be formed of polypropylene (PP). It should be understood that the above-mentioned base 200 may be a single layer structure or a multilayer structure. A plurality of wires (not shown) and pads (not shown) are disposed on the device attach surface 202 of the base 200 . In an embodiment of the present invention, the wires may include signal trace segments or ground wire segments, and the signal trace segments or ground wire segments may be used for input/output (I/O) connections of the first semiconductor package 206 . Moreover, the pads are disposed on the component attaching surface 202 of the base 200 and connected to different ends of the plurality of wires. The pads are used for mounting the first semiconductor package 206 thereon.

As shown in FIG. 1 , the first semiconductor package 206 is fixed on the component attaching surface 202 of the base 200 through a bonding process. In this embodiment, the above-mentioned first semiconductor package 206 is a system-on-chip (SOC) package, such as a logic package. The first semiconductor package 206 includes a first body 208 having a first component attaching surface 210 and a first bump attaching surface 212 opposite to the first component attaching surface 210 . The above-mentioned first substrate 208 may include a circuit 216 , a metal pad 218 and a metal pad 220 . The metal pad 218 is disposed on the top of the circuit 216 close to the first component attaching surface 210 , and the metal pad 220 is disposed on the bottom of the circuit 216 close to the first bump attaching surface 212 . The circuit 216 of the first semiconductor package 206 is interconnected to the circuit of the base 200 through a plurality of first conductive structures 214 , and the first conductive structures 214 are disposed on the first bump attaching surface 212 of the first substrate 208 . Moreover, the first conductive structure 214 contacts the base 200 . In an embodiment of the present invention, the above-mentioned first conductive structure 214 may include a conductive bump structure such as a copper bump structure or a solder bump structure, a conductive pillar structure, a wire structure, or a conductive paste structure. The logic element 222 is fixed on the first element attaching surface 210 of the first substrate 208 through a conductive structure 228 using flip-chip technology. In an embodiment of the present invention, the logic element 222 may include a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory controller (DRAM controller), or any combination thereof. In the present embodiment, the logic element 222 includes a central processing unit (CPU) and/or a graphics processing unit (GPU) 224 and a dynamic random access memory controller (DRAM controller) 226 integrated with the CPU and/or GPU 224 . In an embodiment of the present invention, the conductive structure 228 may include a conductive bump structure such as a copper bump structure or a solder bump structure, a conductive pillar structure, a wire structure, or a conductive paste structure. In an embodiment of the present invention, an underfill material or an underfill 230 may be introduced into the gap between the logic element 222 and the first substrate 208 . In an embodiment of the present invention, the underfill material or the underfill 230 may include capillary underfill (CUF), molded underfill (MUF), nonconductive insulation (nonconductive paste, NCP) , nonconductive insulating film (nonconductive film, NCF), or any combination of the above.

Please refer to Figure 1 again. The second semiconductor package 232 can be stacked on the first component attaching surface 210 of the first semiconductor package 206 through a bonding process. In this embodiment, the above-mentioned second semiconductor package 232 may be a memory package, such as a dynamic random access memory (DRAM) package. The second semiconductor package 232 includes a second substrate 234 having a second component attaching surface 236 and a second bump attaching surface 238 opposite to the second component attaching surface 236 . Similar to the first substrate 208 described above, the second substrate 234 may include a circuit 250 , a metal pad 248 and a metal pad 252 . The metal pad 248 is disposed on the top of the circuit 250 close to the second component attaching surface 236 , and the metal pad 252 is disposed on the bottom of the circuit 250 close to the second bump attaching surface 238 . The circuit 250 of the second semiconductor package 232 is interconnected to the circuit 216 of the first semiconductor package 206 through a plurality of second conductive structures 240, and the second conductive structures 240 are disposed on the second bump attachment of the second substrate 234. On face 238. Moreover, the second conductive structure 240 contacts the first component attaching surface 210 of the first substrate 208 of the first semiconductor package 206 . In an embodiment of the present invention, the second conductive structure 240 may include a conductive bump structure such as a copper bump structure or a solder bump structure, a conductive pillar structure, a wire structure, or a conductive paste structure. In an embodiment of the present invention, the second semiconductor package 232 may include at least one dynamic random access memory (DRAM) element, which is fixedly connected to the second element attaching surface 236 of the second substrate 234 . As shown in FIG. 1 , in this embodiment, there are three DRAM components, such as a DRAM component 242 , a DRAM component 244 and a DRAM component 246 , fixed on the second component attachment surface 236 of the second substrate 234 . Moreover, the DRAM element 242 is fixed to the second element attaching surface 236 of the second substrate 234 through the conductive glue 243 . The DRAM element 244 is stacked on the DRAM element 242 through the conductive glue 245 , and the DRAM element 246 is stacked on the DRAM element 244 through the conductive glue 247 . The DRAM element 242 , the DRAM element 244 and the DRAM element 246 may be coupled to the second substrate 234 through bonding wires, such as bonding wires 268 , 270 and 272 . However, the number of the above-mentioned stacked DRAM devices is only an example, and is not intended to limit the present invention. In other embodiments of the present invention, the DRAM element 242 , the DRAM element 244 and the DRAM element 246 shown in FIG. 1 may be configured side by side. Therefore, the DRAM element 242 , the DRAM element 244 and the DRAM element 246 can be fixed to the second element attaching surface 236 of the second substrate 234 through conductive glue.

It should be noted that the above-mentioned second semiconductor package 232, such as the memory package 232, is only used to package at least one memory element. Therefore, the above-mentioned design rules of the second semiconductor package 232 (eg, pad minimum pitch, pad size, critical dimension of the circuit, etc.) are usually larger than those of the system-on-a-chip (SOC). Design rules for the first semiconductor package 206 of the SOC) package. The second substrate 234 of the second semiconductor package 232 may have enough space for an additional decoupling capacitor to be fixed on the second substrate 234 of the second semiconductor package 232 . Moreover, the second base 234 of the second semiconductor package 232 may include dummy pads and dummy circuits disposed at corners of the second base 234 . The aforementioned dummy pads and dummy circuits are used to release the pressure on the second substrate 234 and prevent the aforementioned semiconductor package from being damaged when it is dropped. Therefore, the dummy pad and the dummy circuit can be fixedly connected to the additional decoupling capacitor, and the additional decoupling capacitor can be electrically coupled to the first semiconductor package 206 through the dummy pad and the dummy circuit. As shown in FIG. 1 , in this embodiment, the second semiconductor package 232 further includes at least one decoupling capacitor fixedly connected to the second component attaching surface 236 of the second substrate 234 . In this embodiment, the decoupling capacitor 254 and the decoupling capacitor 260 are fixedly connected to the second component attachment surface 236 of the second substrate 234 . Moreover, the DRAM element 242 , the DRAM element 244 , the DRAM element 246 , the decoupling capacitor 254 and the decoupling capacitor 260 are discrete devices. In other words, decoupling capacitor 254 and decoupling capacitor 260 are separated from DRAM element 242 , DRAM element 244 , and DRAM element 246 . As shown in FIG. 1 and FIG. 2, because the above-mentioned decoupling capacitor can be designed and fixed on the above-mentioned second semiconductor package 232, and the above-mentioned second semiconductor package 232 is, for example, a DRAM package and its design rule is greater than that of the above-mentioned first semiconductor package, such as a logic package. Design rules for the semiconductor package 206 . Therefore, the above-mentioned first semiconductor package 206 and the above-mentioned second semiconductor package 232 can maintain the original package size without providing additional area for the decoupling capacitor. As shown in FIG. 1 and FIG. 2, in an embodiment of the present invention, in a top view, for example, the boundary 280 of the first substrate 208 of the first semiconductor package 206 of the logic package (below the second semiconductor package 232) can be compared with A border 282 of the second substrate 234 of the second semiconductor package 232 completely overlaps. In other words, in a top view, the boundary 282 of the second substrate 234 of the second semiconductor package 232, such as a DRAM package, can be aligned with the first semiconductor package 206 of the logic package (below the second semiconductor package 232), such as a logic package. A border 280 of the base 208 .

As shown in FIG. 1 , in one embodiment of the present invention, the second semiconductor package 232 further includes a molding material 266 covering the second component attaching surface 236 of the second substrate 234 and including the DRAM component 242 , DRAM element 244 , DRAM element 246 , bonding wire 268 , bonding wire 270 , bonding wire 272 , decoupling capacitor 254 and decoupling capacitor 260 .

Please refer to Figure 1 again. At least one external power supply is disposed on the component attaching surface 202 of the base 200 . In this embodiment, there are two external power sources (eg, external power source 204 , external power source 205 ) disposed on the component attaching surface 202 of the above-mentioned base 200 . In an embodiment of the present invention, both the external power source 204 and the external power source 205 are separated from the first semiconductor package 206 and the second semiconductor package 232 . In this embodiment, the above-mentioned external power supply 204 and the external power supply 205 are used for the above-mentioned CPU and/or GPU 224 and dynamic random access memory (DRAM) controller 226 of the above-mentioned first semiconductor package 206, and the above-mentioned second semiconductor package 232 The DRAM element 242, DRAM element 244, and DRAM element 246 provide power.

In an embodiment of the present invention, the decoupling capacitor 254 and the decoupling capacitor 260 may be coupled to the CPU and/or GPU 224 and/or the dynamic random access memory (DRAM) controller 226 to provide compensation current and/or Compensation current and/or voltage. Also, the decoupling capacitor 254 and the decoupling capacitor 260 can mitigate simultaneous switching output (SSO) noise from a power supply that provides current and/or voltage to the semiconductor package 500 . Therefore, the decoupling capacitor 254 and the decoupling capacitor 260 are used to strengthen the power delivery network (powerdelivery network, PDN) of the DRAM element of the memory package (the above-mentioned second semiconductor package 232), or even strengthen the SOC package (the above-mentioned first semiconductor package 232). The power supply network of the central processing unit (central processing unit, CPU) and the graphics processing unit (graphic processing unit, GPU) of the package 206 . As shown in FIG. 1 , in an embodiment of the present invention, the decoupling capacitor 260 is designed to be coupled to the CPU and/or GPU 224 of the logic element 222 and the external power supply 204 . In this embodiment, the decoupling capacitor 260 provides compensation current and/or compensation voltage to the CPU and/or GPU 224 of the logic element 222 of the first semiconductor package 206 through the current path 262 (marked as a dotted line). In other embodiments of the present invention, the decoupling capacitor 254 is designed to be coupled to the DRAM element 242, the DRAM element 244, the DRAM element 246, the DRAM controller 226 integrated with the logic element 222, and the external power supply 205 . The decoupling capacitor 254 provides compensation current and/or compensation voltage to the DRAM element 242 , DRAM element 244 , and DRAM element 246 of the second semiconductor package 232 through a current path 264 (marked as a dotted line). Moreover, the DRAM element 242 , the DRAM element 244 , the DRAM element 246 , the decoupling capacitor 254 , and the decoupling capacitor 260 are respectively coupled to the first bump attachment surface 238 through different conductive structures 252 . Semiconductor package 206 .

An embodiment of the present invention provides a semiconductor package, such as a package-on-package (POP) semiconductor package. The aforementioned semiconductor package includes a memory package such as a dynamic random access memory (DRAM) package, stacked on a system-on-chip (SOC) package such as a logic package. Because the above-mentioned design rules of the memory package (such as pad minimum pitch, pad size, critical dimension of the circuit, etc.) are usually larger than, for example, the above-mentioned system-on-chip (SOC) Package design rules, so the above-mentioned semiconductor package is designed to include an additional decoupling capacitor fixedly connected to the above-mentioned memory package. Moreover, the above-mentioned additional decoupling capacitors can be fixedly connected to the dummy pads and dummy circuits of the above-mentioned memory package, and the above-mentioned dummy pads and dummy circuits are used to release the pressure on the base of the above-mentioned memory package, and can prevent the above-mentioned semiconductor package from Damage caused by a fall. In one embodiment of the present invention, the above-mentioned decoupling capacitor fixed to the above-mentioned memory package is designed to be coupled to the above-mentioned external power supply 204 of the above-mentioned logic element in the above-mentioned system on a chip (SOC) package, so as to provide compensation current and/or for the above-mentioned logic element or compensation voltage. Moreover, the decoupling capacitor may be designed to be coupled to the DRAM element of the memory package, the DRAM controller, and the external power supply, so as to provide compensation current and/or compensation voltage to the DRAM element. Therefore, the above-mentioned system-on-chip (SOC) package and the above-mentioned memory package can maintain the original package size without providing additional area for decoupling capacitors.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (28)

1. a kind of semiconductor packages, it is characterised in that including：First semiconductor packages and the second semiconductor packages, described first Semiconductor packages includes：

First substrate, attaches face with the first element and attaches face relative to the first projection that first element attaches face；With And

Second semiconductor packages, first element for being bonded to first semiconductor packages attaches face, wherein described Second semiconductor packages includes：

Second substrate, attaches face with the second element and attaches face relative to the second projection that second element attaches face；

Dynamic random access memory, is fixed on the second element attaching face；

Decoupling capacitance, the illusory weld pad being fixed on the second element attaching face of second substrate and dummy circuit On, and it is coupled to first semiconductor packages；And

Multiple conductive structures, are arranged on the second projection attaching face, and are connected to the described of first semiconductor packages First element of first substrate attaches face.

2. semiconductor packages as claimed in claim 1, it is characterised in that in a top view, the border of first substrate with The border of second substrate is completely overlapped.

3. semiconductor packages as claimed in claim 1, it is characterised in that first semiconductor packages also includes logic basis Part, first element for being fixed in first substrate attaches face.

4. semiconductor packages as claimed in claim 3, it is characterised in that also include：

Pedestal, wherein first semiconductor packages and second semiconductor packages pass through first semiconductor packages One conductive structure is fixed on the pedestal；And

External power source, is arranged on the pedestal, and is separated with first semiconductor packages and second semiconductor packages.

5. semiconductor packages as claimed in claim 4, it is characterised in that the decoupling capacitance is coupled to the logic element Both with the external power source.

6. semiconductor packages as claimed in claim 4, it is characterised in that the decoupling capacitance is coupled to the dynamic random Access memory component, the dynamic RAM Controller and the external power source integrated with the logic element.

7. semiconductor packages as claimed in claim 1, it is characterised in that the dynamic random access memory and described Decoupling capacitance is spaced apart.

8. semiconductor packages as claimed in claim 1, it is characterised in that the dynamic random access memory and described Decoupling capacitance attached respectively by being arranged on second projection face different the multiple conductive structures be coupled to it is described First semiconductor packages.

9. semiconductor packages as claimed in claim 1, it is characterised in that second semiconductor packages also includes extra dynamic Random access memory, is stacked vertically on the dynamic random access memory, and is electrically connected to described Two substrates.

10. a kind of semiconductor packages, it is characterised in that including：

Pedestal；

Dynamic random access memory is encapsulated, and is bonded to the pedestal；And

External power source, is arranged on the pedestal, and is separated with dynamic random access memory encapsulation；

Wherein described dynamic random access memory encapsulation includes：

Substrate；

Dynamic random access memory, it is affixed on the substrate；And

On decoupling capacitance, affixed illusory weld pad and dummy circuit on the substrate, and it is coupled to the semiconductor packages On logical wrapper, and separated with the dynamic random access memory.

11. semiconductor packages as claimed in claim 10, it is characterised in that

The logical wrapper, between dynamic random access memory encapsulation and the pedestal, wherein the logic is sealed Dress includes：

First substrate, attaches face with the first element and attaches face relative to the first projection that first element attaches face；

Logic element, first element for being fixed in first substrate attaches face；And

Multiple first conductive structures, are arranged on the first projection attaching face, and contact the pedestal.

12. semiconductor packages as claimed in claim 11, it is characterised in that the dynamic random access memory encapsulation passes through The second projection for being arranged at the substrate of the dynamic random access memory encapsulation attaches multiple second conductive structures in face It is bonded to first element and attaches face, and contact first element and attaches face.

13. semiconductor packages as claimed in claim 12, it is characterised in that the institute of the dynamic random access memory encapsulation Stating substrate, there is the second element for attaching face relative to second projection to attach face, and wherein described dynamic random access memory Device element is fixed on the second element attaching face.

14. semiconductor packages as claimed in claim 12, it is characterised in that the dynamic random access memory and institute State the different the multiple second conductive structures couplings that decoupling capacitance attaches face by being arranged on second projection respectively To the logical wrapper.

15. semiconductor packages as claimed in claim 11, it is characterised in that in a top view, the dynamic randon access is deposited The border and the border of first substrate of the logical wrapper of the substrate of reservoir encapsulation are completely overlapped.

16. semiconductor packages as claimed in claim 11, it is characterised in that the decoupling capacitance is coupled to the logic basis Both part and the external power source.

17. semiconductor packages as claimed in claim 11, it is characterised in that the decoupling capacitance be coupled to the dynamic with Machine access memory component, the dynamic RAM Controller and the external power source integrated with the logic element.

18. semiconductor packages as claimed in claim 10, it is characterised in that the dynamic random access memory encapsulation is also wrapped Extra dynamic random access memory is included, is stacked vertically on the dynamic random access memory, and is electrically connected It is connected to the substrate of the dynamic random access memory encapsulation.

19. a kind of semiconductor packages, it is characterised in that including：

Pedestal；

System single chip is encapsulated, and is bonded to the pedestal；

Memory package, is bonded to the system single chip encapsulation, and wherein memory package includes decoupling capacitance, the decoupling Close electric capacity to be fixed in illusory weld pad and the dummy circuit in the memory package, and be coupled to the system single chip envelope Dress；And

External power source, is arranged on the pedestal, and is separated with system single chip encapsulation.

20. semiconductor packages as claimed in claim 19, it is characterised in that the system single chip encapsulation includes：

First substrate, attaches face with the first element and attaches face relative to the first projection that first element attaches face；

Logic element, is fixed in first element and attaches face；And

Multiple first conductive structures, are arranged on the first projection attaching face, and contact the pedestal.

21. semiconductor packages as claimed in claim 20, it is characterised in that the memory package is deposited for dynamic randon access Reservoir is encapsulated.

22. semiconductor packages as claimed in claim 21, it is characterised in that the dynamic random access memory wrapper Include：

Second substrate, attaches face with the second element and attaches face relative to the second projection that second element attaches face；

Dynamic random access memory and the decoupling capacitance, are fixed on the second element attaching face；And

Multiple second conductive structures, are arranged on second projection and attach face, are connected to the described of the system single chip encapsulation First element of first substrate attaches face.

23. semiconductor packages as claimed in claim 22, it is characterised in that the dynamic random access memory and institute State element of the decoupling capacitance for separation.

24. semiconductor packages as claimed in claim 22, it is characterised in that in a top view, the dynamic randon access is deposited The border for first substrate that the border of second substrate of reservoir encapsulation is encapsulated with the system single chip is completely overlapped.

25. semiconductor packages as claimed in claim 22, it is characterised in that the decoupling capacitance be coupled to the dynamic with Machine access memory component, the dynamic RAM Controller and the external power source integrated with the logic element.

26. semiconductor packages as claimed in claim 22, it is characterised in that the dynamic random access memory and institute State the different the multiple second conductive structures couplings that decoupling capacitance attaches face by being arranged on second projection respectively To system single chip encapsulation.

27. semiconductor packages as claimed in claim 22, it is characterised in that the dynamic random access memory encapsulation is also wrapped Extra dynamic random access memory is included, is stacked vertically on the dynamic random access memory, and is electrically connected It is connected to second substrate.

28. semiconductor packages as claimed in claim 20, it is characterised in that the decoupling capacitance is coupled to the logic basis Both part and the external power source.