CN104037322B - Resistive memory and its storage unit - Google Patents

Abstract

The invention discloses a resistive memory and a memory cell thereof, wherein the resistive memory cell comprises a substrate, a first doped region, a second doped region and a grid electrode. The first doped region and the second doped region are also disposed in the substrate, and the gate is disposed on the substrate and covers a portion of the first doped region and a portion of the second doped region, wherein the gate is a floating gate. In addition, the first doped region and the second doped region respectively receive a first reference voltage and a second reference voltage, and the overlapping regions of the first doped region and the gate electrode and the overlapping regions of the second doped region and the gate electrode respectively provide a first impedance value and a second impedance value which are different according to the voltage difference of the first reference voltage and the second reference voltage.

Description

Resistive memory and its storage unit

technical field

The present invention relates to a resistive memory cell, and in particular to a resistive memory cell with a back-to-back structure.

Background technique

Based on the various advantages of the resistive memory structure, it has become a current trend to apply the resistive memory structure to the non-volatile memory. In the prior art, the resistive memory structure includes a transition metal oxide layer (transition metal oxide) formed of, for example, nickel oxide (NiO), titanium dioxide (TiO ₂ ), copper oxide (CuO) or hafnium oxide (HfO). oxide layer). This transition metal oxide is sandwiched between two metal layers to form a so-called Metal-Insulator-Metal (MIM) structure. Although the so-called MIM structure can be completed by a post-metallization process, but for the resistive memory as an embedded memory, this post-metallization process requires redundant photomasks and process steps. Completed, causing great trouble in production.

In addition, since the resistive memory provides a certain resistance value, when the resistance value provided by the resistive memory is low, a certain degree of leakage phenomenon will occur. In addition to wasting power, this leakage phenomenon will also have a certain interference effect on the system to which the resistive memory belongs, reducing the performance of the system.

Contents of the invention

The invention provides a resistive memory and a resistive memory unit, which can effectively reduce the leakage current that may be generated on the memory unit.

The resistive memory unit of the present invention includes a substrate, a first doped region, a second doped region and a gate. The first doped region and the second doped region are also disposed in the substrate, and the gate is disposed on the substrate and covers part of the first doped region and part of the second doped region, wherein the gate is a floating gate . In addition, the first doped region and the second doped region receive the first reference voltage and the second reference voltage respectively, and the overlapping regions of the first doped region and the second doped region and the gate are respectively based on the first reference voltage and the second reference voltage. The voltage difference of the second reference voltage provides different first and second impedance values respectively.

The present invention also provides a resistive memory, which includes a plurality of resistive memory cells, a plurality of bit lines and word lines. The resistive memory cells are arranged in an array to form a plurality of memory rows and a plurality of memory columns, the bit lines are respectively coupled to the resistive memory cells of the memory rows, and the word lines are respectively coupled to the resistive memory cells of the memory columns. Each resistive memory unit includes a substrate, a first doped region, a second doped region and a gate. The first doped region and the second doped region are also disposed in the substrate, and the gate is disposed on the substrate and covers part of the first doped region and part of the second doped region, wherein the gate is a floating gate . In addition, the first doped region and the second doped region receive the first reference voltage and the second reference voltage respectively, and the overlapping regions of the first doped region and the second doped region and the gate are respectively based on the first reference voltage and the second reference voltage. The voltage difference of the second reference voltage provides different first and second impedance values respectively.

Based on the above, the present invention provides a transistor structure with a floating gate to form a resistive memory cell, effectively providing a storage space for one bit through a single transistor. Moreover, under the condition that the first impedance and the second impedance respectively provided by the overlapping regions of the first doped region and the second doped region and the gate are complementary, there must be a high voltage in the channel of the single resistive memory cell. The impedance path, in other words, the leakage current generated in the channel of the resistive memory unit can be effectively reduced, saving unnecessary power consumption.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a resistive memory cell according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an operation mode of a resistive memory cell according to an embodiment of the present invention.

FIG. 3A is a graph showing the relationship between voltage and impedance of the first doped region according to an embodiment of the present invention.

FIG. 3B is a graph showing the relationship between voltage and impedance of the second doped region according to an embodiment of the present invention.

FIG. 3C is a graph showing the relationship between voltage and impedance of the resistive memory cell 100 according to the embodiment of the present invention.

FIG. 4 is a schematic diagram of a resistive memory according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100, 411 ~ 4MN: resistive memory unit

110: base

121: the first doped region

122: second doped region

130: grid

d1, d2: part of the area

VREF1, V1, V2: first reference voltage

VREF2: Second reference voltage

GND: ground voltage

310, 320, 330, 340, 351, 352, 360: line segment

VRESET: reset voltage value

VSET: set voltage value

VTH1～VTH4: critical voltage

400: resistive memory

BL1～BLN: Bit line

WL1～WLM: word line

detailed description

Please refer to FIG. 1 , which is a schematic diagram of a resistive memory cell 100 according to an embodiment of the present invention. The resistive memory cell 100 includes a substrate 110 , a first doped region 121 , a second doped region 122 and a gate 130 . The first doped region 121 and the second doped region 122 are disposed in the substrate 110 , and the first doped region 121 and the second doped region 122 are not in contact. In addition, the gate 130 is disposed on the substrate 110 and covers a part of the region d1 of the first doped region 121 and a part of the region d2 of the second doped region 122 . In this embodiment, the first doped region 121 and the second doped region 122 receive the first reference voltage VREF1 and the second reference voltage VREF2 respectively. It should be noted that the gate 130 is a floating gate, that is to say, the gate 130 exhibits a state of high impedance.

In addition, the voltage values of the first reference voltage VREF1 and the second reference voltage VREF2 are different, wherein the resistive memory cell 100 passes through the regions where the gate 130 partially overlaps with the first doped region 121 and the second doped region 122 respectively. to provide the first impedance value and the second impedance value respectively. The first impedance value and the second impedance value are determined according to the voltage difference between the first reference voltage VREF1 and the second reference voltage VREF2 .

The resistive memory cell 100 of this embodiment is a bipolar structure. In simple terms, the first impedance value and the second impedance value respectively provided by the first doped region 121 and the second doped region 122 can be Complementary. That is to say, when the first impedance value provided by the overlapping region of the first doped region 121 and the gate 130 is a relatively high high resistance value, the overlapping region of the second doped region 122 and the gate 130 provides The second impedance value may be a relatively low low impedance value. In contrast, when the first impedance value provided by the overlapping region of the first doped region 121 and the gate 130 is relatively low, the first impedance value provided by the overlapping region of the second doped region 122 and the gate 130 The second impedance value may be a relatively high high impedance value.

In other words, at least one of the overlapping regions of the first doped region 121 and the second doped region 122 and the gate 130 in the resistive memory cell 100 will provide a relatively high high resistance value. That is to say, the unnecessary leakage phenomenon caused by the low impedance value of the channel of the resistive memory unit 100 can be effectively reduced.

Incidentally, when the first doped region 121 is a source, the second doped region 122 can be a drain, and on the contrary, when the first doped region 121 is a drain, the second doped region 122 can be can be the source.

In addition, the region between the gate 130 shown in FIG. 1 and the first doped region 121 of the substrate 110 and the second doped region 122 is a dielectric layer material, such as silicon dioxide (SiO ₂ ), hafnium oxide (HfOx), oxide Zirconium (ZrOx), titanium oxide (TiOx), tantalum oxide (TaOx), (nickel oxide (NiOx), copper oxide (CuOx) or aluminum oxide (AlOx), etc., and some regions d1 and d2 have the above dielectric A local area of the layer material.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram illustrating an operation mode of the resistive memory cell 100 according to an embodiment of the present invention. In FIG. 2 , the first reference voltage V1 received by the first doped region 121 may be a positive voltage greater than 0 volts, or a negative voltage less than 0 volts. In contrast, the second reference voltage V2 received by the second doped region 122 may be the ground voltage GND equal to 0 volts. Of course, the second reference voltage does not have to be the ground voltage GND equal to 0 volts.

Please refer to FIG. 2 and FIG. 3A synchronously below. FIG. 3A is a graph showing the relationship between the voltage and impedance of the first doped region 121 according to the embodiment of the present invention. In the graph shown in FIG. 3A , the horizontal axis represents the voltage value of the first reference voltage V1, the gate 130 is equal to the ground voltage GND of 0 volts, and the bias state of the second doped region 122 can be ignored ( For example, it can be set to floating state). The vertical axis represents the current value generated in the first doped region 121 . In other words, the reciprocals of the slopes of the line segments 310 and 320 can represent different impedance values provided by the overlapping regions of the first doped region 121 and the gate 130 under different conditions.

It can be seen from the line segment 310 located in the first quadrant that when the first reference voltage V1 is less than the reset voltage value VRESET, the first impedance value provided by the overlapping region of the first doped region 121 and the gate 130 is equal to a relatively low low impedance value. It can be seen from the line segment 320 located in the first quadrant that as the first reference voltage V1 increases and when the first reference voltage V1 is greater than or equal to the reset voltage value VRESET, the overlapping of the first doped region 121 and the gate 130 The first impedance value provided by the area is changed from a relatively low low impedance value to a relatively high high impedance value (the slope of the line segment 310 is greater than the slope of the line segment 320 ).

In addition, as can be seen from the line segment 320 located in the third quadrant, when the first reference voltage V1 is greater than the set voltage value -VSET, the first impedance value provided by the overlapping region of the first doped region 121 and the gate 130 is equal to the relative High high impedance value. From the line segment 320 located in the third quadrant, it can be seen that as the first reference voltage V1 decreases, and when the voltage value of the first reference voltage V1 is less than or equal to the negative set voltage value -VSET, the first doped region 121 The first impedance value provided by the overlapping area with the gate 130 is changed from a relatively high high impedance value to a relatively low low impedance value.

For the part about the second doped region 122 , please refer to FIG. 2 and FIG. 3B at the same time. FIG. 3B shows the relationship between the voltage and the impedance of the second doped region 122 according to the embodiment of the present invention. In the coordinate diagram shown in FIG. 3B, the horizontal axis represents the voltage value of the gate 130, the second reference voltage V2 is equal to the ground voltage of 0 volts, and the vertical axis represents the current value generated on the second doped region 122. , at this time the bias state of the first doped region 121 can be ignored (for example, it can be set to a floating state). In other words, the slopes of the line segments 330 and 340 can represent different impedance values provided by the overlapping regions of the second doped region 122 and the gate 130 under different conditions.

From the line segment 340 located in the first quadrant, it can be seen that when the voltage of the second reference voltage V2 is lower than the set voltage value VSET, the second impedance value provided by the overlapping region of the second doped region 122 and the gate 130 is equal to a relatively high High impedance value. From the line segment 330 located in the third quadrant, it can be seen that with the increase of the second reference voltage V2, and when the second reference voltage V2 is greater than or equal to the set voltage value VSET, the overlapping of the second doped region 122 and the gate 130 The second impedance value provided by the area is changed from a relatively high high impedance value to a relatively low low impedance value (the slope of the line segment 330 is greater than the slope of the line segment 340 ).

Please also refer to FIG. 2 and FIG. 3B at the same time. From the line segment 330 located in the third quadrant, it can be seen that when the second reference voltage V2 is greater than the negative reset voltage value -VRESET, the overlapping area between the second doped region 122 and the gate 130 The provided second impedance value is equal to the relatively low low impedance value. From the line segment 340 located in the third quadrant, it can be seen that with the decrease of the second reference voltage V2, when the second reference voltage V2 is less than or equal to the negative set voltage value -VRESET, the second doped region 122 and the gate 130 The second impedance value provided by the overlapping region is changed from a relatively low low impedance value to a relatively high high impedance value.

Please refer to FIG. 2 and FIG. 3C at the same time. In the coordinate diagram shown in FIG. 3C , FIG. 3C shows the relationship between the voltage and impedance of the resistive memory cell 100 according to the embodiment of the present invention. The horizontal axis represents the voltage difference applied between the first doped region 121 and the second doped region 122 , and the vertical axis represents the current generated between the first and second doped regions 121 and 122 . When the voltage difference is lower than the threshold voltage VTH1 and greater than zero, the equivalent impedance provided by the resistive memory cell 100 is equal to the reciprocal of the slope of the line segment 360 . At this time, the overlapping regions of the first doped region 121 and the second doped region 122 of the resistive memory cell 100 and the gate 130 respectively provide a first resistance value equal to a low resistance value and a second resistance value equal to a high resistance value , the equivalent impedance provided by the resistive memory unit 100 is equal to the sum of the low impedance value and the high impedance value and approximately equal to the relatively high high impedance value. When the voltage difference increases to be between the critical voltages VTH1 and VTH2, the equivalent impedance provided by the resistive memory unit 100 is equal to the reciprocal of the slope of the line segment 352, which is equal to a relatively low low impedance value. At this time, the resistive memory cell The overlapping regions of the first doped region 121 and the second doped region 122 of the cell 100 and the gate 130 both provide relatively low low resistance values. When the voltage difference is increased to be greater than the threshold voltage VTH2, the overlapping regions of the first doped region 121 and the second doped region 122 of the resistive memory cell 100 and the gate 130 respectively provide the first impedance value equal to the high impedance value and the first impedance value equal to the high impedance value. The second impedance value equal to the low impedance value, the equivalent impedance provided by the resistive memory unit 100 is equal to the sum of the low impedance value and the high impedance value and approximately equal to the relatively high high impedance value.

When the voltage difference is higher than the threshold voltage VTH3 and smaller than zero, the equivalent impedance provided by the resistive memory cell 100 is equal to the reciprocal of the slope of the line segment 360 . At this time, the overlapping regions of the first doped region 121 and the second doped region 122 of the resistive memory cell 100 and the gate 130 respectively provide a first impedance equal to a low impedance value and a second impedance equal to a high impedance value value, the equivalent impedance provided by the resistive memory cell 100 is equal to the sum of the low impedance value and the high impedance value and approximately equal to the relatively high high impedance value. When the voltage difference decreases to be between the critical voltages VTH3 and VTH4, the equivalent impedance provided by the resistive memory unit 100 is equal to the reciprocal of the slope of the line segment 351, which is equal to a relatively low low impedance value. At this time, the resistive memory cell The overlapping regions of the first doped region 121 and the second doped region 122 of the cell 100 and the gate 130 both provide relatively low low resistance values. When the voltage difference is gradually reduced to less than the critical voltage VTH4, the overlapping regions of the first doped region 121 and the second doped region 122 of the resistive memory cell 100 and the gate 130 respectively provide a first resistance value equal to a high resistance value and a high resistance value. The second impedance value equal to the low impedance value, the equivalent impedance provided by the resistive memory unit 100 is equal to the sum of the low impedance value and the high impedance value and approximately equal to the relatively high high impedance value.

It is not difficult to know from the above description that when the resistive memory cell 100 is storing data, the overlapping regions of the first doped region 121 and the second doped region 122 and the gate 130 can respectively provide a second resistance equal to a low resistance value. An impedance value and a second impedance value equal to the high impedance value are used to represent logic level 0, and the overlapping regions of the first doped region 121 and the second doped region 122 and the gate 130 can respectively provide an impedance equal to the high impedance value. The first impedance value and the second impedance value equal to the low impedance value represent logic level 1. Moreover, the above logic state can be read by making the voltage difference between the threshold voltages VTH1 and VTH2, or making the voltage difference between VTH3 and VTH4. Certainly, the definition of the logic level and the impedance states respectively provided by the first doped region 121 and the second doped region 122 is just an example, and the designer can set it according to his needs. To limit the present invention.

In this embodiment, the slopes of the line segments 351 and 352 may be equal.

Please refer to FIG. 4 , which is a schematic diagram of a resistive memory 400 according to an embodiment of the present invention. The resistive memory 400 includes a plurality of resistive memory cells 411-4MN, a plurality of bit lines BL1-BLN and word lines WL1-WLM. The resistive memory cells 411˜4MN are arranged in an array to form a plurality of storage rows and a plurality of storage columns. The resistive memory cells 411˜4MN may be the resistive memory cells 100 as shown in the embodiment of FIG. 1 . Wherein, the bit lines BL1-BLN are respectively coupled to the resistive memory cells 411-4MN of each memory row, and the word lines WL1-WLM are respectively coupled to the resistive memory cells 411-4MN of each memory column. For example, the bit line BL1 is coupled to the resistive memory cells 411, 421, . 41N.

To sum up, the present invention proposes to use the floating gate to construct the resistive memory cell. Under the back-to-back structure formed by the floating gate, the first and second doped regions of the resistive memory cell and the gate The first and second impedances respectively provided by the overlapping regions of the can exhibit complementary states. In this way, one of the first and second impedances will be in a state of high impedance, effectively reducing the leakage current that may be generated in the resistive memory unit. Therefore, the performance of the resistive memory cell can be effectively improved.

Claims (10)

1. a kind of resistive memory cell, including：

One substrate；

One first doped region, configuration is in this substrate；

One second doped region, configuration is in this substrate；

One grid, configuration is in substrate, and covers this first doped region of part and this second doped region of part, and this grid floats for one Moving grid pole,

Wherein, this first doped region and this second doped region receive one first reference voltage and one second reference voltage respectively, and The overlapping region of this first doped region and this second doped region and this grid is respectively according to this first reference voltage and this second ginseng The voltage difference examining voltage provides one first resistance value differing and one second resistance value.

2. resistive memory cell as claimed in claim 1, wherein when the absolute value of this voltage difference is less than a reset voltage value, This first resistance value that the overlapping region of this first doped region and this grid provides is equal to a high impedance value, exhausted when this voltage difference When value being incremented by not less than this reset voltage value, this first impedance of the overlapping region offer of this first doped region and this grid Value is changed to a low impedance value,

Wherein, this high impedance value is more than this low impedance value.

3. resistive memory cell as claimed in claim 2, wherein when the absolute value of this voltage difference is less than a setting voltage value, This second resistance value that the overlapping region of this second doped region and this grid provides is equal to this low impedance value, exhausted when this voltage difference When value being incremented by not less than this setting voltage value, this second impedance of the overlapping region offer of this second doped region and this grid Value is changed to this high impedance value.

4. resistive memory cell as claimed in claim 3, wherein this reset voltage value are equal to this setting voltage value.

5. resistive memory cell as claimed in claim 1, wherein this first doped region are one of them of drain electrode and source electrode, should Second doped region be drain electrode and source electrode another.

6. a kind of resistance-type memory, including：

How several how several resistive memory cell, arranged according to an array mode to form how several storage line and deposit Chu Lie, wherein respectively this resistive memory cell includes：

One substrate；

One first doped region, configuration is in this substrate；

One second doped region, configuration is in this substrate；

One grid, configuration is in substrate, and covers this first doped region of part and this second doped region of part, and this grid floats for one Moving grid pole,

Wherein, this first doped region and this second doped region receive one first reference voltage and one second reference voltage respectively, and The overlapping region of this first doped region and this second doped region and grid is respectively according to this first reference voltage and this second reference One voltage differential of voltage you can well imagine one first resistance value and one second resistance value for differing；And

Several bit lines many and wordline, the plurality of bit line is respectively coupled to the resistive memory cell of the plurality of storage line, The plurality of wordline is respectively coupled to the resistive memory cell of the plurality of storage row.

7. resistance-type memory as claimed in claim 6, wherein when the absolute value of this voltage difference is less than a reset voltage value, should This first resistance value that the overlapping region of the first doped region and this grid provides is equal to a high impedance value, absolute when this voltage difference When value is incremented by not less than this reset voltage value, this first resistance value of the overlapping region offer of this first doped region and this grid It is changed to a low impedance value,

Wherein, this high impedance value is more than this low impedance value.

8. resistance-type memory as claimed in claim 7, wherein when the absolute value of this voltage difference is less than a setting voltage value, should This second resistance value that the overlapping region of the second doped region and this grid provides is equal to this low impedance value, absolute when this voltage difference When value is incremented by not less than this setting voltage value, this second resistance value of the overlapping region offer of this second doped region and this grid It is changed to this high impedance value.

9. resistance-type memory as claimed in claim 8, wherein this reset voltage value are equal to this setting voltage value.

10. resistance-type memory as claimed in claim 6, wherein this first doped region are one of them of drain electrode and source electrode, its In this second doped region be drain electrode and source electrode another.