CN104037207A - Memory device and method of manufacturing the same - Google Patents
Memory device and method of manufacturing the same Download PDFInfo
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- CN104037207A CN104037207A CN201310073110.6A CN201310073110A CN104037207A CN 104037207 A CN104037207 A CN 104037207A CN 201310073110 A CN201310073110 A CN 201310073110A CN 104037207 A CN104037207 A CN 104037207A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000003860 storage Methods 0.000 claims abstract description 65
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- 238000000034 method Methods 0.000 claims description 114
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- 239000003989 dielectric material Substances 0.000 claims description 37
- 239000011232 storage material Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000000694 effects Effects 0.000 abstract description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 17
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- 238000001312 dry etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
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- 229920005591 polysilicon Polymers 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
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Abstract
The invention relates to a memory element and a manufacturing method thereof. The memory device includes a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. Wherein the first dielectric layer is disposed on the substrate. The T-shaped gate is arranged on the first dielectric layer and is provided with an upper gate and a lower gate, and two gaps are respectively arranged on two sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded in the gaps. The second dielectric layer is arranged between the charge storage layer and the upper grid, between the charge storage layer and the lower grid and between the charge storage layer and the substrate. The invention also provides a manufacturing method of the memory element. Therefore, the two charge storage regions are separated by the lower grid of the T-shaped grid, and the positioned charge storage region can be provided, so that the charges can be completely positioned and stored, the second bit effect is reduced, and the programming interference is reduced.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of memory cell and manufacture method thereof.
Background technology
In various memory body products, nonvolatile memory allows data programing repeatedly, reads and erase operation, even after the power interruptions of memory body, can also preserve the data that are stored in wherein.Due to these advantages, nonvolatile memory has become widely used memory body in PC and electronic equipment.Can programming and erasable nonvolatile memory body technology by electricity of the application charge storing structure of knowing, as electronics erasable programmable read-only memory (EEPROM) and fast flash memory bank (flash memory), has been used in various modernizations application.
Fast flash memory bank is designed to have memory cell, and it can be programmed and read independently.General fast flash memory bank memory cell by charge storage in floating grid.The charge-trapping structure that another kind of fast flash memory bank is used non-conductive material (for example silicon nitride) to form, to replace the conductor material of floating grid.When charge-trapping memory cell is programmed, electric charge is captured and can move through idioelectric charge-trapping structure.When not continuing supply power supply, electric charge can remain in electric charge capture layer always, maintains its data mode, until memory cell is wiped free of.It is two end memory cells (two-sided cell) that charge-trapping memory cell can be manipulated into.That is to say, because electric charge can not move through non-conductor electric charge capture layer, so electric charge can be positioned at different charge-trapping places.In other words, in the flash memory device of charge-trapping structural type, in each memory cell, can store an information more than bit.Conventionally, the memory cell with charge-trapping structure can store four kinds of different bit combinations (00,01,10 and 11), and each has corresponding start voltage.At during read operations, flow through the electric current of memory cell because of the start voltage difference of memory cell.Conventionally, this electric current can have four different values, and wherein each is corresponding to different start voltages.Therefore,, by detecting this electric current, can judge the bit combination being stored in memory cell.
All effectively ranges of charge or start voltage scope can classify as memory body operation window (memory operation window).In other words, memory body operation window defines by program level (level) and the difference of wiping between level.Due to the good electrical between the various states of memory cell action need divide equally from, therefore need large memory body operation window.Yet the usefulness of two bit memory cells reduces along with so-called " second bit effect " conventionally.Under second bit effect, in charge-trapping structure, the electric charge of localization affects each other.For example, during reverse read, apply to read and be biased into drain electrode end and the electric charge (i.e. the first bit) being stored near source area detected.Yet the bit (being second bit) near drain region produces the potential barrier reading near the first bit of source area afterwards.This energy barrier can overcome by applying suitable bias voltage, uses drain-induced energy barrier to reduce (DIBL) effect and suppresses the effect near the second bit of drain region, and allow to detect the storing state of the first bit.Yet, when being programmed paramount start voltage state near the second bit of drain region and near the first bit of source area during at programming state not, second bit has improved in fact energy barrier.Therefore,, along with the start voltage about second bit increases, the bias voltage that reads of the first bit has not enough overcome the potential barrier that second bit produces.Therefore,, due to the start voltage increase of second bit, the start voltage of the first bit improves, thereby has reduced memory body operation window.Second bit effect has reduced the operation window of two bit memory bodys.Therefore, need a kind of method and element that can suppress the second bit effect in memory cell badly.
As can be seen here, above-mentioned existing memory cell and manufacture method thereof, in product structure, manufacture method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is completed by development always, and common product and method do not have appropriate structure and method to address the above problem, this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of new memory cell and manufacture method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to, overcome the defect that existing memory cell and manufacture method thereof exist, and provide a kind of new memory cell and manufacture method thereof, technical problem to be solved is to make it that charge storage region of location can be provided, so that electric charge localization storage completely, reduce second bit effect, and reduce programming and disturb, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of memory cell proposing according to the present invention, it comprises the first dielectric layer, T-shaped grid, two electric charge storage layers and 2 second dielectric layers.The first dielectric layer is disposed on substrate.T-shaped gate configuration is on the first dielectric layer and have upper gate and bottom grid, and wherein two spaces are present in respectively between the both sides and upper gate and substrate of bottom grid.Electric charge storage layer embeds in space respectively.The second dielectric layer is disposed between electric charge storage layer and upper gate, between electric charge storage layer and bottom grid and between electric charge storage layer and substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory cell, the thickness of wherein said the first dielectric layer is less than or equal to the thickness of the second dielectric layer.
Aforesaid memory cell, the ratio of the thickness of wherein said bottom grid and the thickness of upper gate is approximately 2～1/25.
Aforesaid memory cell, also comprises two doped regions and word line.Doped region is disposed in the substrate of T-shaped grid both sides.Word line is disposed on T-shaped grid and with T-shaped grid and is electrically connected.
Aforesaid memory cell, the material of wherein said electric charge storage layer comprises silicon nitride or doped polycrystalline silicon.
Aforesaid memory cell, wherein the border of each electric charge storage layer protrudes from the border of upper gate.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of memory cell proposing according to the present invention.It comprises the following steps: on substrate, form a plurality of stacked structures, each stacked structure comprises the first dielectric layer, bottom grid and the sacrificial pattern of configuration from bottom to top, and wherein two spaces are present in respectively between the both sides of each bottom grid and the sacrificial pattern and substrate of correspondence.In space below each sacrificial pattern, form two electric charge storage layers and 2 second dielectric layers, wherein the second dielectric layer be disposed between electric charge storage layer and sacrificial pattern, between electric charge storage layer and bottom grid and between electric charge storage layer and substrate.Form the 3rd dielectric layer to fill up a plurality of gaps between stacked structure.Remove sacrificial pattern, to form a plurality of openings in the 3rd dielectric layer.In opening, form respectively a plurality of upper gate, wherein each upper gate and corresponding bottom grid form a T-shaped grid.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory cell, the method that wherein forms above-mentioned stacked structure comprises the following steps.On substrate, form the first dielectric materials layer, bottom gate material layers and sacrifice layer.On sacrifice layer, form patterned mask layer.Take patterned mask layer as mask, remove partial sacrifice layer and part bottom gate material layers, to form bottom grid and to be positioned at the sacrificial pattern on the grid of bottom.Cut down the width of bottom grid, to form two undercutting below each sacrificial pattern.Remove the first dielectric materials layer not covered by the bottom grid through cutting down, to form respectively the first dielectric layer below the grid of bottom.
The manufacture method of aforesaid memory cell, the material of wherein said patterned mask layer comprises photoresistance, advanced patterned film or its combination.
The manufacture method of aforesaid memory cell, the method that wherein forms above-mentioned the first dielectric materials layer comprises carries out boiler tube technique, chemical vapor deposition method or atom layer deposition process.
The manufacture method of aforesaid memory cell, the method for wherein cutting down the width of above-mentioned bottom grid comprises carries out wet etching process.
The manufacture method of aforesaid memory cell, the method that wherein removes the first dielectric materials layer not covered by the above-mentioned bottom grid through cutting down comprises carries out wet etching process.
The manufacture method of aforesaid memory cell, the material of wherein said sacrifice layer comprises silicon nitride.
The manufacture method of aforesaid memory cell, the method that wherein forms above-mentioned electric charge storage layer and the second dielectric layer comprises the following steps.On substrate, form the second dielectric materials layer, wherein the second dielectric materials layer covers the substrate between stacked structure and stacked structure.Form charge storage material layer, wherein charge storage material layer covers the second dielectric materials layer and fills up space.Remove Partial charge storage material layer and part the second dielectric materials layer.
The manufacture method of aforesaid memory cell, the method that wherein forms above-mentioned the second dielectric materials layer comprises carries out chemical vapor deposition method or atom layer deposition process.
The manufacture method of aforesaid memory cell, the method that wherein forms above-mentioned charge storage material layer comprises carries out boiler tube technique, chemical vapor deposition method or atom layer deposition process.
The manufacture method of aforesaid memory cell, the method that wherein removes Partial charge storage material layer and part the second dielectric materials layer comprises carries out dry etching process.
The manufacture method of aforesaid memory cell, wherein after the step that forms above-mentioned electric charge storage layer and the second dielectric layer and before the step of formation the 3rd dielectric layer, said method is also included in the substrate of stacked structure both sides and forms a plurality of doped regions.After forming the step of above-mentioned upper gate, said method is also included in and on T-shaped grid, forms word line and word line and the electric connection of T-shaped grid.
The manufacture method of aforesaid memory cell, the thickness of wherein said the first dielectric layer is less than or equal to the thickness of the second dielectric layer.
The manufacture method of aforesaid memory cell, the ratio of the thickness of wherein said bottom grid and the thickness of upper gate is approximately 2～1/25.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory cell of the present invention and manufacture method thereof at least have following advantages and beneficial effect: in the memory cell of manufacturing of the present invention, bottom grid by T-shaped grid separates two charge storage region, the charge storage region of location can be provided, so that electric charge localization storage completely, obtain preferably second bit, and significantly reduce programming and disturb.
In sum, the invention relates to a kind of memory cell and manufacture method thereof.This memory cell, it comprises the first dielectric layer, T-shaped grid, two electric charge storage layers and 2 second dielectric layers.The first dielectric layer is disposed on substrate.T-shaped gate configuration is on the first dielectric layer and have upper gate and bottom grid, and wherein two spaces are present in respectively between the both sides and upper gate and substrate of bottom grid.Electric charge storage layer embeds in space respectively.The second dielectric layer is disposed between electric charge storage layer and upper gate, between electric charge storage layer and bottom grid and between electric charge storage layer and substrate.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to 1H is the generalized section of the manufacture method of the memory cell that illustrates according to one embodiment of the invention.
Fig. 1 H-1 is the generalized section of the memory cell that illustrates according to another embodiment of the present invention.
1,1a: memory cell 10: substrate
12: the first dielectric materials layer 12a: the first dielectric layer
14: bottom gate material layers 14a, 14b: bottom grid
15: undercutting 16: sacrifice layer
16a: sacrificial pattern 17: patterned mask layer
18: advanced patterned film 19: photoresist layer
20: space 21: stacked structure
22: the second dielectric materials layer 22a: clearance wall
22b: the second dielectric layer 23: doped region
24a: charge storage material layer 24a: electric charge storage layer
25: 26: the three dielectric layers in gap
27: opening 28: upper gate
29:T type grid 30: word line
T1, t2: thickness
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, memory cell and its embodiment of manufacture method, structure, method, step, feature and effect thereof to proposing according to the present invention, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known and present in the following detailed description coordinating with reference to graphic preferred embodiment.By the explanation of embodiment, should be to reach technological means and the effect that predetermined object takes to obtain one more deeply and concrete understanding to the present invention, yet appended graphic being only to provide with reference to the use with explanation, is not used for the present invention to be limited.
Figure 1A to 1H is the generalized section of the manufacture method of the memory cell that illustrates according to one embodiment of the invention.
Refer to shown in Figure 1A, on substrate 10, sequentially form the first dielectric materials layer 12, bottom gate material layers 14 and sacrifice layer 16.The material of substrate 10 comprises semiconductor, for example, on silicon or insulating barrier, have silicon (SOI).The material of substrate 10 can be also other semiconducting compound.The material of the first dielectric materials layer 12 is for example silica or other suitable materials.The formation method of the first dielectric materials layer 12 comprises the furnace oxidation method of carrying out, chemical vapor deposition method, atom layer deposition process or other suitable technique.The material of bottom gate material layers 14 comprises doped polycrystalline silicon.The formation method of bottom gate material layers 14 is for example to utilize chemical vapor deposition method to form after undoped polycrystalline silicon layer, carries out implanted ions step to form.Or the formation method of bottom gate material layers 14 can be also to utilize chemical vapor deposition method form polysilicon layer and adulterating when participating in the cintest.The material of sacrifice layer 16 comprises silicon nitride, and its formation method comprises and carries out chemical vapor deposition method, atom layer deposition process or other suitable technique.In addition, the thickness of the first dielectric materials layer 12 is for example approximately 30～80 dusts, and the thickness of bottom gate material layers 14 is for example approximately 80～200 dusts, and the thickness of sacrifice layer 16 is for example approximately 100～2,000 dust.
Then, on sacrifice layer 16, form patterned mask layer 17.The material of patterned mask layer 17 comprises advanced patterned film (the Advanced Patterning Film of photoresistance, Applied Materials (Applied Materials, Inc.of Santa Clara, California)
tM, APF) or its combination.In one embodiment, patterned mask layer 17 is the stacked structure that comprises the advanced patterned film 18 of lower floor and the photoresist layer 19 on upper strata, as shown in Figure 1A.The pattern of photoresist layer 19 can form via exposure and the mode of developing.The pattern of advanced patterned film 18 can be shifted the pattern of photoresist layer 19 to form downwards by etch process.(do not illustrate) in another embodiment, patterned mask layer 17 can be also single rete.
Refer to shown in Figure 1B, take patterned mask layer 17 as mask, remove partial sacrifice layer 16 and part bottom gate material layers 14, to form at least two bottom grid 14a and to be positioned at a plurality of sacrificial pattern 16a on the grid 14a of bottom.The method that removes partial sacrifice layer 16 and part bottom gate material layers 14 comprises carries out dry etching process or other suitable technique.Then, remove patterned mask layer 17.The method that removes patterned mask layer 17 comprises carries out dry etching process or other suitable technique.
Refer to shown in Fig. 1 C, cut down the width of bottom grid 14a, to produce undercutting 15 below each sacrificial pattern 16a.In specific words, it is out exposed that the bottom grid 14b through cutting down makes the part bottom of sacrificial pattern 16a.The method of cutting down the width of bottom grid 14a comprises carries out wet etching process or other suitable technique.
Refer to shown in Fig. 1 D, remove the first dielectric materials layer 12 not covered by the bottom grid 14b through cutting down, to form respectively a plurality of the first dielectric layer 12a below the grid 14b of bottom.The method that removes the first dielectric materials layer 12 not covered by the bottom grid 14b through cutting down comprises carries out wet etching process or other suitable technique.Now, two spaces 20 are present in respectively between the both sides of each bottom grid 14b and the sacrificial pattern 16a and substrate 10 of correspondence.This space 20 is as positioning storage space (local storage space).The bottom grid 14b of each first dielectric layer 12a, correspondence and corresponding sacrificial pattern 16a form stacked structure 21.
Based on above-mentioned, can on substrate 10, form a plurality of stacked structures 21, each stacked structure 21 comprises the first dielectric layer 12a, bottom grid 14b and the sacrificial pattern 16a of configuration from bottom to top, and wherein two spaces 20 are present in respectively between the both sides of each bottom grid 14b and the sacrificial pattern 16a and substrate 10 of correspondence.Can form above-mentioned stacked structure 21 with reference to step or other the suitable steps of Figure 1A to 1D.
Refer to shown in Fig. 1 E, on substrate 10, form the second dielectric materials layer 22, the substrate 10 that wherein the second dielectric materials layer 22 covers between stacked structure 21 and stacked structure 21.In specific words, the second dielectric materials layer 22 conformally covers upper surface, sidewall and the bottom of stacked structure 21 and the surface of substrate 10 completely.The second dielectric materials layer 22 fills among the space 20 shown in Fig. 1 D, but does not fill up space 20.The thickness of the second dielectric materials layer 22 is more than or equal to the thickness of the first dielectric layer 12a.The thickness of the second dielectric materials layer 22 is for example approximately 30～80 dusts.The material of the second dielectric materials layer 22 is for example silica, and its formation method comprises that the steam of coming personally produces (ISSG) oxidizing process, chemical vapor deposition method or atom layer deposition process.Be noted that especially the second dielectric materials layer 22 can adopt depositing operation, bottom grid 14b be oxidized avoiding.Or, can adopt any applicable technique to make the second dielectric materials layer 22, only otherwise by all oxidations of bottom grid 14b.Then, form charge storage material layer 24, wherein charge storage material layer 24 covers the second dielectric materials layer 22 and fills up space 20.The material of charge storage material layer 24 comprises silicon nitride or doped polycrystalline silicon.The formation method of silicon nitride is for example boiler tube nitriding, chemical vapor deposition method or atom layer deposition process.The formation method of doped polycrystalline silicon is for example to utilize chemical vapor deposition method form polysilicon layer and adulterating when participating in the cintest.
Refer to shown in Fig. 1 F, remove Partial charge storage material layer 24 and part the second dielectric materials layer 22, to form two electric charge storage layer 24a and 2 second dielectric layer 22b in two spaces 20 below each sacrificial pattern 16a.The second dielectric layer 22b is disposed between electric charge storage layer 24a and sacrificial pattern 16a, between electric charge storage layer 24a and bottom grid 14b and between electric charge storage layer 24a and substrate 10.The method that removes Partial charge storage material layer 24 and part the second dielectric materials layer 22 comprises carries out anisotropic etch process, for example dry etching process.In addition,, in forming the step of electric charge storage layer 24a and the second dielectric layer 22b, also can the while form clearance wall 22a at the sidewall of each sacrificial pattern 16a.
Then, form a plurality of doped regions 23 in the substrate 10 of stacked structure 21 both sides, wherein adjacent stacked structure 21 shares a doped region 23.The method that forms doped region 23 comprises carries out ion implantation technology.The conduction type of doped region 23 is different from the conduction type of substrate 10.In one embodiment, when substrate 10 has the doping of P type; There is N-type doping doped region 23.In another embodiment, substrate 10 has N-type doping; There is the doping of P type doped region 23.N-type doping is for example phosphorus or arsenic; The doping of P type is for example boron or boron difluoride.Doped region 23 is as source area or the drain region of memory cell.
Afterwards, form the 3rd dielectric layer 26 to fill up a plurality of gaps 25 between stacked structure 21.In specific words, the 3rd dielectric layer 26 is inserted the gap 25 between adjacent two stacked structures 21 and is had smooth surface, and exposes the surface of the sacrificial pattern 16a of stacked structure 21.The material of the 3rd dielectric layer 26 comprises silica, and its formation method comprises by chemical vapor deposition method and form dielectric materials layer, carries out afterwards flatening process again.Flatening process is for example etch back process or chemical mechanical milling tech (CMP).
Refer to shown in Fig. 1 G, remove sacrificial pattern 16a, to form a plurality of openings 27 in the 3rd dielectric layer 26.In specific words, opening 27 exposes the surface of the second dielectric layer 22b and the surface of bottom grid 14b.The method that removes sacrificial pattern 16a comprises carries out isotropic etching technique, for example dry etching process, wet etching process or other suitable technique.
Refer to shown in Fig. 1 H, form respectively a plurality of upper gate 28 in opening 27, wherein each upper gate 28 and corresponding bottom grid 14b form a T-shaped grid 29.The material of upper gate 28 comprises doped polycrystalline silicon.The formation method of upper gate 28 comprises by chemical vapor deposition method and forms upper gate material layer, wherein upper gate layer of material covers the 3rd dielectric layer 26 insert opening 27.Upper gate material layer is for example to utilize chemical vapor deposition method to form after undoped polycrystalline silicon layer, carries out implanted ions step.Or the formation method of upper gate material layer can be also to utilize chemical vapor deposition method form polysilicon layer and adulterating when participating in the cintest.Afterwards, utilize chemical mechanical milling tech to remove upper gate material layer outside opening 27 to form.
Then, on T-shaped grid 29, form word line 30, and word line 30 is electrically connected with T-shaped grid 29.In one embodiment, the direction that word line 30 extends is different from the direction that extend doped region 23, for example, be that both are roughly vertical.The method of the formation of word line 30 comprises the wordline material layer that first forms code-pattern, then by wordline material layer pattern to form.The material of wordline material layer comprises conductor material, for example doped polycrystalline silicon, metal, metal alloy or its combination.The formation method of doped polycrystalline silicon is for example to utilize chemical vapor deposition method to form after undoped polycrystalline silicon layer, carries out implanted ions step to form.The formation method of doped polycrystalline silicon can be also to utilize chemical vapor deposition method form polysilicon layer and adulterating when participating in the cintest.The formation method of metal or metal alloy is for example sputtering method or chemical vapor deposition method, or other suitable techniques.So far, complete memory cell 1 of the present invention.
Below, with reference to Fig. 1 H, memory cell of the present invention is described.Memory cell 1 of the present invention comprises a plurality of memory cells (for example Fig. 1 H take two memory cells be example), and each memory cell comprises the first dielectric layer 12a, T-shaped grid 29, two electric charge storage layer 24a, 2 second dielectric layer 22b, two doped regions 23 and word lines 30.The first dielectric layer 12a is disposed on substrate 10.The thickness of the first dielectric layer 12a is approximately 30～80 dusts.T-shaped grid 29 is disposed at the first dielectric layer 12a above and has upper gate 28 and bottom grid 14b.The thickness of bottom grid 14b is approximately 80～200 dusts, and the thickness of upper gate 28 is approximately 100～2,000 dust.In addition, the ratio of the thickness of the thickness of bottom grid 14b and upper gate 28 is approximately 2～1/25.At this, two spaces 20 are present in respectively between the both sides and upper gate 28 and substrate 10 of bottom grid 14b.In one embodiment, the sidewall of the sidewall of bottom grid 14b and the first dielectric layer 12a trims.Doped region 23 is disposed in the substrate 10 of T-shaped grid 29 both sides.Word line 30 is disposed on T-shaped grid 29 and with T-shaped grid 29 and is electrically connected.
Electric charge storage layer 24a embeds respectively in space 20.The material of electric charge storage layer 24a comprises silicon nitride or doped polycrystalline silicon.In one embodiment, the border of each electric charge storage layer 24a protrudes from the border of upper gate 28, as shown in Fig. 1 H.(do not illustrate) in another embodiment, the border of each electric charge storage layer 24a also can trim with the border of upper gate 28.The second dielectric layer 22b is disposed between electric charge storage layer 24a and upper gate 28, between electric charge storage layer 24a and bottom grid 14b and between electric charge storage layer 24a and substrate 10.The thickness of the second dielectric layer 22b is approximately 30～80 dusts.In addition, the thickness t 1 of the first dielectric layer 12a is less than or equal to the thickness t 2 of the second dielectric layer 22b.In the embodiment of Fig. 1 H, be to take thickness t 2 that the thickness t 1 of the first dielectric layer 12a equals the second dielectric layer 22b to illustrate as example, but the present invention is not as limit.In another embodiment, the thickness t 1 of the first dielectric layer 12a also can be less than the thickness t 2 of the second dielectric layer 22b, as shown in the memory cell 1a of Fig. 1 H-1.
In each memory cell of memory cell 1 of the present invention and 1a, the first dielectric layer 12a is as gate dielectric layer.Be positioned at the second dielectric layer 22b of electric charge storage layer 24a below as tunneling dielectric layer, and at dielectric layer between electric charge storage layer 24a and bottom grid 14b and between the second dielectric layer 22b between electric charge storage layer 24a and upper gate 28 is as lining or grid.In this embodiment, lining/or grid between the thickness of dielectric layer and tunneling dielectric layer identical, but the present invention is not as limit.This area has common knowledge and obtains technical staff and should be appreciated that, also can make dielectric layer and tunneling dielectric layer between the lining/grid with different-thickness.Doped region 23 is as source/drain.
In sum, memory cell of the present invention separates two electric charge storage layers by the bottom grid (it is that conductor material is for example doped polycrystalline silicon) of T-shaped grid, the charge storage region of location can be provided, so that electric charge localization storage completely, reduce second bit effect, and reduce programming and disturb.In addition, in the manufacture method of memory cell of the present invention, design by T-shaped grid and make the thickness of tunneling dielectric layer (being the second dielectric layer of electric charge storage layer below) be more than or equal to the mode of the thickness of gate dielectric layer (i.e. the first dielectric layer), two charge storage region can be separated effectively, significantly to reduce second bit effect, and then lift element usefulness.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the method for above-mentioned announcement and technology contents to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
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| US20030094662A1 (en) * | 2001-11-21 | 2003-05-22 | Geum-Jong Bae | MOS transistor having a T-shaped gate electrode and method for fabricating the same |
| CN1870249A (en) * | 2005-02-18 | 2006-11-29 | 英飞凌科技股份公司 | Charge-trapping memory device and method for production |
| US20090061650A1 (en) * | 2007-08-30 | 2009-03-05 | Spansion Llc | Sacrificial nitride and gate replacement |
| WO2009032678A1 (en) * | 2007-09-03 | 2009-03-12 | Spansion Llc | Semiconductor device and method for manufacturing thereof |
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| US20030094662A1 (en) * | 2001-11-21 | 2003-05-22 | Geum-Jong Bae | MOS transistor having a T-shaped gate electrode and method for fabricating the same |
| CN1870249A (en) * | 2005-02-18 | 2006-11-29 | 英飞凌科技股份公司 | Charge-trapping memory device and method for production |
| US20090061650A1 (en) * | 2007-08-30 | 2009-03-05 | Spansion Llc | Sacrificial nitride and gate replacement |
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Application publication date: 20140910 |