CN104037058A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising forming a polysilicon layer on a semiconductor substrate; performing a photolithography process and a metal silicide process to form a metal silicide layer, and the metal silicide layer satisfies: (S1/ The ratio of S2) is 0.8 to 1.2 times the ratio of (RSH1*TCT1)/(RSH2*TCT2), where S1 is the area of the metal silicide layer, RSH1 is the sheet resistance of the metal silicide layer, and TCT1 is the area of the metal silicide layer The temperature coefficient of resistance, S2 is the area of the polysilicon layer not covered with the metal silicide layer, RSH2 is the sheet resistance of the polysilicon layer not covered with the metal silicide layer, and TCT2 is the temperature coefficient of resistance of the polysilicon layer not covered with the metal silicide layer. The invention adopts the combination of metal silicided polysilicon material or non-metal silicided polysilicon material, so that the resistance temperature coefficient of the polysilicon resistance device can be kept substantially constant.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the field of integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

In the field of semiconductor device manufacturing, polysilicon resistors are widely used. In particular, polysilicon resistors are often used in CMOS and BiCOMS processes. For example, polysilicon used in the gate structure of MOS transistors is heavily doped to improve conductivity. Usually, the sheet resistance is 25Ω/square to 50Ω/square. At present, polysilicon resistors are widely used in semiconductor devices as precise passive resistors (Precise Passive resistorDevices) with metal silicided polysilicon materials or polysilicon materials without metal silicide.

However, resistance devices have a common defect, that is, the resistance value drifts with the change of temperature, so the resistance value of the resistance device will drift during the actual operation of the semiconductor device, which will affect the performance of the device's working stability and power consumption.

Contents of the invention

The object of the present invention is to provide a semiconductor device having a polysilicon resistance with a constant temperature resistance coefficient and a manufacturing method thereof.

In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

forming a polysilicon layer on a semiconductor substrate;

forming at least two photoresist patterns on the polysilicon layer, and the photoresist patterns are arranged at intervals;

A metal silicide layer is formed on the polysilicon layer not covered by the photoresist pattern, and the metal silicide layer satisfies:

The ratio of (S1/S2) is 0.8 to 1.2 times the ratio of (RSH1*TCT1)/(RSH2*TCT2)

Among them, S1 is the area of the metal silicide layer, RSH1 is the sheet resistance of the metal silicide layer, TCT1 is the temperature coefficient of resistance of the metal silicide layer, S2 is the area of the polysilicon layer not covered by the metal silicide layer, and RSH2 is the area not covered by the metal silicide layer. The sheet resistance of the polysilicon layer covered by the metal silicide layer, TCT2 is the temperature coefficient of resistance of the polysilicon layer not covered by the metal silicide layer.

Further, the metal silicide layer satisfies:

The ratio of (S1/S2) is equal to the ratio of (RSH1*TCT1)/(RSH2*TCT2).

Further, the shape of the metal silicide layer is square.

Further, the width of the metal silicide layer is equal to the width of the polysilicon layer not covered by the metal silicide layer, and the metal silicide layer satisfies:

The ratio of (L1/L2) to (RSH1*TCT1)/(RSH2*TCT2) is 0.8 to 1.2

Wherein, L1 is the length of the metal silicide layer, and L2 is the length of the polysilicon layer not covered by the metal silicide layer.

Further, the metal silicide layer satisfies:

The ratio of (L1/L2) is equal to the ratio of (RSH1*TCT1)/(RSH2*TCT2).

The present invention also provides a semiconductor device, comprising: a semiconductor substrate, a polysilicon layer formed on the semiconductor substrate, and a metal silicide layer arranged at intervals on the polysilicon layer, and the metal silicide layer satisfies:

The ratio of (S1/S2) is 0.8 to 1.2 times the ratio of (RSH1*TCT1)/(RSH2*TCT2), where S1 is the area of the metal silicide layer, RSH1 is the sheet resistance of the metal silicide layer, and TCT1 is the metal The temperature coefficient of resistance of the silicide layer, S2 is the area of the polysilicon layer not covered by the metal silicide layer, RSH2 is the sheet resistance of the polysilicon layer not covered by the metal silicide layer, TCT2 is the polysilicon layer not covered by the metal silicide layer layer temperature coefficient of resistance.

Further, the metal silicide layer satisfies:

The ratio of (S1/S2) is equal to the ratio of (RSH1*TCT1)/(RSH2*TCT2).

Further, the shape of the metal silicide layer is square.

Further, the width of the metal silicide layer is equal to the width of the polysilicon layer not covered with the metal silicide layer, and the metal silicide layer satisfies:

The ratio of (L1/L2) to (RSH1*TCT1)/(RSH2*TCT2) is 0.8 to 1.2

Wherein, L1 is the length of the metal silicide layer, and L2 is the length of the polysilicon layer not covered by the metal silicide layer.

Further, the metal silicide layer satisfies:

The ratio of (L1/L2) is equal to the ratio of (RSH1*TCT1)/(RSH2*TCT2).

In summary, the semiconductor device and its manufacturing method described in the present invention adopt polysilicon resistance devices combined with metal silicided polysilicon materials or non-metal silicided polysilicon materials; The polysilicon material without metal silicidation is designed so that the temperature coefficient of resistance of the polysilicon resistance device remains basically constant. In the actual working process of the semiconductor device, the resistance value drift will not occur, thereby improving the working stability and power consumption of the semiconductor device. and other performance.

Description of drawings

1 is a schematic flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

Fig. 2 is a structural schematic diagram during the fabrication process of the semiconductor device described in an embodiment of the present invention;

3 is a schematic cross-sectional view of a semiconductor device described in an embodiment of the present invention;

4 is a top view of a semiconductor device described in an embodiment of the present invention;

FIG. 5 is a schematic diagram of the variation of the resistance value of the semiconductor device with temperature according to an embodiment of the present invention.

Detailed ways

The method for manufacturing a semiconductor device and the semiconductor device proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

It has been mentioned in the background art that the existing polysilicon resistors are widely used as precise passive resistors (Precise Passive resistor Devices) in semiconductor devices, polysilicon material with metal silicide or polysilicon material without metal silicide. Among them, the polysilicon material with metal silicide usually has a positive temperature coefficient of resistance (Temperature Coefficient of Resistance), that is, the temperature increases, and the resistance increases; for the polysilicon material without metal silicide, it usually has a negative temperature coefficient of resistance, That is, as the temperature decreases, the resistivity decreases. Therefore, the existing polysilicon resistance device does not produce resistance value drift during the actual working process of the semiconductor device, which further affects the performance of the semiconductor device such as working stability and power consumption.

For this reason, the present invention proposes a kind of semiconductor device and its manufacturing method, adopts the polysilicon resistance device that the polysilicon material of metal silicidation or the polysilicon material that does not carry out metal silicidation combines, and in the manufacturing process through the polysilicon material of metal silicidation or not The polysilicon material that is silicided is designed so that the temperature coefficient of resistance of the polysilicon resistance device remains basically constant, thereby improving the performance of the semiconductor device such as stability and power consumption.

Fig. 1 is a schematic flow chart of a manufacturing method of a semiconductor device described in an embodiment of the present invention, Fig. 2 is a schematic structural view of the manufacturing process of a semiconductor device described in an embodiment of the present invention, and Fig. 3 is an embodiment of the present invention A schematic cross-sectional view of the semiconductor device described in . In order to solve the above-mentioned problem, in conjunction with Fig. 1 to Fig. 3, the present invention proposes a kind of manufacturing method of semiconductor device, comprises the following steps:

Step S01: forming a polysilicon layer 102 on a semiconductor substrate 100, as shown in FIG. 2;

Step S02: performing a photolithography process to form at least two photoresist patterns 103 on the polysilicon layer 102, and the photoresist patterns 103 are arranged at intervals, as shown in FIG. 2 ;

Step S03: performing a metal silicide process to form a metal silicide layer 104 on the exposed polysilicon layer 102, as shown in FIG. 3 , the metal silicide layer 104 satisfies:

The ratio of (S1/S2) satisfies 0.8 to 1.2 times the ratio of (RSH1*TCT1)/(RSH2*TCT2), that is, the ratio of (S1*RSH1*TCT1)/(S2*RSH2*TCT2) is 0.8 to 1.2, Wherein S1 is the area of the metal silicide layer 104, RSH1 is the square resistance of the metal silicide layer 104, TCT1 is the temperature coefficient of resistance of the metal silicide layer 104, and S2 is the area of the polysilicon layer 102 that does not cover the metal silicide layer (i.e. Area of the polysilicon layer 102 not covered by the metal silicide layer), RSH2 is the sheet resistance of the polysilicon layer 102 not covered by the metal silicide layer, and TCT2 is the temperature coefficient of resistance of the polysilicon layer not covered by the metal silicide layer.

In step S03, it specifically includes: first depositing metal material, then removing the photoresist pattern, and then performing a thermal annealing process to form a metal silicide layer 104 on the polysilicon layer 102, and the specific technique of formation is well known to those skilled in the art Technical content, so no more details.

Fig. 4 is a top view of the semiconductor device described in an embodiment of the present invention, referring to Fig. 4, in a preferred embodiment, the shape of the photoresist pattern 103 is square, and the photoresist pattern 103 is The width of the metal silicide layer is equal to the width of the area not covered by the photoresist pattern 103, then the shape of the metal silicide layer 104 is also square and arranged regularly at intervals, and the width of the metal silicide layer is the same as the uncovered area. The width of the polysilicon layer of the metal silicide layer is equal, then by: S1=W*L1, S2=W*L2, it can be obtained

The ratio of (L1/L2) to (RSH1*TCT1)/(RSH2*TCT2) is 0.8 to 1.2

Where L1 is the length of the metal silicide layer, L1=L11+L12+L13, L2 is the length of the polysilicon layer not covered with the metal silicide layer, L2=L21+L22.

Under optimal process conditions, the temperature coefficient of resistance of the formed polysilicon resistance device can be kept constant, that is, the ratio of (S1*RSH1*TCT1)/(S2*RSH2*TCT2) is 1. For the metal silicide When the width of the material layer is equal to the width of the polysilicon layer not covered with the metal silicide layer, then: the ratio of (L1/L2) is equal to (RSH1*TCT1)/(RSH2*TCT2).

FIG. 5 is a schematic diagram of the variation of the resistance value of the semiconductor device with temperature according to an embodiment of the present invention. 5, through the combination of the resistance R1 of the metal silicide layer 104 with a positive temperature coefficient of resistance and the resistance R2 of the polysilicon layer 102 with a negative temperature coefficient of resistance, the resistance R value of the semiconductor device is basically constant with temperature constant.

In addition, in the manufacturing process of semiconductor devices, the sheet resistance (RSH1) of the metal silicide layer and the temperature coefficient of resistance (TCT1) of the metal silicide layer can be determined according to the manufacturing process conditions of the metal silicide layer (such as deposition temperature, reaction concentration or dopant concentration, etc.) are predetermined, and the sheet resistance (RSH2) of the polysilicon layer not covered with the metal silicide layer and the temperature coefficient of resistance (TCT2) of the polysilicon layer not covered with the metal silicide layer can be determined according to the uncovered The production process conditions of the polysilicon layer of the metal silicide layer (such as deposition temperature, reactant concentration or doping concentration, etc.) are predetermined; therefore, in the actual production process, as long as the above known data obtains the ratio of S1 to S2, or in When the width of the metal silicide layer is equal to the width of the polysilicon layer that does not cover the metal silicide layer, the ratio of L1 to L2 can be directly obtained, so that the semiconductor device can obtain a constant resistance within the error range of plus or minus 20%. Temperature Coefficient. Table 1 shows that in the semiconductor device manufacturing process in an embodiment of the present invention, when the width of the metal silicide layer is equal to the width of the polysilicon layer that does not cover the metal silicide layer, L1 and L2 in multiple semiconductor device structures Determination of the ratio. Table 1

Rsh1 TCR1 Rsh2 TCR2 Rsh2/gshl TCR2/TCR1 L1/L2 Process01 3.81 3.23E-03 283 —4.66E-05 7.43E+01 —1.44E-02 1.07E+00 Process02 9.78 2.92E-03 311.3 —1.63E-04 3.18E+01 —5.58E-02 1.78E+00 Process03 T． 18 2.91E-03 315 —5.07E-05 4.39E+01 —1.74E-02 T． 64E-01 Process04 8.18 2.92E-03 319 —1.63E-04 3.90E+Oi A 5.58E-02 2.][8E+00 Process05 9.78 2.92E-03 322 —2.25E-04 3.29E+01 —7.71E-02 2.54E+00 Process06 9.75 2.98E-03 339 —1.97E-04 3.48E+01 A 6.61E-02 2.30E+00 Process07 7.85 2099E-03 321.5 —5.75E-05 4.1OE+01 —1.92E-02 7.88E-01 Process08 8.678 2.93E-03 313.5 —1.05E-04 3.61E+01 —3.58E-02 1.29E+00 Process09 7. B28 2.88E-03 305 —1.40E-04 4. OOE+01 —4.86E-02 1.94E+00 Processl0 8.414 2.88E-03 336.436 —1.31E-04 4. OOE+01 —4.53E-02 1.81E+00 Process1 1 8.7327 2.85E-03 352.4439 — 1.20E-04 4.04E+01 —4.21E-02 1.70E+00 Processl2 7.5274 2.99E-03 317.05 — 1.04E-04 4.21E+01 —3.48E-02 1.47E+00 Processl3 13.32 2.64E-03 430.13 —1.26E-04 3.23E+01 —4.77E-02 1.54E+00 Proce write mutual 14 16.448 2.68E-03 320.7 — 1.07E-04 1.95E+01 —3.99E-02 7.78E-01 Processl5 15.04 1.78E-03 B15.71 — 1.14E-04 4.ogE+01 A B.40E-02 2.62E+00 Processl6 12.42 2.47E-03 679.21 —1.42E-04 5.47E+01 —5.75E-02 3.14E+00 Process17 14.9 2.60E-03 318.9 —1.97E-04 2.14E+01 —7.58E-02 1.62E+00 Processl8 14.93 2.59E-03 289.3 —1.29E-04 1.94E+01 —4.98E-02 9.65E-01 Process19 10.62 2.47E-03 680.6 A 7.35E-05 6.41E+01 —2.98E-02 1.91E+00 Proc Qius20 16 1.96E-03 645 —1.66E-04 4.03E+01 —8.47E-02 3.41E+00 Process21 12.82 1.92E-03 B24 —1.lOE-04 4.87E+01 —5.73E-02 2.79E+00 Process22 12.42 2.45E-03 273 —3.09E-04 2.20E+01 -1.26E-01 2.77E+00

The present invention also provides a semiconductor device. With reference to FIG. 3 and FIG. 4 , the semiconductor device includes: a semiconductor substrate 100, a polysilicon layer 102 formed on the semiconductor substrate 100, and a polysilicon layer 102 arranged at intervals and on the polysilicon layer 102 A metal silicide layer 104, wherein the metal silicide layer 104 satisfies:

The ratio of (S1/S2) satisfies the O of the ratio of (RSH1*TCT1)/(RSH2*TCT2). 8 to 1.2 times, that is, the ratio of (S1*RSH1*TCTl)/(S2*RSH2*TCT2) is O. 8-1.2, where S1 is the area of the metal silicide layer 104, RSH1 is the sheet resistance of the metal silicide layer 104, TCT1 is the temperature coefficient of resistance of the metal silicide layer 104, and S2 is the polysilicon that does not cover the metal silicide layer The area of the layer 102, RSH2 is the sheet resistance of the polysilicon layer 102 not covered with the metal silicide layer, and TCT2 is the temperature coefficient of resistance of the polysilicon layer 102 not covered with the metal silicide layer.

In a preferred embodiment, in the process of forming the metal silicide layer 104, the width of the metal silicide layer is equal to the width of the polysilicon layer not covered with the metal silicide layer, then by: S1--W *L1, S2=W*L2 can get:

The ratio of (L1/L2) to (RSH1*TCTl)/(RSH2*TCT2) is O. 8~1.2

As shown in Figure 4, L1 is the length of the metal silicide layer, L1=L1 1+L12+L13, L2 is the length of the polysilicon layer not covered with the metal silicide layer, L2=L21+L22.

Under optimal process conditions, the temperature coefficient of resistance of the formed polysilicon resistance device can be kept constant, that is, the ratio of (S1*RSH1*TCT1)/(S2*RSH2*TCT2) is 1. For the metal silicide When the width of the material layer is equal to the width of the polysilicon layer not covered with the metal silicide layer, then: the ratio of (L1/L2) is equal to (RSH1*TCT1)/(RSH2*TCT2).

In summary, the semiconductor device and its manufacturing method described in the present invention adopt polysilicon resistance devices combined with metal silicided polysilicon materials or non-metal silicided polysilicon materials; The polysilicon material without metal silicidation is designed so that the temperature coefficient of resistance of the polysilicon resistance device remains basically constant. In the actual working process of the semiconductor device, the resistance value drift will not occur, thereby improving the working stability and power consumption of the semiconductor device. and other performance.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (10)

1. a manufacture method for semiconductor device, comprising:

In semi-conductive substrate, form polysilicon layer;

On described polysilicon layer, form at least two photoetching offset plate figures, described photoetching offset plate figure is spaced;

On the polysilicon layer not covered by described photoetching offset plate figure, form metal silicide layer, described metal silicide layer meets:

(S1/S2) ratio is 0.8～1.2 times of (RSH1*TCT1)/(RSH2*TCT2) ratio

Wherein, S1 is the area of metal silicide layer, RSH1 is the square resistance of metal silicide layer, TCT1 is the temperature coefficient of resistance of metal silicide layer, S2 is the area of the polysilicon layer that do not covered by metal silicide layer, RSH2 is the square resistance of the polysilicon layer that do not covered by metal silicide layer, and TCT2 is the temperature coefficient of resistance of the polysilicon layer that do not covered by metal silicide layer.

2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described metal silicide layer meets:

(S1/S2) ratio is with (RSH1*TCT1)/(RSH2*TCT2) ratio equates.

3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, being shaped as of described metal silicide layer is square.

4. the manufacture method of semiconductor device as claimed in claim 3, is characterized in that, the width of described metal silicide layer equates with the width of the described polysilicon layer not covered by metal silicide layer, and described metal silicide layer meets:

(L1/L2) ratio with (RSH1*TCT1)/(RSH2*TCT2) ratio is 0.8～1.2

Wherein, the length that L1 is metal silicide layer, L2 is the length of the polysilicon layer that do not covered by metal silicide layer.

5. the manufacture method of semiconductor device as claimed in claim 4, is characterized in that, described metal silicide layer meets:

(L1/L2) ratio is with (RSH1*TCT1)/(RSH2*TCT2) ratio equates.

6. a semiconductor device, comprising: Semiconductor substrate, be formed at the polysilicon layer in Semiconductor substrate and be spaced the metal silicide layer on described polysilicon layer, described metal silicide layer meets:

(S1/S2) ratio is 0.8～1.2 times of (RSH1*TCT1)/(RSH2*TCT2) ratio, wherein, S1 is the area of metal silicide layer, RSH1 is the square resistance of metal silicide layer, TCT1 is the temperature coefficient of resistance of metal silicide layer, S2 is the area of the polysilicon layer that do not covered by metal silicide layer, and RSH2 is the square resistance of the polysilicon layer that do not covered by metal silicide layer, and TCT2 is the temperature coefficient of resistance of the polysilicon layer that do not covered by metal silicide layer.

7. semiconductor device as claimed in claim 6, is characterized in that, described metal silicide layer meets:

(S1/S2) ratio is with (RSH1*TCT1)/(RSH2*TCT2) ratio equates.

8. semiconductor device as claimed in claim 6, is characterized in that, being shaped as of described metal silicide layer is square.

9. semiconductor device as claimed in claim 8, is characterized in that, the width of described metal silicide layer equates with the width of the polysilicon layer of described not covering metal silicide layer, and described metal silicide layer meets:

(L1/L2) ratio with (RSH1*TCT1)/(RSH2*TCT2) ratio is 0.8～1.2

Wherein, the length that L1 is metal silicide layer, L2 is the length of the polysilicon layer that do not covered by metal silicide layer.

10. semiconductor device as claimed in claim 9, is characterized in that, described metal silicide layer meets:

(L1/L2) ratio is with (RSH1*TCT1)/(RSH2*TCT2) ratio equates.