CN104023386B - Transmitting terminal, receiving terminal and its frame synchornization method, frame synchronization system - Google Patents

Abstract

The invention provides a sending end, a receiving end, a frame synchronization method and a frame synchronization system thereof. The frame synchronization method at the sending end includes: performing zero-correlation region extension processing and differential processing on the synchronization sequence, marking the frame header of the data to be synchronized using the sequence obtained by the differential processing, and sending the data to be synchronized after the frame header is marked; the frame at the receiving end The synchronization method includes: receiving the data to be synchronized, performing differential processing on the data to be synchronized to obtain the differential data, performing correlation operations on the differential data and the local sequence to obtain the correlation value data, searching for peaks in the correlation value data, and judging whether the number of peaks reaches the first A default value, if yes, execute the synchronous operation. Through the implementation of the invention, the probability of false alarm and missed detection when the receiving end performs peak search in the data synchronization process is reduced.

Description

Sending end, receiving end, frame synchronization method thereof, and frame synchronization system

technical field

The invention relates to the field of data synchronization in communication technology, in particular to a frame synchronization method at a sending end, a frame synchronization method at a receiving end, a sending end, a receiving end and a frame synchronization system.

Background technique

Digital microwave communication is a point-to-point line-of-sight communication system, which is mainly used in the bearer network of 2G/3G mobile services to transmit voice and data services; and frame synchronization technology occupies a very important position in digital microwave communication. The received signal enters the frame synchronization stage after down-conversion, analog device interference elimination, and digital clock recovery processing. The frame synchronization stage is mainly used to complete the frame header mark to provide frame header indication information, system frequency offset value estimation and frequency offset compensation. It can also indicate the synchronization/out-of-synchronization status of the system, reflecting the quality of the channel conditions.

In the existing synchronization technology, the receiving end judges whether to enter the synchronization state by periodically detecting the code group or code element, and judges whether it is synchronized by comparing the number of occurrences of the code element or code group with a set threshold, and then marks the frame header; This frame synchronization scheme has poor anti-noise and frequency offset capabilities, and the peak detection process is prone to false alarms and high probability of missed detection due to false peaks and low signal-to-noise ratio, which affects the system link establishment speed and stability after establishment.

Contents of the invention

The invention provides a sending end, a receiving end, a frame synchronization method thereof, and a frame synchronization system, which solve the problems of peak detection false alarm and high probability of missing detection existing in the current frame synchronization technology.

The present invention provides a frame synchronization method at the sending end. In one embodiment, the frame synchronization method at the sending end includes: performing zero-correlation area extension processing on the synchronization sequence; performing differential processing on the sequence obtained by the zero-correlation area extension processing; using The frame header of the data to be synchronized is marked on the sequence obtained by the differential processing; and the data to be synchronized after the frame header is marked is sent.

The present invention provides a frame synchronization method at the receiving end. In one embodiment, the frame synchronization method at the receiving end includes: receiving data to be synchronized; performing differential processing on the data to be synchronized to obtain differential data; and correlating the differential data with the local sequence Performing operations to obtain correlation value data; searching for peaks in the correlation value data; judging whether the number of peaks reaches a first preset value; if so, performing a synchronous operation.

The present invention provides a sending end. In one embodiment, the sending end includes: a first processing module, a second processing module, and a sending module; wherein, the first processing module is used to perform zero-correlation region extension processing on the synchronization sequence , and perform differential processing on the processed sequence; the second processing module is used to use the sequence obtained by the differential processing to mark the frame header of the data to be synchronized; the sending module is used to send out the data to be synchronized after the frame header is marked.

The present invention provides a receiving end. In one embodiment, the receiving end includes: a receiving module, a third processing module, a fourth processing module, a search module, a judging module, and a synchronization module; wherein the receiving module is used to receive Synchronize data; the third processing module is used to perform differential processing on the data to be synchronized received by the receiving module to obtain differential data; the fourth processing module is used to perform correlation operations on the differential data obtained by the third processing module and the local sequence to obtain correlation values data; the search module is used to search for the peak value in the correlation value data obtained by the fourth processing module; the judgment module is used to judge whether the number of peaks searched by the search module reaches the first preset value; the synchronization module is used to judge in the judgment module As a result, when the number of peaks reaches a first preset value, a synchronization operation is performed.

The present invention provides a frame synchronization system. In one embodiment, the frame synchronization system includes the sending end and the receiving end provided by the present invention.

Through the implementation of the present invention, a frame synchronization technology is provided. By performing zero-correlation region expansion and differential processing on the synchronization sequence, the sending end reduces the side lobes at both ends of the correlation value peak value, and reduces the time when the receiving end searches for the correlation value peak value. False alarm and missed detection probability; the receiving end performs differential processing on the received data, which restores the impact caused by the differential processing of the data by the sending end, and performs differential processing on both the sending end and the receiving end, so that the system enters synchronization stage, the system frequency offset value calculation and system frequency offset compensation can be quickly performed, which improves the flexibility of the system frequency offset correction; further, the receiving end detects the validity of the peak value, and according to the The synchronization state is judged, and the influence of the invalid peak value on the synchronization judgment is avoided.

Description of drawings

FIG. 1 is a schematic diagram of a frame synchronization method at a sending end provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a frame synchronization method at a receiving end provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a peak search method provided by an embodiment of the present invention;

Fig. 4 is the change curve diagram of the correlation value modulus in an embodiment of the present invention;

Fig. 5 is the change curve diagram of the correlation value modulus in another embodiment of the present invention;

FIG. 6 is a schematic diagram of a frame synchronization system provided by an embodiment of the present invention;

FIG. 7 is a schematic diagram of a sending end provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of a receiving end provided by an embodiment of the present invention;

Fig. 9 is a schematic diagram of a receiving end provided by another embodiment of the present invention.

Detailed ways

In the following, the present invention will be further explained by means of specific embodiments in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a frame synchronization method at a sending end provided by an embodiment of the present invention; as can be seen from FIG. 1 , in this embodiment, the frame synchronization method at a sending end provided by the present invention includes the following steps:

S101: Perform zero-correlation region extension processing on the synchronization sequence.

Preferably, before step S101, the frame synchronization method at the sending end in the embodiment shown in FIG. 1 further includes: a step of selecting a synchronization sequence, which is a constant envelope zero autocorrelation series.

Extending the zero-correlation region of the synchronization sequence can achieve the effect of reducing the sidelobes on both sides of the peak in the correlation value obtained by the correlation operation at the receiving end. There are many ways to realize the zero-correlation region extension. In the optimal embodiment of the present invention, The CAZAC (Constant Amplitude Zero Auto Correlation, constant envelope zero autocorrelation) sequence is selected as the synchronization sequence, and the zero correlation region expansion processing is performed on the synchronization sequence.

S102: Perform differential processing on the sequences obtained through the zero-correlation region expansion processing.

After the differential processing is performed on the sequence obtained by the zero-correlation area expansion process, after the receiving end enters the synchronization state, the system frequency offset value can be quickly calculated according to the peak value when entering the synchronization state, and the frequency offset compensation is performed according to the system frequency offset value.

Preferably, before step S102, the frame synchronization method at the sending end in the embodiment shown in FIG. 1 further includes: a step of obtaining the value of the differential order M in the differential processing; specifically, it may be determined according to the frequency offset of the system Estimate the value of M. When the frequency offset of the system is large, a smaller value of M can be taken. When the frequency offset of the system is small, a larger value of M can be taken. The commonly used range of M values is (2, 64); here, the M value can be selected according to the size of the system frequency offset value in experience. If an M value can make the receiving end and the sending end establish a link quickly, then the M value is considered appropriate. At the same time, notify the receiving end and the sending end of the M value. If an M value makes it difficult to establish a link between the receiving end and the sending end, the M value is considered inappropriate, and other values are tried until a suitable M value is determined, and the notification is made. Receiver and sender.

By adjusting the differential order M, the frequency offset correction flexibility of the system is improved; when the value of M is between (2,64), the range of relative frequency offset that can be corrected is between plus and minus 0.5--0.008, if the system If the working frequency is f, the adjustable absolute value of the frequency offset ranges from 0.5*f to 0.008*f.

S103: Mark the frame header of the data to be synchronized using the sequence obtained through the differential processing.

Frame synchronization technology uses the group synchronization code inserted in the signal to realize the search and marking of the frame header. The group synchronization code has two methods: centralized insertion and decentralized insertion. The corresponding insertion signals are called code group and symbol respectively. According to different requirements , both methods are used in the microwave communication system, one of them is used independently or the two are used in combination; in this embodiment, the sequence obtained by differential processing is used as the group synchronization code, and the sending end uses step S102 to obtain The sequence of the frame header is tagged.

S104: Send out the data to be sent after the frame header tag.

After marking the frame header of the data to be synchronized, the sending end can send the data to be synchronized after the frame header is marked to the receiving end.

Fig. 2 is the schematic diagram of the frame synchronization method of the receiving end provided by an embodiment of the present invention; As can be seen from Fig. 2, in this embodiment, the frame synchronization method of the receiving end provided by the present invention comprises the following steps:

S201: Receive data to be synchronized.

S202: Perform differential processing on the data to be synchronized to obtain differential data.

After the receiving end receives the data to be synchronized, it will perform down-conversion processing, analog device interference elimination processing, and digital clock recovery processing on the data. Since these processing are not the core points of the present invention, the process will not be described in detail; the differentially processed data It can be the data to be synchronized after the digital clock recovery process, or sampled data. The sampled data refers to the data obtained by sampling the best sampling point for the data to be synchronized after the digital clock recovery process. At this time, the object of step S202 is the sampling data;

In order to restore the impact of the differential processing of the synchronization sequence by the sending end, the receiving end performs differential processing on the synchronous data or sampled data, and the differential order of the differential processing should be consistent with the differential order M value of the sending end, and the receiving end obtains the M value There are various ways, and in the best embodiment of the present invention, in the header of the data to be synchronized, a field for informing the receiving end of the M value used by the sending end of the data is added; before the receiving end performs differential processing, Extract this field, obtain the M value, and perform differential processing according to the obtained M value. Specifically, it can be: perform differential calculations at intervals of M data to be synchronized, that is, perform the difference between the first and M+1 data, and the second and The M+2th data is differentiated, and so on.

S203: Perform a correlation operation on the differential data and the local sequence to obtain correlation value data.

The receiving end selects the local sequence corresponding to it according to the relevant code group sequence used by the sending end, and performs a correlation operation on the selected local sequence and the differential data; since the sending end and the receiving end in the present invention can support multiple sets of related code group sequence configurations , this application establishes the corresponding relationship between the relevant code group sequence used by the sending end and the local sequence at the receiving end, and the receiving end selects the corresponding local sequence according to the relevant code group sequence used by the data to be synchronized received by each branch, and will select The correlation operation between the local sequence and the differential data can effectively reduce the interference between multi-channel signals in the polarization mode, and improve the anti-interference ability of the system.

Specifically, the correlation operation may be a conjugate multiplication operation, etc.; when the correlation operation is a conjugate multiplication operation, step S203 may specifically be: sending the differential data output obtained in S202 into a delay register, and combining the selected local sequence with Correlation calculations are performed on the received differential data to obtain correlation value data; because the local sequence is known and the value is fixed, the entire delay register can be mainly composed of a delay circuit and an addition and subtraction circuit, with a simple structure and small processing delay.

S204: Search for a peak in the correlation value data.

The purpose of searching for the peak value in the correlation value data can be achieved in a variety of ways. Since the correlation value data obtained by the processing of step S203 is a complex number, in a preferred embodiment of the present invention, the peak search can be performed according to the modulus value of the correlation value , the specific search process will be described in detail with reference to FIGS. 3 to 5 .

S205: Determine whether the number of peaks reaches the first preset value; if yes, execute step S206; otherwise, return to step S204.

In a preferred embodiment of the present invention, the specific implementation of this step may be to set a synchronous judgment counter. When a peak value is found in S204, the value of the synchronous judgment counter is increased by "1". When the value n reaches the _first preset value N1, it means that the system enters into a synchronous state, and step S206 is executed.

S206: Execute a synchronization operation.

When the judgment result of S205 is that the value n of the synchronization judgment counter reaches the _first preset value N1, perform synchronization operations, such as frame header marking, system frequency offset value calculation, and frequency offset compensation.

Preferably, in other embodiments, the frame synchronization method at the receiving end in the embodiment shown in FIG. 2 also includes after step S204: a step of detecting whether each peak is valid; at this time, step S205 is specifically to determine whether the number of effective peaks is The first preset value is reached; specifically:

Through the implementation of step S204, a plurality of peaks can be searched, and after a peak is found, the step of detecting whether the peak is effective, this step can specifically be: determine whether the interval between the peak to be detected and its next adjacent peak is Equal to the frame length of the data to be synchronized; if so, the peak value to be detected is valid, and the peak value is recorded as a valid peak value; otherwise, the peak value to be detected is invalid, and the peak value is recorded as an invalid peak value; the specific can be:

When the first peak is found, the peak interval counting is turned on. If the next peak arrives, the interval between the two peaks is equal to the frame length of the data to be synchronized, and the peak is judged to be valid; otherwise, the peak is judged to be invalid; if the second If the interval between the peak value and the first peak value does not meet the frame length, the peak interval counting will be restarted with the second peak value as the starting point, and the subsequent peak value will be judged, and so on; when the channel condition is relatively bad, the initial The peak position may need to be shifted back several times.

After step S206, when the system is synchronizing, frequency offset compensation needs to be performed at this time, and to perform frequency offset compensation, the system frequency offset value must be calculated, so the frame synchronization method at the receiving end in the embodiment shown in Figure 2 is After step S206, it also includes: the step of obtaining the system frequency offset value and performing frequency offset compensation according to the system frequency offset value; there are many ways to obtain the system frequency offset value. The bias value is obtained according to the peak value. Specifically, it can be calculated according to any one of the N ₁ effective peak values, the average value, or the N ₁ effective peak value before the system is synchronized; for the convenience of explanation, set the difference The order of differential processing is M. When the receiving end performs digital clock recovery on the data information sent by the sending end and then samples the data, the optimal sampling point interval used is T _s , and the system frequency offset is calculated according to the N _1th effective peak value value A, then the calculation method is:

First, calculate the arc tangent according to the correlation value of the N _1th effective peak value including I/Q two channels to obtain the frequency offset angle w,

Secondly, the system frequency offset value is calculated according to the system frequency offset value A=w/(2π·M·T _s ).

After step S206, after the system performs the data synchronization operation, it is necessary to check whether the system is out of sync, so the frame synchronization method at the receiving end in the embodiment shown in Figure 2 also includes a step of detecting whether the system is out of sync after step S206; There are many ways to check whether the system is out of sync. In a preferred embodiment of the present invention, the monitoring method can be to judge whether the number of invalid peaks reaches the second preset value to detect whether the system is out of sync. The optimal , it can detect whether the system is out of sync by detecting the number of consecutive invalid peaks. When the number of consecutive invalid peaks reaches the second preset value N ₂ , it indicates that the system is out of sync and performs an out of sync operation; in order to improve the system link building The subsequent stability can be set as N ₂ >N ₁ , which not only takes into account the speed of system chain establishment, but also improves the stability of the system after chain establishment.

In order to further reduce the probability of missed peak detection and false alarms, the present invention also provides a technique for searching for peaks by multiple windowing. FIG. 3 is a schematic diagram of a peak search method provided by an embodiment of the present invention. FIG. The change curve of the correlation value modulus in an embodiment, Fig. 5 is the change curve of the correlation value modulus in another embodiment of the present invention; Now in conjunction with Fig. 3, Fig. 4 and Fig. 5 illustrate; By Fig. 3 It can be seen that the peak search method provided by the present invention comprises the following steps:

S301: Detect whether the central window value is greater than the first threshold Th ₁ ;

Referring to Fig. 4 , the correlation value modulus of the central window value is Y _k , and step S301 is to detect the size of Y _k in Fig. 4 and the first threshold Th ₁ ; if Y _k ≥ Th ₁ , then execute step S302, if Y _k < Th ₁ , then the center window value is not a peak value, and enter the judgment process of the next center window value;

S302: Detect whether the difference between the central window value and its adjacent window value is greater than the second threshold Th2;

Referring to FIG. 4 , setting step S302 is to detect whether the difference between the correlation value modulus of the central window value and the correlation value modulus of K window values on both adjacent sides is greater than the second threshold Th ₂ , K on both sides, At this time, it is necessary to compare the difference between the central window value Y _k and the correlation value modulus of 2K window values with the size of the second threshold Th ₂ , and step S302 is to detect (Y _k -Y ₁ ) in Figure 4 , (Y _k -Y ₂ ), ..., (Y _k -Y _k-1 ), (Y _k -Y _k+1 ), (Y _k -Y _k+2 ), ..., (Y _k -Y _2k ) and the size of the second threshold Th ₂ ; if (Y _k -Y ₁ ), (Y _k -Y ₂ ), ..., (Y _k -Y _k-1 ), (Y _k -Y _k+1 ) , (Y _k -Y _k+2 ), ..., (Y _k -Y _2k ) are all greater than or equal to Th ₂ , then execute step S303, if not, the central window value is not the peak value, and enter the next central window value judgment process;

S303: Taking the maximum correlation value of the central window value as the peak value;

When the system synchronization state is good, the center window value generally has only one correlation value. At this time, this correlation value can be regarded as the peak value; when the system synchronization state is poor, multiple correlation values will appear in one center window , as shown in Figure 4, at this time, compare the 2c correlation values in the center window, and select the correlation value corresponding to the largest modulus value among these correlation value moduli as the peak value, that is, to detect Y _kc in Figure 4 , Y _k-c+1 , ... , Y _k+c-1 , Y _k+c , the correlation value corresponding to the maximum modulus value is taken as the peak value, in a preferred embodiment of the present invention, c<k; it is foreseeable that multiple correlation values are compared in order to ensure that there will be no missing peak detection.

Fig. 5 is a change curve diagram of the correlation value modulus in another embodiment of the present invention, specifically, after the frame header identification is performed on the sequence after the zero-correlation area expansion processing and differential processing of the CAZAC sequence by the transmitting end in the present invention , the software simulation diagram of the correlation value modulus obtained by the receiving end after sampling, differential processing and correlation processing of the data to be synchronized; the correlation value modulus obtained by sampling it with the data after frame header marking using the existing conventional synchronization sequence The change curve diagram of the value, that is, the change curve diagram shown in Figure 4, is compared, and it can be seen intuitively that the side lobes on both sides of the correlation value of the central window value shown in Figure 5 are larger than those on both sides of the correlation value in Figure 4 The side lobes are small, and the central window value is prominent. Now in conjunction with Figure 3 and Figure 5 for further description:

It can be clearly seen from Fig. 5 that the central window value is Y _k . At this time, step S301 in Fig. 3 is to detect the size of Y _k in Fig. 5 and the first threshold Th ₁ ; only when Y _k ≥ Th ₁ , execute step S302;

It can be clearly seen from Figure 5 that the two sides of the central window are horizontal areas, and there will be no peaks in this area; the window values of the K windows on both sides of the central window are not much different, and are similar to Y _k The difference is stable, therefore, with reference to the above-mentioned embodiment, step S302 in Fig. 3 is set to detect whether the difference between the central window value and the K window values on both adjacent sides thereof is greater than the second threshold Th ₂ , at this time, step S302 is is to detect (Y _k -Y ₁ ), ..., (Y _k -Y _2k ) and the size of the second threshold Th ₂ in Figure 5; only when (Y _k -Y ₁ ), ..., (Y _k - Y _2k ) ≥ Th ₂ , execute step S303;

In Fig. 5, since the extension processing of the zero-correlation region is carried out to the synchronization sequence at the sending end, the correlation value of the central window of the correlation value modulus value detected by the receiving end is prominent; at this time, the comparison speed of step S303 among Fig. 3 is just Very fast, because at this time only less than 2c, usually 1 to 3, correlation value comparisons are required, and the peak value of the central window can be quickly determined.

FIG. 6 is a schematic diagram of a frame synchronization system provided by an embodiment of the present invention; it can be seen from FIG. 6 that in this embodiment, the frame synchronization system 6 provided by the present invention includes: a sending end 61 and a receiving end 62, wherein,

The sending end 61 is used to perform zero-correlation area extension processing on the synchronization sequence, and perform differential processing on the processed sequence, mark the frame header of the data to be synchronized using the sequence obtained by the differential processing, and send the frame header marked to be synchronized data;

The receiving end 62 is used to receive the data to be synchronized sent by the sending end 61; perform differential processing on the data to be synchronized to obtain differential data; perform correlation operations on the differential data and local sequences to obtain correlation value data; search for peak values in the correlation value data; Judging whether the number of peaks reaches a first preset value; if yes, performing a synchronization operation.

Fig. 7 is a schematic diagram of a sending end provided by an embodiment of the present invention; it can be seen from Fig. 7 that in this embodiment, the sending end 61 in the embodiment shown in Fig. 6 includes: a first processing module 611, a second processing module 612 and Sending module 613; Wherein,

The first processing module 611 is configured to perform zero-correlation region extension processing on the synchronization sequence of the data to be transmitted, and perform differential processing on the processed sequence;

The second processing module 612 is configured to use the sequence obtained by the differential processing of the first processing module 611 to mark the frame header of the data to be synchronized;

The sending module 613 is configured to send out the data to be synchronized carrying the frame header marked by the second processing module 612 , that is, send out the data to be synchronized after the frame header is marked.

In other embodiments, the sending end 61 in the embodiment shown in FIG. 7 further includes a selection module, and the selection module is used to select a synchronization sequence, and the synchronization sequence is a CAZAC series, and the synchronization sequence is passed to the first processing module 611 for processing.

In other embodiments, the sending end 61 in the embodiment shown in FIG. 7 also includes a first acquisition module, the first acquisition module is used to acquire the order value M of differential processing, and the first processing module 611 is used for synchronizing Sequences are differentially processed.

Fig. 8 is a schematic diagram of a receiving end provided by an embodiment of the present invention; it can be seen from Fig. 8 that in this embodiment, the receiving end 62 in the embodiment shown in Fig. 6 includes: a receiving module 621, a third processing module 622, a fourth Processing module 623, search module 624, judgment module 625 and synchronization module 626; wherein,

The receiving module 621 is used to receive data to be synchronized;

The third processing module 622 is configured to perform differential processing on the data to be synchronized received by the receiving module 621 to obtain differential data;

The fourth processing module 623 is configured to perform a correlation operation on the differential data obtained by the third processing module 622 and the local sequence to obtain correlation value data;

The search module 624 is used to search for a peak in the correlation value data obtained by the fourth processing module 623;

The judging module 625 is used to judge whether the number of peaks searched by the searching module 624 reaches a first preset value;

The synchronization module 626 is configured to perform a synchronization operation when the judging result of the judging module 625 is that the number of peaks reaches a first preset value.

In another preferred embodiment of the present invention, the search module 624 in the embodiment shown in Figure 7 is used to detect whether the center window value is greater than the first threshold; Whether the difference between adjacent window values is greater than the second threshold; if so, the maximum correlation value of the central window value is used as the peak value.

Fig. 9 is a schematic diagram of a receiving end provided by another embodiment of the present invention; it can be seen from Fig. 9 that in this embodiment, the receiving end 62 in the embodiment shown in Fig. 8 also includes a second acquisition module 627 and a compensation module 628; wherein ,

The second acquisition module 627 is used to acquire the system frequency offset value according to the peak value, and transmit it to the compensation module 628;

The compensation module 628 is configured to perform frequency offset compensation on the data according to the system frequency offset value acquired by the second acquisition module 627 .

In another preferred embodiment of the present invention, the receiving end in the embodiment shown in Fig. 8 also includes a detection module; the detection module is used to detect whether each peak value searched by the search module 624 is valid; the judging module 625 is also used to judge the detected Whether the number of effective peaks detected by the module reaches the first preset value; the synchronization module 626 is used to perform a synchronization operation when the judging result of the judging module 625 is that the number of effective peaks reaches the first preset value.

In another preferred embodiment of the present invention, the detection module in the above embodiment is used to judge whether the interval between the peak value to be detected and its next adjacent peak value is equal to the frame length of the data to be synchronized; if so, the peak value to be detected is valid, and the It is recorded as a valid peak; otherwise, the peak to be detected is invalid, and it is recorded as an invalid peak.

In another preferred embodiment of the present invention, the judgment module 625 in the above embodiment is also used to judge whether the number of invalid peaks detected by the detection module reaches the second preset value; When the judging result at 625 is that the number of invalid peaks reaches the second preset value, an out-of-synchronization operation is performed.

As can be seen from the above, by implementing the present invention, at least have the following beneficial effects:

1. By expanding the zero-correlation area of the synchronization sequence, the sending end reduces the side lobes at both ends of the correlation value peak, and reduces the false alarm and missed detection probability when the receiving end searches for the correlation value peak;

2. The receiving end detects the validity of the peak value and performs synchronous operation according to the number of valid peak values to avoid the influence of invalid peak values on the synchronous operation;

3. The receiving end performs differential processing on the received data, which recovers the influence caused by the differential processing on the data by the sending end, and improves the flexibility of the frequency offset correction of the system;

4. Both the sending end and the receiving end perform differential processing, so that when the data enters the synchronization stage, the calculation of the system frequency offset value and the system frequency offset compensation can be performed quickly, so that the system frequency offset value can be quickly calculated after the system is synchronized , used for frequency offset correction, which shortens the link establishment time of the system. Usually, the link establishment time can be reduced by 2 physical frames after this method is adopted;

5. Adopt strict peak interval judgment criteria to judge whether the peak value is valid, and further set the judgment threshold of synchronization and out of synchronization, taking into account the two requirements of fast link building speed and high stability of the system;

6. The sending end and the receiving end support multiple sets of related code group sequence configurations, and a set of related code group sequences corresponds to a set of local sequences, which can effectively reduce the interference between the two signals in the polarization mode and improve the system's anti-correlation Interference ability;

7. By adjusting the two parameters of the synchronization sequence length and the difference order, the requirements of frame synchronization and frequency offset correction under different wireless channels can be met, making the present invention more specific and wider application scenarios.

The above are only specific embodiments of the present invention, and do not limit the present invention in any form. Any simple modification, equivalent change or modification made to the above embodiments according to the technical essence of the present invention still belongs to the technology of the present invention. protection scope of the program.

Claims (19)

1. A frame synchronization method at a sending end, characterized in that, comprising: Perform zero-correlation region extension processing on the synchronization sequence; Differential processing is performed on the sequence obtained by the expansion processing of the zero-correlation region; Using the sequence obtained by differential processing to mark the frame header of the data to be synchronized; Send the data to be synchronized after the header tag. 2. The frame synchronization method of sending end as claimed in claim 1, it is characterized in that, before carrying out zero-correlation area expansion process to synchronization sequence, also comprise: the step of selecting synchronization sequence, described synchronization sequence is constant envelope zero self related series. 3. The frame synchronization method at the sending end according to claim 1 or 2, characterized in that, before performing differential processing on the sequence obtained by the zero-correlation region extension processing, further comprising: a step of obtaining the order value of the differential processing. 4. A frame synchronization method at a receiving end, characterized in that, comprising: receiving the data to be synchronized processed by the frame synchronization method of the sending end according to any one of claims 1-3; performing differential processing on the data to be synchronized to obtain differential data; performing a correlation operation on the differential data and the local sequence to obtain correlation value data; searching for peaks in said correlation value data; judging whether the number of peaks reaches a first preset value; If so, perform a synchronous operation. 5. The frame synchronization method of the receiving end as claimed in claim 4, wherein the step of searching for the peak value in the correlation value data is specifically: detecting whether the central window value is greater than a first threshold; if the central window If the value is greater than the first threshold, it is detected whether the difference between the central window value and its adjacent window value is greater than the second threshold; if so, the maximum correlation value of the central window value is used as the peak value. 6. The frame synchronization method of the receiving end as claimed in claim 4, characterized in that, before judging whether the number of peaks reaches the first preset value, it also includes: a step of detecting whether each peak is valid; said judging the number of peaks The step of whether the first preset value is reached is specifically: judging whether the number of effective peaks reaches the first preset value. 7. The frame synchronization method of the receiving end as claimed in claim 6, wherein the step of detecting whether each peak value is effective is specifically: judging whether the interval between the peak value to be detected and its next adjacent peak value is equal to the data to be synchronized frame length; if so, the peak to be detected is a valid peak; otherwise, the peak to be detected is an invalid peak. 8. The frame synchronization method at the receiving end according to claim 7, further comprising: after performing the synchronization operation, judging whether the number of invalid peaks reaches a second preset value, and if so, performing an out-of-synchronization operation. 9. The frame synchronization method at the receiving end according to any one of claims 4 to 8, characterized in that, after performing the synchronization operation, further comprising: obtaining a system frequency offset value according to the peak value, and according to the system frequency offset value value to perform frequency offset compensation steps. 10. A sending end, characterized in that it includes: a first processing module, a second processing module, and a sending module; wherein, The first processing module is configured to perform zero-correlation region extension processing on the synchronization sequence, and perform differential processing on the processed sequence; The second processing module is used to mark the frame header of the data to be synchronized using the sequence obtained by differential processing; The sending module is used for sending the data to be synchronized after the header mark. 11. The sending end according to claim 10, further comprising a selection module, the selection module is used to select the synchronization sequence, and the synchronization sequence is a constant envelope zero autocorrelation series. 12. The sending end according to claim 10 or 11, further comprising a first obtaining module, the first obtaining module is configured to obtain the order value of the differential processing. 13. A receiving terminal, characterized in that it includes: a receiving module, a third processing module, a fourth processing module, a search module, a judgment module and a synchronization module; wherein, The receiving module is used to receive the data to be synchronized sent via the sending end according to any one of claims 10-12; The third processing module is configured to perform differential processing on the data to be synchronized received by the receiving module to obtain differential data; The fourth processing module is used to perform a correlation operation on the differential data obtained by the third processing module and the local sequence to obtain correlation value data; The search module is used to search for a peak in the correlation value data obtained by the fourth processing module; The judgment module is used to judge whether the number of peaks searched by the search module reaches a first preset value; The synchronization module is configured to execute a synchronization operation when the determination result of the determination module is that the number of peaks reaches a first preset value. 14. The receiving terminal according to claim 13, wherein the search module is used to detect whether the center window value is greater than a first threshold; if the center window value is greater than the first threshold, then detect the center Whether the difference between the window value and its adjacent window value is greater than the second threshold; if so, the maximum correlation value of the central window value is used as the peak value. 15. The receiving terminal according to claim 13, further comprising a detection module; the detection module is used to detect whether each peak value searched by the search module is valid; the judgment module is also used to judge the Whether the number of effective peaks detected by the detection module reaches a first preset value; the synchronization module is used to perform a synchronization operation when the judgment result of the judging module is that the number of effective peaks reaches the first preset value. 16. The receiving terminal according to claim 15, wherein the detection module is used to judge whether the interval between the peak value to be detected and its next adjacent peak value is equal to the frame length of the data to be synchronized; if so, the The peak to be detected is a valid peak; otherwise, the peak to be detected is an invalid peak. 17. The receiving terminal according to claim 16, wherein the judging module is further used to judge whether the number of invalid peaks detected by the detecting module reaches a second preset value; the synchronizing module also uses When the judging result of the judging module is that the number of invalid peaks reaches a second preset value, an out-of-synchronization operation is performed. 18. The receiving end according to any one of claims 13 to 17, further comprising a second acquisition module and a compensation module; the second acquisition module is used to acquire the system frequency offset value according to the peak value, so The compensation module is used to perform frequency offset compensation according to the system frequency offset value. 19. A frame synchronization system, comprising the transmitting end according to any one of claims 10 to 12, and the receiving end according to any one of claims 13 to 18.