CN104022147B - Semiconductor device with function of restraining transient voltage - Google Patents
Semiconductor device with function of restraining transient voltage Download PDFInfo
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- 230000001052 transient effect Effects 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000000452 restraining effect Effects 0.000 title 1
- 230000001629 suppression Effects 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 230000005684 electric field Effects 0.000 abstract description 4
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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- H10D8/422—PN diodes having the PN junctions in mesas
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
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Abstract
本发明公开了一种瞬态电压抑制半导体器件，包括上台体、与上台体底面面接触的中台体和与中台体底面面接触的下台体，上台体和与下台体各自的外侧面均为斜面，此上台体包括第一轻掺杂N型区、第一重掺杂N型区，所述中台体从上至下依次为第一轻掺杂P型区、重掺杂P型区和第二轻掺杂P型区，此下台体包括第二轻掺杂N型区、第二重掺杂N型区；第一PN结接触面的中央区域具有中心上凸面，所述第一PN结接触面的边缘区域具有边缘下凹面，此边缘下凹面位于中心上凸面两侧。本发明降低漏电流中来自表面的漏电流，大大降低整个器件的反向漏电流，且提高了器件耐高温性能，降低了在边缘处电场强度梯度，从而提高了器件耐压性能。
The invention discloses a transient voltage suppressing semiconductor device, which comprises an upper platform body, a middle platform body in contact with the bottom surface of the upper platform body, and a lower platform body in contact with the bottom surface of the middle platform body, and the respective outer surfaces of the upper platform body and the lower platform body are uniform The upper mesa includes a first lightly doped N-type region and a first heavily doped N-type region, and the middle mesa consists of a first lightly doped P-type region and a heavily doped P-type Region and the second lightly doped P-type region, the lower platform body includes the second lightly doped N-type region and the second heavily doped N-type region; the central region of the first PN junction contact surface has a central upper convex surface, and the first The edge region of a PN junction contact surface has an edge concave surface, and the edge concave surface is located on both sides of the central upper convex surface. The invention reduces the leakage current from the surface in the leakage current, greatly reduces the reverse leakage current of the whole device, improves the high temperature resistance performance of the device, reduces the electric field intensity gradient at the edge, and thus improves the device voltage resistance performance.
Description
技术领域technical field
本发明涉及一种半导体器件，具体涉及一种瞬态电压抑制半导体器件。The invention relates to a semiconductor device, in particular to a transient voltage suppression semiconductor device.
背景技术Background technique
瞬态电压抑制半导体器件TVS可确保电路及电子元器件免受静电、浪涌脉冲损伤，甚至失效。一般TVS并联于被保护电路两端，处于待机状态。当电路两端受到瞬态脉冲或浪涌电流冲击，并且脉冲幅度超过TVS的击穿电压时，TVS能以极快的速度把两端的阻抗由高阻抗变为低阻抗实现导通，并吸收瞬态脉冲。在此状态下，其两端的电压基本不随电流值变化，从而把它两端的电压箝位在一个预定的数值，该值约为击穿电压的1.3～1.6倍，以而保护后面的电路元件不受瞬态脉冲的影响。Transient voltage suppression semiconductor device TVS can ensure that circuits and electronic components are protected from static electricity, surge pulse damage, or even failure. Generally, the TVS is connected in parallel at both ends of the protected circuit and is in a standby state. When both ends of the circuit are impacted by transient pulse or surge current, and the pulse amplitude exceeds the breakdown voltage of TVS, TVS can quickly change the impedance of both ends from high impedance to low impedance to achieve conduction, and absorb the transient state pulse. In this state, the voltage at both ends of it basically does not change with the current value, so that the voltage at both ends of it is clamped at a predetermined value, which is about 1.3 to 1.6 times the breakdown voltage, so as to protect the following circuit components. affected by transient pulses.
发明内容Contents of the invention
针对上述存在的技术问题，本发明的目的是：提出了一种瞬态电压抑制半导体器件，该瞬态电压抑制半导体器件降低漏电流中来自表面的漏电流，大大降低整个器件的反向漏电流，且提高了器件耐高温性能，降低了在边缘处电场强度梯度，从而提高了器件耐压性能。In view of the above-mentioned technical problems, the object of the present invention is to provide a transient voltage suppression semiconductor device, which reduces the leakage current from the surface in the leakage current and greatly reduces the reverse leakage current of the entire device. , and improves the high temperature resistance performance of the device, reduces the electric field intensity gradient at the edge, thereby improving the device withstand voltage performance.
本发明的技术解决方案是这样实现的：一种瞬态电压抑制半导体器件，包括上台体、与上台体底面面接触的中台体和与中台体底面面接触的下台体，所述上台体和与下台体各自的外侧面均为斜面，此上台体包括第一轻掺杂N型区、第一重掺杂N型区，所述中台体从上至下依次为第一轻掺杂P型区、重掺杂P型区和第二轻掺杂P型区，此下台体包括第二轻掺杂N型区、第二重掺杂N型区；所述第一重掺杂N型区、第一轻掺杂N型区接触并位于其正上方，所述第二重掺杂N型区、第二轻掺杂N型区接触并位于其正下方；The technical solution of the present invention is achieved as follows: a transient voltage suppression semiconductor device, comprising an upper platform, a middle platform in contact with the bottom surface of the upper platform, and a lower platform in contact with the bottom surface of the middle platform, the upper platform The outer surfaces of the upper and lower mesa bodies are inclined, and the upper mesa body includes a first lightly doped N-type region and a first heavily doped N-type region, and the middle mesa body is the first lightly doped N-type region from top to bottom. A P-type region, a heavily doped P-type region, and a second lightly doped P-type region, the lower platform includes a second lightly doped N-type region, a second heavily doped N-type region; the first heavily doped N-type region type region, the first lightly doped N-type region is in contact with and located directly above it, and the second heavily doped N-type region and the second lightly doped N-type region are in contact with and located directly below;
所述中台体中第一轻掺杂P型区与上台体的第一轻掺杂N型区接触形成第一PN结接触面，所述中台体中第二轻掺杂P型区与下台体的第二轻掺杂N型区接触形成第二PN结接触面；The first lightly doped P-type region in the mesa body is in contact with the first lightly doped N-type region of the upper mesa body to form a first PN junction contact surface, and the second lightly doped P-type region in the mesa body is in contact with the first lightly doped N-type region of the upper mesa body. The second lightly doped N-type region of the lower mesa is contacted to form a second PN junction contact surface;
一第一钝化保护层覆盖于第一重掺杂N型区上表面的边缘区域和第一重掺杂N型区的侧表面，一第二钝化保护层覆盖于第二重掺杂N型区下表面的边缘区域和第二重掺杂N型区的侧表面，上金属层覆盖于第一重掺杂N型区的中央区域，下金属层覆盖于第二重掺杂N型区的中央区域；A first passivation protection layer covers the edge region of the upper surface of the first heavily doped N-type region and the side surface of the first heavily doped N-type region, and a second passivation protection layer covers the second heavily doped N-type region. The edge region of the lower surface of the N-type region and the side surface of the second heavily doped N-type region, the upper metal layer covers the central region of the first heavily doped N-type region, and the lower metal layer covers the second heavily doped N-type region the central area of
所述第一轻掺杂N型区与第一重掺杂N型区接触的上部区域且位于第一轻掺杂N型区边缘的四周区域具有第一中掺杂N型区，此第一中掺杂N型区的上表面与第一重掺杂N型区的下表面接触，此第一中掺杂N型区的外侧面延伸至上台体外侧面，所述第一轻掺杂P型区与重掺杂P型区接触的下部区域且位于第一轻掺杂P型区边缘的四周区域具有第一中掺杂P型区，此第一中掺杂P型区的下表面与重掺杂P型区的上表面接触，此第一中掺杂P型区的外侧面延伸至中台体外侧面；The upper region of the first lightly doped N-type region in contact with the first heavily doped N-type region and the surrounding region located at the edge of the first lightly doped N-type region has a first moderately doped N-type region, the first The upper surface of the moderately doped N-type region is in contact with the lower surface of the first heavily doped N-type region, the outer side of the first moderately doped N-type region extends to the outer side of the upper platform, and the first lightly doped P-type The lower region in contact with the heavily doped P-type region and the surrounding region located at the edge of the first lightly doped P-type region has a first moderately doped P-type region, and the lower surface of the first moderately doped P-type region is in contact with the heavy The upper surface of the doped P-type region is in contact, and the outer side of the first doped P-type region extends to the outer side of the middle stage;
所述第二轻掺杂N型区与第二重掺杂N型区接触的下部区域且位于第二轻掺杂N型区边缘的四周区域具有第二中掺杂N型区，此第二中掺杂N型区的下表面与第二重掺杂N型区的上表面接触，此第二中掺杂N型区的外侧面延伸至下台体外侧面，所述第二轻掺杂P型区与重掺杂P型区接触的上部区域且位于第二轻掺杂P型区边缘的四周区域具有第二中掺杂P型区，此第二中掺杂P型区的上表面与重掺杂P型区的下表面接触，此第二中掺杂P型区的外侧面延伸至中台体外侧面；The lower region of the second lightly doped N-type region in contact with the second heavily doped N-type region and the surrounding region located at the edge of the second lightly doped N-type region has a second moderately doped N-type region, the second The lower surface of the moderately doped N-type region is in contact with the upper surface of the second heavily doped N-type region, the outer side of the second moderately doped N-type region extends to the outer side of the lower platform, and the second lightly doped P-type The upper region in contact with the heavily doped P-type region and the surrounding region located at the edge of the second lightly doped P-type region has a second medium-doped P-type region, and the upper surface of the second medium-doped P-type region is in contact with the heavily doped P-type region The lower surface of the doped P-type region is in contact, and the outer side of the second doped P-type region extends to the outer side of the middle stage;
所述第一PN结接触面的中央区域具有中心上凸面，所述第一PN结接触面的边缘区域具有边缘下凹面，此边缘下凹面位于中心上凸面两侧；所述第二PN结接触面的中央区域具有中心下凹面，所述第二PN结接触面的边缘区域具有边缘上凸面，此边缘上凸面位于中心下凹面两侧。The central region of the first PN junction contact surface has a central convex surface, and the edge region of the first PN junction contact surface has an edge concave surface, and the edge concave surface is located on both sides of the central convex surface; the second PN junction contact The central area of the surface has a central concave surface, and the edge area of the second PN junction contact surface has an edge upper convex surface, and the edge upper convex surface is located on both sides of the central lower concave surface.
上述技术方案中的有关内容解释如下：The relevant content in the above-mentioned technical scheme is explained as follows:
上述方案中，所述上台体的外侧面和与中台体中第一轻掺杂P型区的外侧面的夹角为135°~155°，所述下台体的外侧面和与中台体中第二轻掺杂P型区的外侧面的夹角为135°~155°。In the above scheme, the angle between the outer surface of the upper platform body and the outer surface of the first lightly doped P-type region in the middle platform body is 135°~155°, and the outer surface of the lower platform body and the middle platform body The included angle between the outer surfaces of the second lightly doped P-type region is 135°-155°.
由于上述技术方案运用，本发明与现有技术相比具有下列优点和效果：Due to the use of the above-mentioned technical solutions, the present invention has the following advantages and effects compared with the prior art:
1. 本发明瞬态电压抑制半导体器件，其包括上台体和与上台体底面面接触的下台体，此上台体包括轻掺杂N型区、重掺杂N型区，此下台体包括重掺杂P型区、轻掺杂P型区，轻掺杂N型区与重掺杂N型区接触的上部区域且位于第一轻掺杂N型区边缘的四周区域具有中掺杂N型区，此中掺杂N型区的上表面与重掺杂N型区的下表面接触，此中掺杂N型区的外侧面延伸至上台体外侧面，轻掺杂P型区与重掺杂P型区接触的下部区域且位于轻掺杂P型区边缘的四周区域具有中掺杂P型区，此中掺杂P型区的下表面与重掺杂P型区的上表面接触，此中掺杂P型区的外侧面延伸至下台体外侧面，在低压（10V以下）TVS在隧道击穿模式下，降低漏电流中来自表面的漏电流，大大降低整个器件的反向漏电流，从而进一步降低了功耗，避免了器件的局部温升，提高了电路稳定性和可靠性。1. The transient voltage suppression semiconductor device of the present invention comprises an upper platform body and a lower platform body in contact with the bottom surface of the upper platform body, the upper platform body includes a lightly doped N-type region and a heavily doped N-type region, and the lower platform body includes a heavily doped N-type region The heterogeneous P-type region, the lightly doped P-type region, the upper region where the lightly doped N-type region contacts the heavily doped N-type region and the surrounding region located at the edge of the first lightly doped N-type region has a moderately doped N-type region , where the upper surface of the doped N-type region is in contact with the lower surface of the heavily doped N-type region, wherein the outer side of the doped N-type region extends to the outer side of the upper platform, and the lightly doped P-type region and the heavily doped P The lower region in contact with the lightly doped P-type region and the surrounding region at the edge of the lightly doped P-type region has a moderately doped P-type region, wherein the lower surface of the doped P-type region is in contact with the upper surface of the heavily doped P-type region, wherein The outer side of the doped P-type region extends to the outer side of the lower platform. Under low voltage (below 10V) TVS tunnel breakdown mode, the leakage current from the surface in the leakage current is reduced, and the reverse leakage current of the entire device is greatly reduced, thereby further The power consumption is reduced, the local temperature rise of the device is avoided, and the circuit stability and reliability are improved.
2. 本发明瞬态电压抑制半导体器件，其上台体和与上台体底面面接触的下台体，上台体和与上台体各自的外侧面均为斜面，上台体的外侧面和与下台体的外侧面的夹角为135°~155°，提高了器件耐高温性能，降低了在边缘处电场强度梯度，从而提高了器件耐压性能。2. The transient voltage suppression semiconductor device of the present invention, its upper platform body and the lower platform body contacting with the upper platform body bottom surface, the upper platform body and the respective outer sides with the upper platform body are inclined planes, the outer side surface of the upper platform body and the outer surface of the lower platform body The included angle of the side is 135°~155°, which improves the high temperature resistance performance of the device, reduces the electric field intensity gradient at the edge, and thus improves the withstand voltage performance of the device.
3. 本发明瞬态电压抑制半导体器件，其轻掺杂N型区与重掺杂N型区接触的上部区域且位于第一轻掺杂N型区边缘的四周区域具有中掺杂N型区，轻掺杂P型区与重掺杂P型区接触的下部区域且位于轻掺杂P型区边缘的四周区域具有中掺杂P型区，PN结接触面的中央区域具有上凸面，PN结接触面的边缘区域具有下凹面，此下凹面位于上凸面两侧，提高了有效载流面积，将电场峰值向中心移动提高了电流密度的同时也降低整个器件的反向漏电流，保证了在高温下，能仰制反向电流快速升高。3. The transient voltage suppression semiconductor device of the present invention, the upper region where the lightly doped N-type region contacts the heavily doped N-type region and the surrounding region located at the edge of the first lightly doped N-type region has a moderately doped N-type region , the lower region where the lightly doped P-type region is in contact with the heavily doped P-type region and the surrounding region located at the edge of the lightly doped P-type region has a moderately doped P-type region, and the central region of the PN junction contact surface has an upper convex surface, PN The edge area of the junction contact surface has a lower concave surface, which is located on both sides of the upper convex surface, which increases the effective current-carrying area, moves the peak value of the electric field to the center, increases the current density, and reduces the reverse leakage current of the entire device, ensuring At high temperature, the reverse current can be restrained from rising rapidly.
附图说明Description of drawings
下面结合附图对本发明技术方案作进一步说明：Below in conjunction with accompanying drawing, technical solution of the present invention will be further described:
附图1为本发明瞬态电压抑制半导体器件结构示意图；Accompanying drawing 1 is the structural representation of transient voltage suppression semiconductor device of the present invention;
以上附图中：1、上台体；2、中台体；3、第一轻掺杂N型区；4、第一重掺杂N型区；5、第二轻掺杂N型区；6、第二重掺杂N型区；7、第一钝化保护层；8、第二钝化保护层；9、上金属层；10、下金属层；11、第一中掺杂N型区；12、第一中掺杂P型区；13、下台体；14、第一轻掺杂P型区；15、重掺杂P型区；16、第二轻掺杂P型区；17、第二中掺杂N型区；18、第二中掺杂P型区；19、中心上凸面；20、边缘下凹面；21、中心下凹面；22、边缘上凸面。In the above drawings: 1. Upper platform body; 2. Middle platform body; 3. First lightly doped N-type region; 4. First heavily doped N-type region; 5. Second lightly doped N-type region; 6. , the second heavily doped N-type region; 7, the first passivation protection layer; 8, the second passivation protection layer; 9, the upper metal layer; 10, the lower metal layer; 11, the first medium-doped N-type region ; 12, the first moderately doped P-type region; 13, the lower platform; 14, the first lightly doped P-type region; 15, the heavily doped P-type region; 16, the second lightly doped P-type region; 17, The second moderately doped N-type region; 18. The second moderately doped P-type region; 19. The upper convex surface at the center; 20. The lower concave surface at the edge; 21. The lower concave surface at the center; 22. The upper convex surface at the edge.
具体实施方式detailed description
下面结合附图来说明本发明。The present invention is described below in conjunction with accompanying drawing.
如附图1所示的一种瞬态电压抑制半导体器件，包括上台体1、与上台体1底面面接触的中台体2和与中台体2底面面接触的下台体13，所述上台体1和与下台体13各自的外侧面均为斜面，此上台体1包括第一轻掺杂N型区3、第一重掺杂N型区4，所述中台体2从上至下依次为第一轻掺杂P型区14、重掺杂P型区15和第二轻掺杂P型区16，此下台体2包括第二轻掺杂N型区5、第二重掺杂N型区6；所述第一重掺杂N型区4、第一轻掺杂N型区3接触并位于其正上方，所述第二重掺杂N型区6、第二轻掺杂N型区5接触并位于其正下方；A kind of transient voltage suppressing semiconductor device as shown in accompanying drawing 1, comprises upper platform body 1, the middle platform body 2 that contacts with upper platform body 1 bottom surface surface and the lower platform body 13 that contacts with middle platform body 2 bottom surface surfaces, described upper platform The outer surfaces of the body 1 and the lower platform body 13 are sloped, the upper platform body 1 includes a first lightly doped N-type region 3 and a first heavily doped N-type region 4, and the middle platform body 2 is from top to bottom The first lightly doped P-type region 14, the heavily doped P-type region 15, and the second lightly doped P-type region 16 are in sequence. The lower platform 2 includes the second lightly doped N-type region 5, the second heavily doped N-type region 6; the first heavily doped N-type region 4 and the first lightly doped N-type region 3 contact and are located directly above it, the second heavily doped N-type region 6, the second lightly doped N-type region The N-type region 5 is in contact with and directly below it;
所述中台体2中第一轻掺杂P型区14与上台体1的第一轻掺杂N型区3接触形成第一PN结接触面，所述中台体2中第二轻掺杂P型区16与下台体13的第二轻掺杂N型区5接触形成第二PN结接触面；The first lightly doped P-type region 14 in the middle platform body 2 is in contact with the first lightly doped N-type region 3 of the upper platform body 1 to form a first PN junction contact surface, and the second lightly doped N-type region 14 in the middle platform body 2 The heterogeneous P-type region 16 is in contact with the second lightly doped N-type region 5 of the lower platform body 13 to form a second PN junction contact surface;
一第一钝化保护层7覆盖于第一重掺杂N型区4上表面的边缘区域和第一重掺杂N型区4的侧表面，一第二钝化保护层8覆盖于第二重掺杂N型区6下表面的边缘区域和第二重掺杂N型区6的侧表面，上金属层9覆盖于第一重掺杂N型区4的中央区域，下金属层10覆盖于第二重掺杂N型区6的中央区域；A first passivation protection layer 7 covers the edge region of the upper surface of the first heavily doped N-type region 4 and the side surfaces of the first heavily doped N-type region 4, and a second passivation protection layer 8 covers the second The edge region of the lower surface of the heavily doped N-type region 6 and the side surface of the second heavily doped N-type region 6, the upper metal layer 9 covers the central region of the first heavily doped N-type region 4, and the lower metal layer 10 covers In the central region of the second heavily doped N-type region 6;
所述第一轻掺杂N型区3与第一重掺杂N型区4接触的上部区域且位于第一轻掺杂N型区3边缘的四周区域具有第一中掺杂N型区11，此第一中掺杂N型区11的上表面与第一重掺杂N型区4的下表面接触，此第一中掺杂N型区11的外侧面延伸至上台体1外侧面，所述第一轻掺杂P型区14与重掺杂P型区15接触的下部区域且位于第一轻掺杂P型区14边缘的四周区域具有第一中掺杂P型区12，此第一中掺杂P型区12的下表面与重掺杂P型区15的上表面接触，此第一中掺杂P型区12的外侧面延伸至中台体2外侧面；The upper region of the first lightly doped N-type region 3 in contact with the first heavily doped N-type region 4 and the surrounding region located at the edge of the first lightly doped N-type region 3 has a first moderately doped N-type region 11 , the upper surface of the first moderately doped N-type region 11 is in contact with the lower surface of the first heavily doped N-type region 4, and the outer side of the first moderately doped N-type region 11 extends to the outer side of the upper platform body 1, The lower region of the first lightly doped P-type region 14 in contact with the heavily doped P-type region 15 and the surrounding region located at the edge of the first lightly doped P-type region 14 has a first moderately doped P-type region 12, which The lower surface of the first moderately doped P-type region 12 is in contact with the upper surface of the heavily doped P-type region 15, and the outer side of the first moderately doped P-type region 12 extends to the outer side of the mesa 2;
所述第二轻掺杂N型区5与第二重掺杂N型区6接触的下部区域且位于第二轻掺杂N型区5边缘的四周区域具有第二中掺杂N型区17，此第二中掺杂N型区17的下表面与第二重掺杂N型区6的上表面接触，此第二中掺杂N型区17的外侧面延伸至下台体13外侧面，所述第二轻掺杂P型区16与重掺杂P型区15接触的上部区域且位于第二轻掺杂P型区16边缘的四周区域具有第二中掺杂P型区18，此第二中掺杂P型区18的上表面与重掺杂P型区15的下表面接触，此第二中掺杂P型区18的外侧面延伸至中台体2外侧面；The lower region of the second lightly doped N-type region 5 in contact with the second heavily doped N-type region 6 and the surrounding region located at the edge of the second lightly doped N-type region 5 has a second moderately doped N-type region 17 , the lower surface of the second moderately doped N-type region 17 is in contact with the upper surface of the second heavily doped N-type region 6, and the outer side of the second middle-doped N-type region 17 extends to the outer side of the lower platform body 13, The upper region of the second lightly doped P-type region 16 in contact with the heavily doped P-type region 15 and the surrounding region located at the edge of the second lightly doped P-type region 16 has a second moderately doped P-type region 18. The upper surface of the second moderately doped P-type region 18 is in contact with the lower surface of the heavily doped P-type region 15, and the outer side of the second moderately doped P-type region 18 extends to the outer side of the mesa 2;
所述第一PN结接触面的中央区域具有中心上凸面19，所述第一PN结接触面的边缘区域具有边缘下凹面20，此边缘下凹面20位于中心上凸面19两侧；所述第二PN结接触面的中央区域具有中心下凹面21，所述第二PN结接触面的边缘区域具有边缘上凸面22，此边缘上凸面22位于中心下凹面21两侧。The central region of the first PN junction contact surface has a central upper convex surface 19, and the edge region of the first PN junction contact surface has an edge lower concave surface 20, and this edge lower concave surface 20 is located on both sides of the central upper convex surface 19; The central region of the two PN junction contact surfaces has a central concave surface 21 , and the edge region of the second PN junction contact surface has an edge upper convex surface 22 , and the edge upper convex surface 22 is located on both sides of the central lower concave surface 21 .
上述上台体1的外侧面和与中台体2中第一轻掺杂P型区14的外侧面的夹角为135°~155°，所述下台体13的外侧面和与中台体2中第二轻掺杂P型区16的外侧面的夹角为135°~155°。The angle between the outer surface of the upper platform 1 and the outer surface of the first lightly doped P-type region 14 in the middle platform 2 is 135°~155°, and the outer surface of the lower platform 13 and the outer surface of the middle platform 2 The included angle between the outer surface of the second lightly doped P-type region 16 is 135°-155°.
采用上述瞬态电压抑制半导体器件时，其在低压（10V以下）TVS在隧道击穿模式下，降低漏电流中来自表面的漏电流，大大降低整个器件的反向漏电流，从而进一步降低了功耗，避免了器件的局部温升，提高了电路稳定性和可靠性；再次，其上台体和与上台体底面面接触的下台体，上台体和与上台体各自的外侧面均为斜面，上台体的外侧面和与下台体的外侧面的夹角为135°~155°，提高了器件耐高温性能，保证了在高温下，能仰制反向电流快速升高。When the above-mentioned transient voltage suppression semiconductor device is used, under the low voltage (below 10V) TVS in the tunnel breakdown mode, the leakage current from the surface in the leakage current is reduced, and the reverse leakage current of the entire device is greatly reduced, thereby further reducing the power consumption. consumption, avoiding the local temperature rise of the device, and improving the stability and reliability of the circuit; again, the upper platform body and the lower platform body in contact with the bottom surface of the upper platform body, the upper platform body and the outer sides of the upper platform body are sloped, and the upper platform body The angle between the outer surface of the body and the outer surface of the lower platform is 135°~155°, which improves the high temperature resistance of the device and ensures that the reverse current can be controlled to rise rapidly at high temperature.
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并加以实施，并不能以此限制本发明的保护范围，凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围内。The above-mentioned embodiments are only to illustrate the technical conception and characteristics of the present invention, and its purpose is to allow those familiar with this technology to understand the content of the present invention and implement it, and cannot limit the protection scope of the present invention with this. Substantial equivalent changes or modifications shall fall within the protection scope of the present invention.
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