CN104022043A - Groove type power MOSFET with split gates and manufacturing method - Google Patents

Abstract

The present invention relates to a semiconductor device for power management, more precisely, the present invention aims to provide a method for introducing a split gate into a power MOSFET with a trench structure and a corresponding preparation method. The shielding gate in the lower part of the active trench or the termination trench is electrically connected to the source metal layer on the upper surface of the silicon wafer, so that the shield gate and the source are in the same potential, while the active trench or the termination trench The upper control grid in the groove is insulated from the shielding grid.

Description

Trench power MOSFET with split gate and manufacturing method thereof

technical field

The present invention relates to a semiconductor device for power management, more precisely, the present invention aims to provide a method for introducing a split gate into a power MOSFET with a trench structure and a corresponding preparation method.

Background technique

For semiconductor devices commonly used in power electronic systems and power management, the power Metal-Oxide-Semiconductor-Field-Effect-Transistor MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), or Insulated Gate Field-Effect Transistor, is widely introduced .

Trench power MOSFET is a new high-efficiency and power switching device developed after MOSFET. It adopts trench gate structure field effect transistor, which not only inherits the high input impedance of MOS field effect transistor (≥10 ⁸ Ω), It has the advantages of small driving current (about 0.1μA), and also has excellent characteristics such as high withstand voltage, large operating current, high output power, good transconductance, and fast switching speed. It is precisely because it combines the advantages of electron tubes and power transistors that it is widely used in switching power supplies, inverters, voltage amplifiers, power amplifiers and other circuits. Therefore, high breakdown voltage, high current, and low on-resistance are the most critical indicators of power MOSFETs. However, for power MOSFETs, it is almost impossible to obtain high breakdown voltage and low on-resistance at the same time, so as to achieve the purpose of lower power consumption when working with high current. It is necessary to improve the breakdown voltage and on-resistance Compromise with each other.

In order to optimize the device structure as much as possible to achieve higher breakdown voltage and low on-resistance, trench type double-layer gate power field effect transistor (Split Gate MOSFET) came into being. It mainly improves the breakdown voltage by integrating the field plate effect of a shielding gate short-circuited with the source in the lower part of the trench. Therefore, under the same breakdown voltage requirement, the on-resistance of the power MOSFET can be reduced by increasing the doping concentration of the silicon epitaxial layer, thereby reducing the power consumption during high-current operation. However, this layer of shielded gate structure greatly increases the difficulty of process implementation and increases the processing cost of the device.

The present invention aims to reduce the photomask level as much as possible, simplify the processing technology, and realize the power MOSFET device of the trench type double-layer gate structure, which not only reduces the processing difficulty, thereby reducing the processing cost, but also can realize high breakdown voltage and low conduction resistance and increased yield. Finally, the market competitiveness of the device is enhanced.

In order to realize the short-circuit between the shielded gate and the source in the existing trench type double-layer gate power MOSFET, either the shielded gate is directly connected to the top of the trench, or a deep hole is opened on the shielded gate. The former solution needs to increase the level of the mask, and requires a very expensive process to realize, such as adding the oxide layer between the shielded grid mask and the thickened double-layer gate of another layer of mask, and then increasing the gap between the double-layer gates. breakdown voltage and reduce the parasitic capacitance between the double-layer gates. Moreover, this solution requires the use of very expensive processes such as high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition) and chemical mechanical polishing (CMP-Chemical Mechanical Polish), which increases the difficulty of device processing and reduces The accuracy of process control is impaired, which is not conducive to achieving high yield. The latter option also requires deep holes to be dug where the shield gate is shorted to the source, achieved by chemical vapor deposition of metal. In this way, on the one hand, it is necessary to add a layer of photomask behind the shielding gate to retain the thick oxide layer above the shielding gate shorted to the source, and it also requires expensive processes such as HDP and CMP. Moreover, opening deep holes on the shield gate requires an expensive chemical vapor deposition method to realize metallization, which increases the difficulty of the process and increases the risk of device reliability.

In this solution, by changing the process sequence and finding another way, it not only reduces the number of photomask layers, but also does not require expensive processes, and realizes a trench-type double-layer gate structure power MOSFET.

Contents of the invention

In one embodiment, a method for fabricating a trench power device with a split gate includes the following steps: step A, etching a ring-shaped termination trench on top of an epitaxial layer on a bottom substrate and a plurality of active trenches, wherein the termination trenches may not be ring-shaped but only arranged side by side with the active trenches, and the termination trenches need to be set to be ring-shaped only when a field plate is added on the substrate; Step B, generating a first insulating layer, covering the respective sidewalls and bottoms of the termination trench and the active trench, and simultaneously covering the top surface of the epitaxial layer; Step C, covering the termination trench, the active trench The lower parts of the grooves are filled with conductive materials as shielding grids; step D, etching removes the first insulating layer at the sidewalls of the upper parts of the termination grooves, the active trenches and the top surface of the epitaxial layer, and forms the shielding grids on each of the shielding grids Prepare an isolation layer above; step E, generate a second insulating layer, covering the upper exposed sidewalls of the termination trench and the active trench, and simultaneously covering the top surface of the epitaxial layer; step F, in the termination The upper part of the trench and the active trench is filled with a conductive material as a control gate. Step G, etching the control gate and the isolation layer in the termination trench, defining one or more via holes that expose the shielding gate; step H, forming A top dielectric layer fused with the second insulating layer on the top surface of the epitaxial layer, covering the top surface of the epitaxial layer and each control gate, synchronously forming a side dielectric layer attached to the sidewall of the through hole; step 1, Filling conductive material into the through hole; step J, forming an insulating passivation layer covering the top dielectric layer and the through hole; step K, etching the insulating passivation layer to form at least the first set of contact holes therein, and then filling the metal The plug is plugged into the first set of contact holes and a top metal layer is deposited on the top dielectric layer, and the metal plug in the first set of contact holes is set to electrically connect the conductive material in the through hole with the top metal layer.

The above method, in step C, includes the following steps: depositing a conductive material for the first time, covering the top of the first insulating layer on the top surface of the epitaxial layer, and filling in the termination trench and the active trench; Conductive material is engraved, and the conductive material at the lower part of the termination groove and the active groove is reserved as a shielding grid.

The above method, in step D, includes the following steps: depositing an insulator, covering the first insulating layer on the top surface of the epitaxial layer, and filling the respective upper parts of the termination trench and the active trench; returning Etching to remove the insulator, and etching back to remove the first insulating layer covering the termination trenches, the upper sidewalls of the active trenches, and the top surface of the epitaxial layer, leaving a via above each shield gate The isolation layer left by the insulator etched back.

The above method, in step F, includes the following steps: depositing a conductive material for the second time, covering the upper part of the second insulating layer on the top surface of the epitaxial layer, and filling the upper part of the termination trench and the active trench; The conductive material is etched back, and the conductive material on the top of the termination trench and the active trench is reserved as a control gate.

The above method, in step G, includes the following steps: forming a photoresist layer on the top of the second insulating layer on the top surface of the epitaxial layer and on the tops of each control gate; The opening of the part of the control gate region in the termination trench is exposed, and the control gate and the isolation layer in the termination trench are etched downward to form one or more through holes exposing the shielding gate.

The above method, in step H, includes the following steps: preparing an insulating dielectric layer of the same material as the second insulating layer above the second insulating layer on the top surface of the epitaxial layer, this part of the insulating dielectric layer and the top surface of the epitaxial layer The original second insulating layer is fused to form a top dielectric layer, which covers the top surface of the epitaxial layer and the control gates; another part of the insulating dielectric layer formed simultaneously is also attached to the exposed sidewall of the via hole to A side dielectric layer is formed.

The above method, after step H, includes the following steps: directly using the top dielectric layer as an etching mask, and dry etching to remove the synchronous covering under the via hole in the step of generating the top dielectric layer and the side dielectric layer The insulating dielectric layer at the exposed area of the shielding grid.

The above method, in step I, includes the following steps: depositing a conductive material for the third time, covering the top dielectric layer on the top surface of the epitaxial layer and filling it in the through hole; etching back the conductive material, retaining the conductive material in the through hole conductive material.

The above method, after any one of steps F, G, H, and I, but before step J, further includes the following steps: implanting dopants at least on top of the epitaxial layer inside the termination trench to form a bulk layer , surrounding the upper portion of each active trench; and implanting dopants on top of the body layer to form a source layer near the top surface of the epitaxial layer.

The above method, when etching the insulating passivation layer in step K, further includes sequentially etching the insulating passivation layer, the top dielectric layer, the source layer and the body layer downwards to form an active trench that extends into the body layer and is located in the adjacent active trench. The second set of contact holes between the trenches or between the active trenches and the termination trenches; and then also filling the second set of contact holes with metal plugs, the formed top metal layer The metal plugs form electrical contacts.

In the above method, in the step K of etching the insulating passivation, a first set of contact holes penetrating the insulating passivation layer and aligned with the conductive material in the through hole is formed, so that the metal filled in the first set of contact holes The plug is electrically connected to the conductive material in the through hole.

The above-mentioned method, in step I, includes the following steps: when etching back the conductive material deposited for the third time, still retain a part of the conductive material overlapping the termination trench as a field plate, wherein the field plate is formed This part of the conductive material extends outside the horizontal direction termination trench until it extends near the peripheral edge of the epitaxial layer.

In the above method, in the step K of etching the insulating passivation, a first set of contact holes penetrating the insulating passivation layer and aligned with the field plate are formed, so that the metal plugs filled in the first set of contact holes pass through the field plate And electrically connected to the conductive material in the via hole below the field plate.

In a device structure of an alternative embodiment, a trench power device with a split gate includes: a base substrate and an epitaxial layer located on the base substrate; an epitaxial layer formed in the epitaxial layer such as Ring-shaped termination grooves and multiple active grooves, wherein the termination grooves may not be ring-shaped but only arranged side by side with the active grooves, and only need to be set when field plates are added on the substrate The termination trench is ring-shaped; the shielding grids filled in the lower parts of the active trenches and the termination trenches and the control grids filled in their respective upper parts respectively, and a Isolation layer insulation; at least one body layer formed on the top of the epitaxial layer inside the termination trench and surrounding the upper portion of each active trench, and a source layer formed on the top of the body layer; penetrating the termination in turn The control gate in the trench, one or more sidewalls of the isolation layer are attached with a side dielectric layer through hole, and the conductive material filled in the through hole; it is located on the top surface of the epitaxial layer and covers each control gate a top dielectric layer and an insulating passivation layer located on the top dielectric layer; extending downward through the insulating passivation layer, the top dielectric layer and the source layer and extending into the body layer and located between adjacent active trenches A second set of contact holes occasionally located between the active trench and the termination trench, and a first set of contact holes penetrating down through the insulating passivation layer and aligned with the conductive material in the through hole; filling in the first set , the metal plugs in the second set of contact holes and the top metal layer disposed on the insulating passivation layer; the interconnected shielding grids are thus composed of the conductive material in the through holes and the metal plugs in the first set of contact holes The conductive path is electrically connected to the top metal layer.

In another alternative embodiment, a trench power device with a split gate includes: a base substrate and an epitaxial layer overlying the base substrate; The connection groove and multiple active grooves, wherein the termination groove may not be ring-shaped but only arranged side by side with the active groove, and the termination groove needs to be set only when a field plate is added on the substrate It is ring-shaped; the shielding grids filled in the lower parts of the active trenches and the termination trenches and the control grids filled in their respective upper parts are respectively filled, and an isolation layer is provided between each shielding grid and a control grid above it; At least a body layer formed on the top of the epitaxial layer inside the termination trench and surrounding the upper part of each active trench, and a source layer formed on the top of the body layer; penetrating downwards in turn through the control in the termination trench One or more sidewalls of the gate, isolation layer, a via hole with a side dielectric layer attached, and a conductive material filled in the via hole; a top dielectric located on the top surface of the epitaxial layer and covering the control gates layer; the field plate located on the top dielectric layer and overlapped on the termination trench, and the field plate extends outward in the horizontal direction to the outside of the termination trench; the field plate disposed on the top dielectric layer At the same time, it also covers the insulating passivation layer of the field plate; it extends downward through the insulating passivation layer, the top dielectric layer and the source layer in sequence, and extends into the body layer and is located between adjacent active trenches or in the active trenches The second set of contact holes between the groove and the termination trench, and the first set of contact holes penetrating down through the insulating passivation layer and aligned with the field plate; the metal filling the first set and the second set of contact holes The plug and the top metal layer disposed on the insulating passivation layer; the interconnected shield grids are thereby electrically connected to the conductive path of the conductive material in the through hole and the metal plug in the first set of contact holes. the top metal layer.

In other preparation methods of trench power devices with split gates, the termination trenches are canceled, including the following steps: Step A, etching a plurality of parallel-arranged epitaxial layers on the top of the bottom substrate Trench; step B, generating a first insulating layer, covering the side walls and bottom of each trench, and covering the top surface of the epitaxial layer; step C, filling the lower part of the trench with conductive material as a shielding gate; step D 1. Etching and removing the first insulating layer on the upper sidewall of the trench and the top surface of the epitaxial layer, and preparing an isolation layer above each shielding gate; step E, generating a second insulating layer to cover the exposed upper part of the trench On the sidewall, covering the top surface of the epitaxial layer at the same time; step F, filling the conductive material on the upper part of the trench as a control gate; step G, etching the control gate and isolation layer in part of the trench, defining one or more Exposing the through hole of the shielding gate; step H, forming a top dielectric layer fused with the second insulating layer on the top surface of the epitaxial layer, covering the top surface of the epitaxial layer and each control gate, synchronously forming a side dielectric layer The layer is attached to the sidewall of the through hole; step I, filling the conductive material into the through hole; step J, forming an insulating passivation layer to cover the top dielectric layer and the through hole; step K, etching the insulating passivation layer at least Forming the first set of contact holes therein, then filling the first set of contact holes with metal plugs and depositing a top metal layer on the top dielectric layer, setting the metal plugs in the first set of contact holes to electrically connect the through holes Conductive material and top metal layer. The trenches mentioned here may be active trenches.

The above method, in step C, includes the following steps: depositing a conductive material for the first time, covering the top of the first insulating layer on the top surface of the epitaxial layer, and filling it in the trench; etching back the conductive material, retaining the trench The lower conductive material acts as a shielding grid.

The above method, in step D, includes the following steps: depositing an insulator to cover the first insulating layer on the top surface of the epitaxial layer, and filling the upper part of the trench; etching back to remove the insulator, and returning The first insulating layer covering the upper sidewall of the trench and the top surface of the epitaxial layer is removed by etching, and an isolation layer above each shielding gate is left by etching back the insulating material.

The above method, in step F, includes the following steps: depositing a conductive material for the second time, covering the top of the second insulating layer on the top surface of the epitaxial layer, and filling the upper part of the trench; etching back the conductive material, retaining the trench The conductive material on the top of the slot acts as a control grid.

The above method, in step G, includes the steps of: forming a photoresist layer over the second insulating layer on the top surface of the epitaxial layer and on the tops of each control gate; Part of the opening of the control gate region in the preset trench is etched downward to form one or more through holes exposing the shielding gate.

The above method, in step H, includes the following steps: preparing an insulating dielectric layer of the same material as the second insulating layer above the second insulating layer on the top surface of the epitaxial layer, this part of the insulating dielectric layer and the top surface of the epitaxial layer The original second insulating layer is fused to form a top dielectric layer, which covers the top surface of the epitaxial layer and the control gates; another part of the insulating dielectric layer formed simultaneously is also attached to the exposed sidewall of the via hole to A side dielectric layer is formed.

The above method, after step H, includes the following steps: directly using the top dielectric layer as an etching mask, and dry etching to remove the synchronous covering under the via hole in the step of generating the top dielectric layer and the side dielectric layer The insulating dielectric layer at the exposed area of the shielding grid.

The above method, in step I, includes the following steps: depositing a conductive material for the third time, covering the top dielectric layer on the top surface of the epitaxial layer and filling it in the through hole; etching back the conductive material, retaining the conductive material in the through hole conductive material.

The above-mentioned method, after any one of steps F, G, H, and I, but before step J, includes the following steps: among all the plurality of grooves, the outermost two grooves are used as boundaries to limit their inner sides The top of the epitaxial layer needs to be implanted with dopants, that is, at least the top of the epitaxial layer inside the outermost trench is implanted with dopant to form a body layer, which surrounds the upper part of each trench; and in the body layer The top implantation of dopants forms a source layer near the top surface of the epitaxial layer.

In the above method, when etching the insulating passivation layer in step K, it also includes sequentially etching the insulating passivation layer, the top dielectric layer, the source layer and the body layer downwards to form a layer extending into the body layer and located between adjacent trenches. and subsequently filling the second set of contact holes with metal plugs, the formed top metal layer forms electrical contact with the metal plugs in the second set of contact holes.

In the above method, in the step K of etching the insulating passivation, a first set of contact holes penetrating the insulating passivation layer and aligned with the conductive material in the through hole is formed, so that the metal filled in the first set of contact holes The plug is electrically connected to the conductive material in the through hole.

In other alternative embodiments, a trench power device with a split gate, eliminating the termination trench, includes: a base substrate and an epitaxial layer over the base substrate; formed on the epitaxial layer A plurality of trenches in the trench; the shielding gate filled in the lower part of the trench and the control gate filled in the upper part of the trench, and an isolation layer is provided between each shielding gate and a control gate above it; in multiple side-by-side Among the trenches, a body layer is formed on the top of the inner epitaxial layer of the two outermost trenches (boundary), the body layer surrounds the upper part of each trench, and a source layer is formed on the top of the body layer Of course, the body layer can also be formed on the top of the outer epitaxial layer of the two outermost trenches (boundary), and the top of the outer body layer can also be doped to form a source layer; The control gate in the trench, one or more sidewalls of the isolation layer are attached with a side dielectric layer through hole, and the conductive material filled in the through hole; it is located on the top surface of the epitaxial layer and covers each control gate A top dielectric layer and an insulating passivation layer located on the top dielectric layer; down through the insulating passivation layer, the top dielectric layer and the source layer and extending into the body layer and located between adjacent trenches The second set of contact holes, and the first set of contact holes that penetrate the insulating passivation layer and align with the conductive material in the through hole; the metal plugs filled in the first set and the second set of contact holes and arranged in the insulating passivation layer The top metal layer above the top metal layer; the interconnected shield grids are thereby electrically connected to the top metal layer by the conductive path of the conductive material in the via hole and the metal plug in the first set of contact holes. The trenches mentioned here may be active trenches.

Description of drawings

Embodiments of the present invention are more fully described with reference to the accompanying drawings. However, the accompanying drawings are for illustration and illustration only, and do not limit the scope of the present invention.

1A-1Q are schematic flow charts of the method of the present invention.

FIG. 2 is a schematic diagram of a method for filling the upper part of the active trench and the termination trench with polysilicon deposited for the second time and then preparing the body layer and the source layer.

FIG. 3 is a schematic diagram of a method for preparing a body layer and a source layer after etching through holes in the polysilicon filled above the active trench and the termination trench.

FIG. 4 is a schematic diagram of a method for forming a top dielectric layer on the top surface of the epitaxial layer and attaching a side dielectric layer to the side wall of the through hole before preparing a body layer and a source layer.

FIGS. 5A-5C are based on the flow of FIGS. 1A-1Q but additionally the field plate is applied in the device.

FIG. 6 is a schematic partial top view of the chip.

FIG. 7 is a schematic partial top view of the chip after the field plate is fabricated.

Detailed ways

In FIG. 1A, a substrate includes a heavily doped N+-type bottom substrate 101a, and also includes a lightly doped N-type bottom substrate with a lower doping concentration than the bottom substrate 101a above the bottom substrate 101a. For the epitaxial layer 101b, the base substrate 101a and the epitaxial layer 101b can be set to be of the first conductivity type. An illustrated hard mask layer 200, such as a silicon dioxide layer, is deposited and formed on the top surface of the epitaxial layer 101b, and a predetermined groove pattern is transferred to a not shown in the figure using known photolithography techniques. In the photoresist layer, the photoresist layer is covered on the hard mask layer 200, and then the photoresist layer is used as an etching mask, and the hard mask layer 200 is etched by plasma etching or wet etching. opening pattern, and then use the hard mask layer 200 with the opening pattern as an etching mask, so as to further etch a plurality of active trenches 102a and a plurality of active trenches 102a and An annular termination groove 102b. A plurality of active trenches 102a arranged side by side are disposed on the active region of the substrate inside the termination trench 102b. In another alternative embodiment of preparing grooves, the photoresist can also be directly spin-coated on the top surface of the epitaxial layer 101b to replace the hard mask layer 200, and then the photoresist with the groove pattern The layer is directly used as an etching mask, and the epitaxial layer 101b region exposed to the opening pattern in the photoresist layer is etched by plasma dry etching to prepare the active trench 102a and the termination trench 102b, and finally photolithography The adhesive layer needs to be stripped off as well as the hard mask layer 200 .

In FIG. 1B, a sacrificial oxide layer not shown in the figure is grown by thermal oxidation on the respective sidewalls and bottoms of the active trench 102a and the termination trench 102b, and then the sacrificial oxide layer is stripped off by wet etching. layer, the sacrificial oxide layer is only a transition product, used to repair the damage of the inner wall of the trench and form a smooth inner wall, and fillet the bottom corner of the trench. Then grow a thinner layer such as a thermal silicon oxide layer by thermal oxidation, as the first insulating layer 103 with a partial thickness, and then grow a thicker layer such as an oxide layer by a low-pressure chemical vapor deposition (LPCVD) method, As another partial thickness of the first insulating layer 103, LPCVD is used to further increase the thickness of the first insulating layer 103. The first insulating layer 103 can be understood as a composite layer comprising a thin silicon oxide layer and a thick CVD oxide layer. . Thereafter, a high-temperature annealing is performed to improve the density of the oxide layer, so that the total thickness of the first insulating layer 103 finally reaches the designed thickness value. In addition, in some other alternative embodiments, the preparation method of the first insulating layer 103 is simply through the thermal oxidation step, or simply through the LPCVD method, so as to achieve a certain thickness of the required dense, such as oxidation. layer as the first insulating layer 103. The first insulating layer 103 covers the entire sidewalls and bottoms of the active trench 102a and the termination trench 102b, and also covers the top surface of the epitaxial layer 101b.

In FIG. 1C, for example, by LPCVD deposition method, the conductive material 104 shown in the figure is formed, and polysilicon, such as in-situ doping, is grown with a certain expected thickness value. According to the spirit of the present invention, this is the first time that the conductive material 104 is deposited. . As shown in the figure, the conductive material 104 covers the first insulating layer 103 on the top surface of the epitaxial layer 101b, and the conductive material 104 also fills the inner space of the active trench 102a and the termination trench 102b.

In FIG. 1D, the conductive material 104 is etched back by plasma dry etching. Here, no additional mask is used, and the conductive material 104 is directly etched to the required depth, so that the conductive material 104 is as deep as possible. The surface formed by etching is relatively smooth. Therefore, by etching back, the part of the conductive material 104 above the first insulating layer 103 on the top surface of the epitaxial layer 101b is removed, and at the same time, the part of the conductive material 104 on the upper part of the active trench 102a and the termination trench 102b is removed. are also removed, thus leaving interstitial spaces above the respective upper portions of the active trench 102a and the termination trench 102b. As shown in FIG. 1D , only the conductive material 104 at the bottom of the active trench 102 a and the termination trench 102 b is reserved as a shield gate (Shield gate) 104 a.

In FIG. 1E, an insulator 105 is grown and deposited by LPCVD, for example, a silicon oxide layer is prepared, and a densified LPCVD insulator 105 is realized through a relatively high temperature annealing process. The insulator 105 fills the active trenches 102a and The respective upper parts of the trenches 102b are terminated, and the gap space formed above the trenches is completely filled with the insulator 105, and the insulator 105 often covers the top of the first insulating layer 103 on the top surface of the epitaxial layer 101b. In essence, the insulator 105 is an analogue of the same material as the first insulating layer 103. When the insulator 105 is formed, the interface between it and the first insulating layer 103 will almost fuse together during the high-temperature treatment stage. This makes the contact interface between the two less obvious. In the step of performing etch-back etching on the insulator 105 in FIG. 1F , the epitaxial layer 101b is peeled off by a wet method such as using HF or BOE (representing a mixture of HF and NH ₄ F solution) in a time-controlled manner. All the oxide layer on the surface and the upper sidewall of each trench, but the oxide layer on the upper surface of the polysilicon shielding gate 104a is retained to increase the breakdown voltage between the shielding gate 104a and the subsequent control gate 107a. Specifically, predetermined etching is required to remove unnecessary parts of the insulator 105: for example, a part of the insulator 105 above the first insulating layer 103 on the top surface of the epitaxial layer 101b, and the insulator 105 is filled in the active trench 102a and a substantial portion of the upper portion of each of the termination grooves 102b. In this etch-back step, simultaneous etching is required to remove the first insulating layer 103 covering the respective upper sidewalls of the active trench 102a and the termination trench 102b, and etch to remove the top surface of the epitaxial layer 101b. The first insulating layer 103 on it. It is worth emphasizing that although most of the insulator 105 in each trench has been etched away, it is still necessary to retain a spacer above the top surface of each shield gate 104a left by the insulator 105 etch back. Layer 105a. Note that at this stage, the lower parts of the active trenches 102a and the termination trenches 102b are filled with shielding gates 104a, and the sidewalls and bottoms of the lower parts of the trenches are still attached with the first insulating layer 103. At the same time, the active trenches 102a A hollow interstitial space is formed at the upper part of the termination trench 102b, and the top surface of the epitaxial layer 101b is also exposed.

In FIG. 1G, a second insulating layer 106 is formed, typically a silicon dioxide layer regrown by thermal oxidation, and the second insulating layer 106 covers the active trench 102a and the termination trench 102b. On the exposed side walls of the upper parts, the second insulating layer 106 also covers the entire exposed top surface or upper surface of the epitaxial layer 101b, in fact, on the side walls of the upper parts of the active trench 102a and the termination trench 102b The attached second insulating layer 106 will be the actual gate oxide layer of the unit cell of the vertical trench MOSFET device, which will be introduced further in the following.

In FIG. 1H , according to the spirit of the present invention, the conductive material 107 is deposited for the second time, such as by LPCVD method, to grow a polysilicon layer. Ion implantation or thermal diffusion methods achieve polysilicon doping. The conductive material 107 is covered on the top of the second insulating layer 106 on the top surface of the epitaxial layer 101b, and the conductive material 107 is also filled in the respective upper parts of the active trench 102a and the termination trench 102b. In FIG. The interstitial spaces originally formed in the respective upper portions of the trenches 102 a and the termination trenches 102 b are filled again with the conductive material 107 of polysilicon. Subsequently, as shown in FIG. 1I, the conductive material 107 is etched by the plasma dry etching method, and the conductive material 107 is etched back to a certain extent, so that the top surface of the conductive material 107 retained in the trench is in the same position as the second The position where the upper surface of the insulating layer 106 is substantially flush, that is, the position is etched back to the position close to the top surface of the epitaxial layer 101b, as shown in FIG. 1I . After the conductive material 107 is etched back, the conductive material 107 on the respective upper parts of the active trench 102a and the termination trench 102b is finally reserved as a control gate (Control gate) 107a.

In FIG. 1J, a photoresist layer 208 needs to be used as an etching mask, and the spin-coated photoresist layer 208 covers the entire second insulating layer 106 above the top surface of the epitaxial layer 101b. The photoresist Layer 208 also overlies the top of each control gate 107a. Then, using conventional photolithography technology, several openings 208a in the photoresist 208 are formed after exposure and development, and the openings 208a are overlapped on the control grid 107a in the termination trench 102b. The width of the opening 208a in the width direction of the termination trench 102b does not exceed the width of the termination trench 102b itself (it can also be said that it does not exceed the width of the control gate 107a in this direction). Now use the photoresist layer 208 with the opening 208a as an etching shielding layer to define the through hole 107b. For the convenience of observation and understanding, the steps of FIG. 1K-1 to FIG. 1K-3 can be combined, wherein FIG. 1K-1 The photoresist 208 is not shown in FIG. 1K-2 . In addition, FIG. 1K-2 to FIG. 1K-3 are vertical cross-sectional views along the dotted line AA in FIG. 1K-1 .

The specific step of etching to define the through hole 107b is: to etch the exposed control gate 107a area under the opening 208a by dry plasma etching, for example, in FIG. 1K-1 and FIG. 1K-2, at the end A via hole 107b is formed by etching in the control gate 107a connected to the trench 102b. Then do not peel off the photoresist layer 208, still use it as an etching mask, and continue to etch downward (here, dry or wet etching can be used), until the exposed isolation layer 105a region at the bottom of the via hole 107b is also is etched away, as shown in FIG. 1K-3 , but the etching stops at the exposed top surface of the shield gate 104a. Therefore, the via hole 107b formed in the filled control gate 107a above the termination trench 102b penetrates down through the control gate 107a and the isolation layer 105a sequentially, exposing the region of the partial shielding gate 104a below the via hole from the via hole 107b. In this etching step, a dry etching process with a high selectivity ratio between polysilicon and oxide layer should be selected as far as possible, so as to realize the etching of the through hole 107b without damaging the oxide layer such as the second insulating layer on the side wall of the through hole 107b. 106. In a preferred embodiment, the width of the through hole 107b in the width direction of the termination trench 102b is approximately equal to or slightly smaller than the width of the control gate 107a, that is, the original width W _T of the termination trench 102b is subtracted twice The thickness T _O of the second insulating layer 106 is approximately equal to W _T −2T _O , and the thickness of the insulating layer 106 attached to the two opposite sidewalls on the upper part of the termination trench 102b needs to be considered. In this way, through the patterned opening 208a in the photoresist layer 208 for exposing a part of the control gate 107a area in the termination trench 102b, the control gate 107a and the control gate 107a in the termination trench 102b are etched downward. The isolation layer 105a forms one or more through holes 107b exposing a partial area of the shielding grid 104a. Referring additionally to FIG. 1K-1 , along the length of the termination trench 102b, a plurality of spaced through holes 107b may be provided. As shown in FIG. 1K-3 , after the etching of the through hole 107b and the removal of the isolation layer 105a at the bottom of the through hole 107b are completed, the photoresist layer 208 is removed by etching.

In FIG. 1L-1, a top dielectric layer 108 needs to be prepared on the top surface of the epitaxial layer 101b. For example, a thicker oxide layer is grown directly by low-pressure chemical vapor deposition (LPCVD) method, as an insulating dielectric layer (not separately marked), which has the upper part of the original second insulating layer 106 covering the top surface of the epitaxial layer 101b. This part of the insulating dielectric layer also covers the exposed top surface of each control gate 107a. It can be considered that the top dielectric layer 108 is actually a total composite layer, which contains the original second layer on the top surface of the epitaxial layer 101b. The insulating layer 106, and a part of the insulating dielectric layer prepared above the original second insulating layer 106 on the top surface of the epitaxial layer 101b is fused. Finally, the obtained top dielectric layer 108 covers the top surface of the epitaxial layer 101b and also covers the top surfaces of each control gate 107a. It is worth emphasizing that the second insulating layer 106 and the prepared insulating dielectric layer can be substantially made of the same silicon dioxide material, and they can also be selected to use high-temperature annealing to improve the compactness of the entire oxide layer. In addition, it must be clarified that in the step of generating a thick oxide layer by LPCVD deposition, the obtained insulating dielectric layer (oxide) is not selectively deposited or grown. The actual situation is that the generated insulating dielectric layer not only covers the Above the original second insulating layer 106 on the top surface of the epitaxial layer 101b, similarly, the prepared insulating dielectric layer also has a part attached to the sidewall of the through hole 107b, and this part of the insulating dielectric layer is defined as a side dielectric Layer 108a, as shown in Figure 1L-1 and Figure 1L-2. In other words, an insulating dielectric layer of the same material as the second insulating layer 106 is prepared, which has at least a part above the second insulating layer 106 covering the top surface of the epitaxial layer 101b, and this part of the insulating dielectric layer together with the top surface of the epitaxial layer 101b The original second insulating layer 106 above the surface is fused together to form the top dielectric layer 108; at the same time, another part of the insulating dielectric layer generated synchronously is also attached to the exposed sidewall of the via hole 107b to form the side dielectric layer 108a, Figure 1L-2 shows the results of this step.

Another aspect that needs to be considered is that, in view of the fact that the obtained insulating dielectric layer (oxide) is not selectively deposited or grown, while simultaneously preparing the top dielectric layer 108 and the side dielectric layer 108a, there is still a part of the insulating dielectric layer Naturally, it will be deposited on the bottom of the through hole 107b, at the area where the shielding grid 104a is exposed from the through hole 107b, actually covering the exposed area on the top surface of the shielding grid 104a directly below the through hole 107b. According to the spirit of the present invention, it is necessary to directly use the top dielectric layer 108 as an etching mask without using an additional mask. After anisotropic dry etching step, the top surface of the shielding grid 104a is located directly under the through hole 107b The part of the insulating dielectric layer covered by the region will be removed by etching, and this region is the region exposed from the through hole 107b.

In FIG. 1M, the step of depositing a conductive material 109 is performed. The conductive material 109 is prepared by, for example, growing in-situ doped polysilicon by LPCVD method, or depositing polysilicon without dedoping first, and then preparing doped polysilicon by ion implantation or diffusion method. Miscellaneous polysilicon. Depositing the conductive material 109 is the third polysilicon deposition step. Finally, the conductive material 109 covers the top dielectric layer 108 on the top surface of the epitaxial layer 101b, and the conductive material 109 is also filled in each through hole 107b. Then, as shown in FIG. 1N-1 , a step of etching back the conductive material 109 is performed. Etch back the conductive material 109, such as by plasma dry etching, so that the conductive material 109 in the via hole 107b is etched back to a position substantially flush with the top surface of the top dielectric layer 108, but the top surface of the epitaxial layer 101b The conductive material 109 above the top dielectric layer 108 above the surface will be removed. As shown in FIG. 1N-2 , only the portion of the conductive material 109a inside the through hole 107b remains.

In order to understand the relative positional relationship between the through hole 107b and other nearby components in more detail, FIG. 1N-3 deliberately intercepts the cross-sectional view of the vertical section along the dotted line BB in FIG. 1N-2. FIG. 1N-3 is a fragment of the termination trench 102b, showing approximately one-half of the width of the termination trench 102b, wherein the first insulating layer 103 is attached on the sidewall and bottom of the lower portion of the termination trench 102b. , and the lower part of the termination trench 102b is filled with a shielding grid 104a, the isolation layer 105a is disposed on the top surface of the shielding grid 104a, and the upper sidewall of the termination trench 102b is covered with a second insulating layer 106, The first insulating layer 103 is generally much thicker than the second insulating layer 106 . In addition, the upper part of the termination trench 102b is filled with a control gate 107a, and each shielding gate 104a and a control gate 107a directly above it are isolated from each other by an isolation layer 105a between them. The top dielectric layer 108 covers the top surface of the control gate 107a. According to the structure shown in the figure, the through hole 107b passes through the control gate 107a and the isolation layer 105a downwards in sequence, and the side wall of the through hole 107b is covered with the side dielectric layer 108a, so the conductive material 109a filled in the through hole 107b depends on the side The dielectric layer 108a is insulated from the area surrounded by the control grid 107a around the through hole 107b, but the conductive material 109a filled in the through hole 107b is connected to the shield grid 104a and has an electrical contact relationship. In addition, the through hole 107b is filled with The conductive material 109a is also exposed from the top dielectric layer 108 .

In FIG. 1O, an implantation mask can be used as a shielding layer for ion implantation, so that dopants are implanted on the top of the epitaxial layer 101b inside the termination trench 102b to form a bulk layer 110, where the implanted dopants Impurities or ions are of P type, which is the second conductivity type opposite to the aforementioned first conductivity type. The formed body layer 110 surrounds the upper part of each active trench 102a. Note that the body layer 110 and the epitaxial layer 101b below it The interface between them is set above the bottom surface of the control gate 107a so that a vertical inversion layer can be formed in the body layer 110 along the sidewalls of the active trench 102a or the termination trench 102b to establish the channel of the MOSFET cell. And then continue to implant N+ type dopants on the top of the body layer 110 to form a source layer 111 near the top surface of the epitaxial layer 101b, the source layer 111 also surrounds the upper part of each active trench 102a, but Its depth is much shallower than that of the bulk layer 110 . After the implantation of the body layer 110 and the source layer 111 is completed, the implantation mask not shown in the figure can be stripped off. In the embodiment of FIG. 1O, the implanted body layer 110 and the source layer 111 are located in the active region inside the termination trench 102b, and no body layer 110 is formed in the termination region outside the termination trench 102b. , the source layer 111 . However, in some other embodiments not shown in the figures, an implantation mask can be saved, and no ion implantation mask is used, and an integral blanket implant is directly used, not only in the inner side of the termination trench 102b A body layer 110 is formed on top of the epitaxial layer 101b and a source layer 111 is formed on top of the body layer 110 at the location, a body layer 110 is also formed on top of the epitaxial layer 101b outside the termination trench 102b, and The source layer 111 is formed on top of the body layer 110 outside the termination trench 102b, in other words, both the active region and the termination region are integrally implanted into the body layer and the source layer.

In FIG. 1P , an insulating passivation layer 112 is firstly deposited to cover the top surface of the top dielectric layer 108 , such as using low temperature oxide LTO and/or silicon glass BPSG containing boric acid. The insulating passivation layer 112 also covers the conductive material 109a filled in each through hole 107b. After preparing the insulating passivation layer 112, an additional photoresist layer is spin-coated on the insulating passivation layer 190, and photolithographically developed to form some opening patterns therein, using this photoresist layer as a contact hole etching mask, After proper anisotropic dry etching, several first set of contact holes 112b and second set of contact holes 112a penetrating through the insulating passivation layer 112 are formed simultaneously. When etching the insulating passivation layer 112 in FIG. 1P to prepare the second set of contact holes 112a, it is mainly to prepare the contact holes extending down to the mesa structure of the active region, including sequentially etching the insulating passivation layer downwards. 112. The top dielectric layer 108, the source layer 111 in the active region, and the body layer 110 in the active region form a second set of contact holes 112a extending downward into the body layer 110, and each of the second set of contact holes 112a A contact hole is either disposed between two adjacent active trenches 102a, or disposed between the outermost active trench 102a and its adjacent termination trench 102b (the outermost active trench 102a is The active trench closest to the termination trench 102b among all the active trenches 102a). When etching the insulating passivation layer 112 in FIG. 1P to prepare the first set of contact holes 112b, a corresponding contact hole is mainly prepared on a through hole 107b, and each contact hole in the first set of contact holes 112 overlaps. over a via 107b and the conductive material inside it. In this way, in the first set of contact holes 102b, for each contact hole formed through the insulating passivation layer 112 downwards, it is correspondingly aligned and contacts a through hole 107b directly below it. Filled with conductive material 109a.

In some embodiments not shown in the figures, the insulating passivation layer 112 with the second set of contact holes 112a is used as a self-aligned implant mask, and each contact hole of the second set of contact holes 112a can also be injected The bottom is implanted with P+ type heavily doped ions to form a body contact region located in the body layer 110 and located near the bottom of each contact hole in the second set of contact holes 112a, the doping concentration of which is higher than that of the body layer 110. impurity concentration is higher.

In some embodiments, the first set of contact holes 112b and the second set of contact holes 112a are first filled with a metal material (such as tungsten), and the metal material in the contact holes forms a metal plug or a metal joint. , this metal plug adopts a separate deposition process followed by an etching process to remove unnecessary unnecessary metal material above the insulating passivation layer 112 and only retain the metal material in each contact hole. In addition, in this embodiment, a top metal layer 113 needs to be separately deposited to cover the entire insulating passivation layer 112, and the top metal layer 113 is connected to each contact hole in the first set of contact holes 112b and the second set of contact holes 112a. The metal plugs form electrical connections/contacts. Since each contact hole in the first set of contact holes 102b is correspondingly aligned with the conductive material 109a filled in a through hole 107b below it, the conductive material 109a filled in each specific through hole 107b is naturally aligned with the through hole 107b. A metal plug in a contact hole directly above (belonging to the first set of contact holes) forms an electrical contact.

In some other optional embodiments, the metal material (metal plug) filled in each contact hole in the first set of contact holes 112b and the second set of contact holes 112a is the same as the metal material (top metal plug) above the insulating passivation layer 112. Layer 113) is generated by simultaneous deposition, that is to say, the metal plugs in each contact hole and the top metal layer 113 are actually integrally formed. At this time, their materials are completely the same, and the top metal layer 113 and the first set of contact holes 112b 1. The metal plugs in each contact hole in the second set of contact holes 112a naturally form an electrical connection/contact.

For a trench-type power MOSFET device, the top metal layer 113 is embodied as a source electrode, and an unillustrated bottom metal layer disposed on the bottom surface of the bottom substrate 101a is embodied as a drain electrode, and each active trench The control gates 107a in the trenches 102a are all connected to an undrawn gate to pick up the conductive material in the trenches, and another contact hole not shown in the figure that penetrates the insulating passivation layer 112 and the top dielectric layer 108 is provided. Aligning and contacting the conductive material in the gate pick-up trench, the metal plug in the contact hole electrically connects the conductive material in the gate pick-up trench to another gate electrode located above the insulating passivation layer 112 on the gate metal layer.

In the embodiments shown in FIGS. 2 to 4, the steps are based on the steps in FIGS. 1A to 1Q. The only modification is to adjust the timing of the implantation of the body layer 110 or the source layer 111. Other steps are the same as those shown in FIG. 1A. ~1Q is exactly the same without any difference. For example, in the steps of FIGS. 1A˜1Q , the body layer 110 or the source layer 111 is implanted after the conductive material 109 a in the through hole 107 b is formed in FIG. 10 . However, in the embodiment of FIG. 2, after the control gate 107a on the upper part of the active trench 102a and the termination trench 102b are prepared in FIG. P-type body layer 110 or N-type source layer 111, which replaces the original ion implantation step in FIG. 1O. In the embodiment of FIG. 3, immediately after the step of peeling off the photoresist layer 208 in FIG. Pole layer 111, which replaces the ion implantation step in the original step of FIG. 1O. In the embodiment of FIG. 4, after the steps of preparing the top dielectric layer 108 and the side dielectric layer 108a of FIG. or N-type source layer 111, which replaces the ion implantation step in the original step of FIG. 1O. In the embodiment of FIG. The upper part of the insulating dielectric layer will be additionally covered, so the implantation timing of the dopant forming the body layer 110 or the source layer 111 in FIG. Before a part of the insulating dielectric layer covered on the top, it may also be after cleaning the part of the insulating dielectric layer. Similarly, a part of the insulating dielectric layer referred to here is formed simultaneously with the top dielectric layer 108 and the side dielectric layer 108a, only However, this part of the insulating dielectric layer is deposited on the bottom of the via hole 107b.

In the embodiment of FIGS. 5A-5C, it is based on the steps of FIGS. 1A-1Q, and the only modification is in the step of etching the conductive material 109 deposited for the third time (ie, FIG. 1M to FIG. 1N-1), not only Only the expected conductive material 109a is left in the through hole 107b, and a field plate composed of a part of the remaining conductive material 109b is also left at the same time, and the other steps are completely consistent with those in FIGS. 1A-1Q without any difference. . As shown in FIGS. 5A-5B , an additional photoresist layer (not shown) is used as an etching mask to cover the conductive material 109, and then the conductive material 109 on the top dielectric layer 108 is etched, and the conductive material 109 The portion overlapping the epitaxial layer 101a inside the termination trench 109a is completely removed by etching, but the portion of the conductive material 109 overlapping the epitaxial layer 101a outside the termination trench 109a is retained. Next, the conductive material 109 corresponding to the vicinity of the peripheral edge of the epitaxial layer 101a remains, and the retained conductive material 109b also has a portion overlapping the termination trench 102b. Due to the shielding effect of the conductive material 109b, the conductive material 109a filled in the through hole 107b is located directly below the conductive material 109b, blocked by the conductive material 109b, and will not be etched away, so it remains. In this way, the conductive material 109a filled in the through hole 107b and the conductive material 109b are substantially electrically connected to each other, and they are also integrally formed structurally. The portion of the conductive material 109b serving as the field plate extends from directly above the termination trench 102a to the outside of the termination trench 102a in the horizontal direction until it reaches near the peripheral edge of the epitaxial layer 101b. Compared with the steps in Figs. 1P-1Q, since there is a part of additional conductive material 109b on the top dielectric layer 108 and the termination trench 102b, the insulating passivation layer 112 prepared later will also cover the conductive material 109b. cover, then when preparing the first set of contact holes 112b in FIG. Each of the contact holes is aligned and in contact with the field plate, so that the subsequent metal plugs filled in the first set of contact holes 112b can be electrically connected to the conductive material 109a in the through hole 107b below the field plate through the field plate .

6 to 7 show a partial schematic diagram of a substrate or chip. The substrate has an active region 170 inside the termination trench 102b, and a termination region 160 outside the termination trench 102b. Several elongated active trenches 102a are arranged inside the trench 102b. In addition to the part parallel to the active trench 102a, the termination trench 102b has a part perpendicular to the active trench 102a. Connected with the end of the active trench 102a, a plurality of spaced through holes 107b are prepared by etching in the control gate 107a on the upper part of the termination trench 102b, and the termination trench 102b, the active trench The shielding grids 104a at the respective lower parts of 102a are interconnected, whereby the conductive path is plugged by the conductive material 109a in the through hole 107b and the metal plug in the first set of contact holes 112b, so that the electrical connection of the shielding grid 104a to the on the top metal layer 113, making them equipotential. In FIG. 7, the conductive material 109b (i.e., the field plate) is located on the top dielectric layer 108 and has a portion that overlaps the termination trench 102b. The field plate is also ring-shaped from the termination trench 102b. It expands outward along the horizontal direction, and extends outward to the outside of the termination groove 102b, for example, it may extend to the terminal area outside the termination groove 102b. In addition, the outer edge of the field plate 109b itself may also be configured. close to the peripheral edge 150 of the chip or substrate or epitaxial layer 101b, and the opposite inner edge of the field plate 109b is located near the inner sidewall of the termination trench 102b near the active region (or toward the center of the chip), the Field plates can be used to alleviate electric field crowding in the termination region.

In some optional but non-essential embodiments, the termination groove 102b may not be a closed ring shape, but is arranged side by side with the active groove 102a and located on both sides of the active groove 102a. In some optional embodiments, only when an additional field plate 109b is added on the substrate, it is necessary to additionally set the closed annular termination trench 102b, for example, when the field plate 109b on the epitaxial layer is no longer If it exists, it is not a necessary condition to define the termination trench 102b as a ring shape, as long as the through hole 107b is opened in the termination trench 102b or the active trench 102a. If it is attempted to cancel the termination trench 102b and only retain the active trench 102a, it is only necessary to open a via hole in the control gate 107a on the top of the active trench 102a. According to the content disclosed above in the present invention, it is easy to understand that when desired Opening a through hole in the control gate 107a on the top of the active trench 102a, the process steps are exactly the same as the steps of opening a through hole in the control gate 107a on the top of the termination trench 102b, so it will not be described in detail. When the through hole 107b is opened in the trench 102a, it is only necessary to lead out the shield gate 104a at the lower part of the active trench 102a to be short-circuited with the top metal layer 113 serving as the source electrode. Of course, in other embodiments, if the field plate 109b is required, the termination trench 102b around the active trench 102a can be prepared.

According to the spirit of the present invention, it is possible to reduce the level of photomasks and simplify the processing technology, which not only reduces the processing difficulty and processing cost, but also realizes high breakdown voltage, low conduction resistance and improved yield, and the device can have a relatively high Strong market competitiveness. The invention also abandons the traditional way of using expensive processes such as HDP and CMP, and the holes opened on the shielding grid do not need expensive chemical vapor deposition methods to realize metallization, which effectively reduces the difficulty of the process and greatly enhances the long-term durability of the device. reliability.

Above, through description and accompanying drawings, typical embodiments of specific structures of specific embodiments are given, and the above inventions propose existing preferred embodiments, but these contents are not intended to be limiting. Various changes and modifications will no doubt become apparent to those skilled in the art upon reading the foregoing description. Therefore, the appended claims should be considered to cover all changes and modifications within the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should still be deemed to be within the intent and scope of the present invention.

Claims (27)

1. with a preparation method for the groove-type power device of splitting bar, it is characterized in that, comprise the following steps:

The top of steps A, the epitaxial loayer on base substrate etches a termination groove and a plurality of active groove;

Step B, generation one first insulating barrier, be covered in termination groove and active groove sidewall and bottom separately, is covered on the end face of epitaxial loayer simultaneously;

Step C, at termination groove, active groove under-filled electric conducting material separately, as shield grid;

Step D, etching remove termination groove, active groove the first insulating barrier on upper portion side wall place and epitaxial loayer end face separately, and above each shield grid, prepare a separator;

Step e, generate the second insulating barrier, cover termination groove and active groove separately on the exposed sidewall in top, be covered on the end face of epitaxial loayer simultaneously;

Step F, at termination groove, active groove top filled conductive material separately, as control gate;

Step G, in termination groove etching control gate and separator, define one or more through holes that expose shield grid;

The top medium layer of the second insulating barrier on epitaxial loayer end face has been merged in step H, formation one, is covered on epitaxial loayer end face and each control gate, synchronously forms the sidewall that a sidepiece dielectric layer is attached to through hole;

Step I, filled conductive material are to through hole;

Step J, formation one insulating passivation layer are covered on top medium layer and through hole;

Step K, etching insulating passivation layer at least form first set contact hole wherein, fill subsequently metal plug to first set contact hole and on top medium layer, depositing a metal layer at top, the metal plug arranging in first set contact hole is electrically connected electric conducting material and the metal layer at top in through hole.

2. the method for claim 1, is characterized in that, in step C, comprises the following steps:

Deposits conductive material, covers the top of the first insulating barrier on epitaxial loayer end face for the first time, and is filled in termination groove and active groove;

Return and carve electric conducting material, retain termination groove, the active groove electric conducting material of bottom separately, as shield grid.

3. the method for claim 1, is characterized in that, in step D, comprises the following steps:

Deposition insulant, is covered in the top of the first insulating barrier on epitaxial loayer end face, and is filled in termination groove and active groove top separately;

Return to carve and to remove insulant, and return to carve to remove and be covered in termination groove, active groove the first insulating barrier on upper portion side wall place and epitaxial loayer end face separately, a nationality that retains each shield grid top is returned the separator of carving and staying by insulant.

4. the method for claim 1, is characterized in that, in step F, comprises the following steps:

Deposits conductive material, covers the top of the second insulating barrier on epitaxial loayer end face for the second time, and is filled in the top of termination groove and active groove;

Return and carve electric conducting material, retain termination groove, the active groove electric conducting material on top separately, as control gate.

5. the method for claim 1, is characterized in that, in step G, comprises the following steps:

On the second insulating barrier top on epitaxial loayer end face and the top of each control gate, form a photoresist layer;

Nationality is controlled the opening of gate region for inner minute in photoresist layer for exposing termination groove, control gate and the separator in etching termination groove, forms one or more through holes that expose shield grid downwards.

6. the method for claim 1, is characterized in that, in step H, comprises the following steps:

Above the second insulating barrier on epitaxial loayer end face, prepare the insulating medium layer with the identical material of the second insulating barrier, original the second insulating barrier on this SI semi-insulation dielectric layer and epitaxial loayer end face merges and forms in a top medium layer, and this top medium layer is covered on epitaxial loayer end face and each control gate;

The synchronous another part insulating medium layer forming is also attached on the sidewall that through hole is exposed to form sidepiece dielectric layer.

7. method as claimed in claim 6, is characterized in that, after step H, comprises the following steps:

Directly utilize top medium layer as etch mask, dry etching removes in the step that generates top medium layer and sidepiece dielectric layer and is synchronously covered in the insulating medium layer at the exposed region place of the shield grid below through hole.

8. the method for claim 1, is characterized in that, in step I, comprises the following steps:

Deposits conductive material, covers the top of the top medium layer on epitaxial loayer end face and is filled in through hole for the third time;

Return and carve electric conducting material, retain the electric conducting material in through hole.

9. the method for claim 1, is characterized in that, in step F, G, H, I after any one step, but before step J, further comprising the steps of:

At least the top of the epitaxial loayer inside termination groove is implanted alloy and is formed a body layer, is centered around each active groove top around; And

Near one source pole layer implanting alloy formation epitaxial loayer end face at the top of body layer.

10. method as claimed in claim 9, it is characterized in that, when step K etching insulating passivation layer, also comprise downwards etching insulating passivation layer, top medium layer, source layer and body layer successively, form and extend in body layer and second overlapping contact hole between adjacent active groove or between active groove and termination groove; And

Also in the second cover contact hole, fill metal plug subsequently, the metal plug in formed metal layer at top and the second cover contact hole forms in electrical contact.

11. the method for claim 1, it is characterized in that, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at electric conducting material in described through hole, thereby the metal plug of filling in first set contact hole is electrically connected the electric conducting material in through hole.

12. methods as claimed in claim 4, is characterized in that, in step I, comprise the following steps:

When returning the electric conducting material depositing for the third time quarter, also retain a part of electric conducting material overlap on termination groove as a field plate, wherein, this part electric conducting material termination groove outside expansion in the horizontal direction that forms this field plate is extended, until extend near epitaxial loayer periphery edge.

13. methods as claimed in claim 12, it is characterized in that, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at this field plate, thereby the metal plug of filling in first set contact hole is electrically connected to the electric conducting material in the through hole of field plate below via field plate.

14. 1 kinds of groove-type power devices with splitting bar, is characterized in that, comprising:

One base substrate and be positioned at the epitaxial loayer on base substrate;

Be formed on a termination groove and a plurality of active groove in epitaxial loayer;

Be filled in respectively active groove, termination groove separately bottom shield grid and be filled in their control gates on top separately, between a control gate of each shield grid and its top, be provided with a separator insulation;

At least be formed on termination groove inner side epitaxial loayer top and be centered around each active groove top body layer around, and the one source pole layer that is formed on body layer top;

Run through successively downwards on one or more sidewalls of control gate, separator in termination groove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole;

A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered and be positioned at the insulating passivation layer on top medium layer;

Downwards run through successively insulating passivation layer, top medium layer and source layer and extend to body layer in and second overlapping contact hole between adjacent active groove or between active groove and termination groove, and running through insulating passivation layer downwards and aim at the first set contact hole of the interior electric conducting material of described through hole;

Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer;

The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.

15. 1 kinds of groove-type power devices with splitting bar, is characterized in that, comprising:

One base substrate and be positioned at the epitaxial loayer on base substrate;

Be formed on a termination groove and a plurality of active groove in epitaxial loayer;

Be filled in respectively active groove, termination groove separately bottom shield grid and be filled in their control gates on top separately, between a control gate nationality of each shield grid and its top, be provided with a separator;

At least be formed on termination groove inner side epitaxial loayer top and be centered around each active groove top body layer around, and the one source pole layer that is formed on body layer top;

Run through successively downwards on one or more sidewalls of control gate, separator in termination groove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole;

A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered;

Be positioned on top medium layer and overlap on the field plate on termination groove, field plate outwards extends to the outside of termination groove in the horizontal direction;

When being arranged on top medium layer, also envelope the insulating passivation layer of described field plate;

Downwards run through successively insulating passivation layer, top medium layer and source layer and extend to body layer in and second overlapping contact hole between adjacent active groove or between active groove and termination groove, and running through insulating passivation layer downwards and aim at the first set contact hole of described field plate;

Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer;

The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.

16. 1 kinds of preparation methods with the groove-type power device of splitting bar, is characterized in that, comprise the following steps:

The top of steps A, the epitaxial loayer on base substrate etches a plurality of grooves;

Step B, generation one first insulating barrier, be covered in each trenched side-wall and bottom, and be covered on the end face of epitaxial loayer;

Step C, at the under-filled electric conducting material of groove, as shield grid;

Step D, etching remove the first insulating barrier on groove upper portion side wall place and epitaxial loayer end face, and above each shield grid, prepare a separator;

Step e, generate the second insulating barrier, on the exposed sidewall in covering groove top, be covered on the end face of epitaxial loayer simultaneously;

Step F, at groove top filled conductive material, as control gate;

Step G, in part groove etching control gate and separator, define one or more through holes that expose shield grid;

The top medium layer of the second insulating barrier on epitaxial loayer end face has been merged in step H, formation one, is covered on epitaxial loayer end face and each control gate, synchronously forms the sidewall that a sidepiece dielectric layer is attached to through hole;

Step I, filled conductive material are to through hole;

Step J, formation one insulating passivation layer are covered on top medium layer and through hole;

Step K, etching insulating passivation layer at least form first set contact hole wherein, fill subsequently metal plug to first set contact hole and on top medium layer, depositing a metal layer at top, the metal plug arranging in first set contact hole is electrically connected electric conducting material and the metal layer at top in through hole.

17. methods as claimed in claim 16, is characterized in that, in step C, comprise the following steps:

Deposits conductive material, covers the top of the first insulating barrier on epitaxial loayer end face, and is filled in groove for the first time;

Return and carve electric conducting material, retain the electric conducting material of groove bottom, as shield grid.

18. methods as claimed in claim 16, is characterized in that, in step D, comprise the following steps:

Deposition insulant, is covered in the top of the first insulating barrier on epitaxial loayer end face, and is filled in the top in groove;

Return and remove insulant quarter, and remove the first insulating barrier being covered on groove upper portion side wall place and epitaxial loayer end face time quarter, a nationality that retains each shield grid top is returned the separator of carving and staying by insulant.

19. methods as claimed in claim 16, is characterized in that, in step F, comprise the following steps:

Deposits conductive material, covers the top of the second insulating barrier on epitaxial loayer end face for the second time, and is filled in the top of groove;

Return and carve electric conducting material, retain the electric conducting material on groove top, as control gate.

20. methods as claimed in claim 16, is characterized in that, in step G, comprise the following steps:

On the second insulating barrier top on epitaxial loayer end face and the top of each control gate, form a photoresist layer;

Nationality is for exposing the opening in a part of control gate region in pregroove in photoresist layer, and control gate and the separator in this pregroove of etching, forms one or more through holes that expose shield grid downwards.

21. methods as claimed in claim 16, is characterized in that, in step H, comprise the following steps:

Above the second insulating barrier on epitaxial loayer end face, prepare the insulating medium layer with the identical material of the second insulating barrier, original the second insulating barrier on this SI semi-insulation dielectric layer and epitaxial loayer end face merges and forms in a top medium layer, and this top medium layer is covered on epitaxial loayer end face and each control gate;

The synchronous another part insulating medium layer forming is also attached on the sidewall that through hole is exposed to form sidepiece dielectric layer.

22. methods as claimed in claim 21, is characterized in that, after step H, comprise the following steps:

Directly utilize top medium layer as etch mask, dry etching removes in the step that generates top medium layer and sidepiece dielectric layer and is synchronously covered in the insulating medium layer at the exposed region place of the shield grid below through hole.

23. methods as claimed in claim 16, is characterized in that, in step I, comprise the following steps:

Deposits conductive material, covers the top of the top medium layer on epitaxial loayer end face and is filled in through hole for the third time;

Return and carve electric conducting material, retain the electric conducting material in through hole.

24. methods as claimed in claim 16, is characterized in that, in step F, G, H, I after any one step, but before step J, further comprising the steps of:

At least the top of the epitaxial loayer inside outermost groove is implanted alloy and is formed a body layer, is centered around each groove top around; And

Near one source pole layer implanting alloy formation epitaxial loayer end face at the top of body layer.

25. methods as claimed in claim 24, it is characterized in that, when step K etching insulating passivation layer, also comprise downwards etching insulating passivation layer, top medium layer, source layer and body layer successively, form the second cover contact hole extending in body layer and between adjacent trenches; And

Also in the second cover contact hole, fill metal plug subsequently, the metal plug in formed metal layer at top and the second cover contact hole forms in electrical contact.

26. methods as claimed in claim 16, it is characterized in that, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at electric conducting material in described through hole, thereby the metal plug of filling in first set contact hole is electrically connected the electric conducting material in through hole.

27. 1 kinds of groove-type power devices with splitting bar, is characterized in that, comprising:

One base substrate and be positioned at the epitaxial loayer on base substrate;

Be formed on a plurality of grooves in epitaxial loayer;

Be filled in the shield grid and the control gate that is filled in groove top of groove bottom, between each shield grid and a control gate of its top, be provided with a separator insulation;

At least be formed on outermost groove inner side epitaxial loayer top and be centered around each groove top body layer around, and the one source pole layer that is formed on body layer top;

Run through successively downwards on one or more sidewalls of control gate, separator in a part of pregroove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole;

A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered and be positioned at the insulating passivation layer on top medium layer;

Run through successively insulating passivation layer, top medium layer and source layer downwards and extend to the second cover contact hole in body layer and between adjacent trenches, and run through the first set contact hole of electric conducting material in insulating passivation layer aligned through holes downwards;

Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer;

The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.