CN104007571B - Array base plate and manufacture method thereof - Google Patents
Array base plate and manufacture method thereof Download PDFInfo
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- CN104007571B CN104007571B CN201410244058.0A CN201410244058A CN104007571B CN 104007571 B CN104007571 B CN 104007571B CN 201410244058 A CN201410244058 A CN 201410244058A CN 104007571 B CN104007571 B CN 104007571B
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- layer
- array base
- line terminals
- metal layer
- scanning line
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Abstract
The invention discloses an array base plate. The array base plate comprises a substrate base plate (1), a first metal layer (2), a JAS layer (3) and an ITO (Indium Tin Oxide) electrode layer (4), wherein the JAS layer (3) and the ITO electrode layer (4) are positioned on a source drain insulation layer; a first metal layer (2) forms data line terminals and scanning line terminals in an array manufacture procedure. The array base plate is characterized in that hole etching baffling layers (5) positioned between a grid electrode insulation layer (7) and the source drain electrode insulation layer are formed above hole etching parts at the data line terminals and the scanning line terminals; the residual ITO electrodes that are produced by the ITO electrode layer (4) at the side edge of the JAS layer (3) during imaging the ITO electrode layer (4) can be remained on the hole etching baffling layers (5) through the hole etching baffling layers (5). According to the array base plate, the hole etching baffling layers arranged enable the ITO electrodes that are residual at the side edge of the JAS layer during imaging the ITO electrode layer to be remained only on the hole etching baffling layers, and thus short circuit generated between the data line terminals or the scanning line terminals can be avoided.
Description
Technical field
The present invention relates to liquid crystal display manufacturing technology field, specifically a kind of by the terminal in the first metal layer
Carve to add above hole portion position and carve hole barrier layer to prevent array base palte and its manufacture method of the short-circuit of terminals.
Background technology
Traditional crt display relies on the fluorescent material that cathode-ray tube launching electronics are clashed on screen to carry out display image, but
The principle of liquid crystal display is then entirely different.Generally, liquid crystal display (lcd) device has upper substrate and infrabasal plate, has certain each other
It is spaced and mutually face.The multiple electrodes being formed on two substrates are facing each other.Liquid crystal is clipped between upper substrate and infrabasal plate.
Voltage is applied on liquid crystal by the electrode on substrate, then changes the arrangement of liquid crystal molecule thus showing according to the voltage being acted on
Because that liquid crystal indicator not launching light, it needs light source to carry out display image to diagram picture.Therefore, liquid crystal display dress
Put the backlight having after liquid crystal panel.Controlled from the incident light quantity of backlight thus showing according to the arrangement of liquid crystal molecule
Diagram picture.Glass substrate, colored filter, electrode, liquid crystal layer and crystal is accompanied between two pieces of polaroids of this liquid crystal display
Pipe film, liquid crystal molecule is the material with refractive index and dielectric constant anisotropy.The light that backlight sends is through lower inclined
Mating plate, becomes the polarised light with certain polarization direction.Institute's making alive between transistor controlled electrode, and this voltage acts on liquid
Controlling the polarization direction of polarised light, polarised light forms monochromatic polarised light through after color film chromatograph accordingly to crystalline substance, if polarised light
Upper strata polaroid can be penetrated, then show corresponding color；Electric-field intensity is different, and the deflection angle of liquid crystal molecule is also different,
Through light intensity different, the brightness of display is also different.Show five by the combination of the different light intensity of three kinds of colors of RGB
The image of Yan Liuse.
Terminal on array base palte is the interface connecting scan line, data wire and external drive ic.Typically in array base palte
On scanning line terminals data line terminals can be set, because data wire can be typically several times of scan line, so data line end
Quantum count can be more than scanning line terminals, and interval smaller, and data line terminal spacing is 12.5um, and scan line terminal pitch is
27.5um, because data line terminal interval is little, the probability being short-circuited is also relatively large.Portion of terminal essential structure is generally strip
Ito is covered, rear extended meeting is passed through crimping engineering and connected with corresponding cof above scan line.
In the design of high opening, organic insulator (hereinafter referred to as jas layer) can be made on sd insulating barrier, can be effective
Improve aperture opening ratio.Jas layer is the organic material layer of more than 2um.Jas machine portion of terminal can by carve hole engineering by jas layer and
Insulating barrier removes, and exposes data line terminal and scanning line terminals, then makes ito electrode.But now due to jas layer edge
High segment difference can lead to photoresist to occur to expose insufficient residual, leads to ito electrode layer (transparent electrode layer) between terminal to remain and draw
Play the short-circuit of terminals.As shown in figure 1, using jas material when, the bad phenomenon being short-circuited at terminal, be mainly shown as terminal it
Between ito electrode remain.As shown in Fig. 2 the array base palte that is patterned into of ito electrode layer 4 forms last step, here
Step forms pixel electrode, contact pore electrod and terminal electrode；It is the ito electrode layer 4 that whole face is formed on array base palte first
Figure, then coating photoresist 6.As shown in figure 3, being exposed to photoresist 6 developing, due to thicker (the general 2- of jas material
3um) thus jas layer 3 bottom margin photoresist 6 with respect to thicker elsewhere it is impossible to sufficiently be exposed, lead to
Photoresist 6 occurs during development remain.As shown in figure 4, carry out ito electrode layer 4 graphical when due to the protection of photoresist 6, jas
The ito electrode material at layer 3 edge cannot be etched away, and left behind, and the ito electrode connection which results between terminal is short
Road.As shown in figure 5, illustrating for interface at b-b, between terminal, ito electrode residual leads to the short-circuit of terminals to occur.
Content of the invention
The purpose of the present invention be for prior art exist problem, provide a kind of by the first metal layer terminal carve
Add above hole portion position and carve hole barrier layer to prevent array base palte and its manufacture method of the short-circuit of terminals.
The purpose of the present invention solves by the following technical programs:
A kind of array base palte, including underlay substrate, the first metal layer, the jas layer being located on source-drain electrode insulating barrier and ito electricity
Pole layer, in array process by the first metal layer formed data line terminal and scanning line terminals it is characterised in that: in data line end
The quarter hole that the top of the quarter hole portion position of son and scanning line terminals is provided between gate insulator and source-drain electrode insulating barrier stops
Layer, so that the residual that the ito electrode layer being located at jas layer edge when ito electrode layer is graphical produces is present in quarter hole barrier layer
On.
Between described quarter hole barrier layer and the first metal layer, there is gate insulator.
Described quarter hole barrier layer is second metal layer or semiconductor active layer.
Described hole barrier layer of carving covers above the quarter hole portion position of data line terminal and scanning line terminals.
Described quarter hole barrier layer is continuous type pattern or discontinuous form pattern.
The width carving hole barrier layer of continuous type pattern is not less than data line terminal and the width of scanning line terminals.
The width carving hole barrier layer of discontinuous form pattern is not less than any one data line terminal and the width of scanning line terminals.
Described hole barrier layer of carving is intersected with the bore edges of data line terminal and the quarter hole portion position of scanning line terminals.
A kind of manufacture method of array base palte it is characterised in that: this manufacture method comprises the following steps that
(a), on underlay substrate, form the first metal layer, scan line, grid and data wire are formed by the first metal layer
Terminal, scanning line terminals；
(b), deposit gate insulator on the first metal layer；
(c), on gate insulator deposited semiconductor active layer；
(d), second metal layer is formed on semiconductor active layer, data wire, source-drain electrode are formed by second metal layer, and
Semiconductor active layer or second metal layer cover to be formed above the quarter hole portion position of data line terminal and scanning line terminals and carve
Hole barrier layer；
E () forms source-drain electrode insulating barrier in second metal layer；
F () forms jas layer on source-drain electrode insulating barrier；
G () carries out carving hole to data line terminal and scanning line terminals, source-drain electrode respectively；
H () deposits ito electrode layer on jas layer and carries out ito electrode layer patterning process, form pixel electrode, contact
Pore electrod and terminal electrode, then complete the manufacture process of array base palte.
The present invention has the following advantages compared to existing technology:
The present invention passes through to carve in the terminal of the first metal layer and adds quarter hole barrier layer above hole portion position so that in ito electrode
During layer pattern, when jas layer edge occurs ito electrode residual, the ito electrode of residual only can be present in quarter hole and stop
On layer, and carve and between hole barrier layer and the first metal layer, there is gate insulator, thus avoiding between data line terminal or scanning
Short circuit is produced between line terminals；Second metal layer is passed through on this quarter hole barrier layer or the extension of semiconductor active layer can achieve, work
Skill clear process and operation easier is little, suitably promotes the use of.
Brief description
Accompanying drawing 1 is when data line terminal or the scan line short-circuit of terminals on the array base palte of jas machine in prior art
Structural representation；
Accompanying drawing 2 is a-a section structural representation during coating photoresist before ito electrode layer is graphical in accompanying drawing 1；
Accompanying drawing 3 is the structural representation after the photoresist exposure imaging in accompanying drawing 2；
Accompanying drawing 4 is the structural representation after ito electrode layer etching in accompanying drawing 3；
Accompanying drawing 5 is b-b cross section structure schematic diagram in accompanying drawing 1；
Accompanying drawing 6 is the array base-plate structure schematic diagram of the embodiment of the present invention one；
Accompanying drawing 7 is the a-a cross section structure schematic diagram of accompanying drawing 6；
Accompanying drawing 8 is the array base-plate structure schematic diagram of the embodiment of the present invention two.
Wherein: 1 underlay substrate；2 the first metal layers；3 jas layers；4 ito electrode layers；5 quarter holes barrier layer；
6 photoresists；7 gate insulators.
Specific embodiment
The present invention is further illustrated with embodiment below in conjunction with the accompanying drawings.
As shown in figs 6-8: a kind of array base palte, array base palte making step is: the first step forms on underlay substrate 1
One metal level 2, second step forms gate insulator 7, and the 3rd step forms semiconductor active layer, and the 4th step forms second metal layer,
And forming source-drain electrode, the 5th step forms source-drain electrode insulating barrier, and the 6th step forms jas layer 3, the 7th step forms contact hole, the 8th step
Form ito electrode layer 4.
In array process, data line terminal and scanning line terminals are formed by the first metal layer 2, in order to prevent between terminal
Ito electrode there is residual and lead to the short-circuit of terminals, be provided with position above the quarter hole portion position of data line terminal and scanning line terminals
Quarter hole barrier layer 5 between gate insulator 7 and source-drain electrode insulating barrier, so that be located at jas when ito electrode layer 4 is graphical
The residual that the ito electrode layer 4 at layer 3 edge produces is present on quarter hole barrier layer 5, due to carving hole barrier layer 5 and the first metal
Between layer 2, there is gate insulator 7, thus avoiding between data line terminal or scan producing short circuit between line terminals.Above-mentioned
Carve hole barrier layer 5 to cover above the quarter hole portion position of data line terminal and scanning line terminals and carve hole barrier layer 5 and data wire
Terminal and scanning line terminals quarters hole portion position bore edges intersect, in addition quarter hole barrier layer 5 can be set to continuous type pattern or
Discontinuous form pattern, when carving hole barrier layer 5 for continuous type pattern, the width carving hole barrier layer 5 is not less than data line terminal and sweeps
Retouch the width of line terminals；When carving hole barrier layer 5 for discontinuous form pattern, the width carving hole barrier layer 5 is not less than any one data
Line terminals and the width of scanning line terminals.This facilitates array process, and this quarter hole barrier layer 5 is had by second metal layer or semiconductor
The extension of active layer can achieve, hole barrier layer 5 can be second metal layer or semiconductor active layer at once.
The step of the manufacture method of above-mentioned array base palte is as follows: (a), the first metal layer 2 is formed on underlay substrate 1, by
The first metal layer 2 forms scan line, grid and data line terminal, scanning line terminals；(b), deposit on the first metal layer 2
Gate insulator 7；(c), on gate insulator 7 deposited semiconductor active layer；(d), form second on semiconductor active layer
Metal level, forms data wire, source-drain electrode, and semiconductor active layer by second metal layer or second metal layer covers in data
The top of the quarter hole portion position of line terminals and scanning line terminals is formed carves hole barrier layer 5；E () forms source-drain electrode in second metal layer
Insulating barrier；F () forms jas layer 3 on source-drain electrode insulating barrier；G () enters respectively to data line terminal and scanning line terminals, source-drain electrode
Row carves hole；H () deposits ito electrode layer 4 on jas layer 3 and carries out ito electrode layer patterning process, form pixel electrode, contact
Pore electrod and terminal electrode, then complete the manufacture process of array base palte.
The present invention pass through the first metal layer 2 terminal carve hole portion position above add quarter hole barrier layer 5 so that ito electricity
During pole layer 4 is patterned, when jas layer 3 edge occurs ito electrode residual, the ito electrode of residual only can be present in quarter hole
On barrier layer 5, and carve and between hole barrier layer 5 and the first metal layer 2, there is gate insulator 7, thus avoid data line terminal it
Between or scanning line terminals between produce short circuit；This quarter hole barrier layer 5 by the extension of second metal layer or semiconductor active layer is
Can achieve, technological process is clear and operation easier is little, suitably promotes the use of.
Above example technological thought only to illustrate the invention is it is impossible to limit protection scope of the present invention with this, every
According to technological thought proposed by the present invention, any change done on the basis of technical scheme, each fall within the scope of the present invention
Within；The technology that the present invention is not directed to all can be realized by prior art.
Claims (9)
1. a kind of array base palte, the organic insulator (3) including the first metal layer (2), being located on source-drain electrode insulating barrier and ito electricity
Pole layer (4), in array process by the first metal layer (2) formed data line terminal and scanning line terminals it is characterised in that: counting
Top according to line terminals and the quarter hole portion position of scanning line terminals is provided with positioned between gate insulator (7) and source-drain electrode insulating barrier
Carve hole barrier layer (5), so that the ito electrode layer (4) being located at organic insulator (3) edge when ito electrode layer (4) is graphical produces
Raw residual was present on quarter hole barrier layer (5).
2. array base palte according to claim 1 it is characterised in that: described quarter hole barrier layer (5) and the first metal layer
(2) there is between gate insulator (7).
3. array base palte according to claim 1 and 2 it is characterised in that: described quarter hole barrier layer (5) be the second metal
Layer or semiconductor active layer.
4. array base palte according to claim 1 and 2 it is characterised in that: described quarter hole barrier layer (5) covers in data
The top of the quarter hole portion position of line terminals and scanning line terminals.
5. array base palte according to claim 1 and 2 it is characterised in that: described quarter hole barrier layer (5) be continuous type figure
Case or discontinuous form pattern.
6. array base palte according to claim 5 it is characterised in that: the width on the quarter hole barrier layer (5) of continuous type pattern
Width not less than data line terminal and scanning line terminals.
7. array base palte according to claim 5 it is characterised in that: the width on the quarter hole barrier layer (5) of discontinuous form pattern
Width not less than any one data line terminal and scanning line terminals.
8. array base palte according to claim 5 it is characterised in that: described quarter hole barrier layer (5) and data line terminal
Intersect with the bore edges of the quarter hole portion position of scanning line terminals.
9. a kind of manufacture method of array base palte it is characterised in that: this manufacture method comprises the following steps that
(a), form the first metal layer (2) underlay substrate (1) is upper, by the first metal layer (2) formed scan line, grid and
Data line terminal, scanning line terminals；
(b), in the first metal layer (2) upper deposition gate insulator (7)；
(c), in the upper deposited semiconductor active layer of gate insulator (7)；
(d), second metal layer is formed on semiconductor active layer, data wire, source-drain electrode are formed by second metal layer, and partly leads
Body active layer or second metal layer cover to be formed above the quarter hole portion position of data line terminal and scanning line terminals and carve hole resistance
Barrier (5)；
E () forms source-drain electrode insulating barrier in second metal layer；
F () forms organic insulator (3) on source-drain electrode insulating barrier；
G () carries out carving hole to data line terminal and scanning line terminals, source-drain electrode respectively；
H () in organic insulator (3) upper deposition ito electrode layer (4) and carries out ito electrode layer patterning process, form pixel electricity
Pole, contact pore electrod and terminal electrode, then complete the manufacture process of array base palte.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410244058.0A CN104007571B (en) | 2014-06-04 | 2014-06-04 | Array base plate and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410244058.0A CN104007571B (en) | 2014-06-04 | 2014-06-04 | Array base plate and manufacture method thereof |
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| Publication Number | Publication Date |
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| CN104007571A CN104007571A (en) | 2014-08-27 |
| CN104007571B true CN104007571B (en) | 2017-01-18 |
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| CN201410244058.0A Expired - Fee Related CN104007571B (en) | 2014-06-04 | 2014-06-04 | Array base plate and manufacture method thereof |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106648250B (en) * | 2016-12-30 | 2020-04-10 | 南京中电熊猫液晶显示科技有限公司 | In-Cell touch panel and manufacturing method thereof |
| CN108987411A (en) * | 2017-06-02 | 2018-12-11 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display device |
| CN107367771B (en) * | 2017-07-11 | 2020-01-31 | 中国科学院电子学研究所 | Electrochemical geophone sensitive electrode and preparation method thereof |
| US10453868B2 (en) * | 2018-03-02 | 2019-10-22 | Innolux Corporation | Display apparatus |
| CN110109573B (en) * | 2019-05-27 | 2023-02-24 | 昆山龙腾光电股份有限公司 | Touch control assembly and touch control display panel |
| CN110488525B (en) * | 2019-08-30 | 2021-12-17 | 厦门天马微电子有限公司 | Display panel and display device |
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|---|---|---|---|---|
| US6317174B1 (en) * | 1999-11-09 | 2001-11-13 | Kabushiki Kaisha Advanced Display | TFT array substrate, liquid crystal display using TFT array substrate, and manufacturing method thereof |
| CN102224536A (en) * | 2008-11-21 | 2011-10-19 | 夏普株式会社 | Substrate for display panel, and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3305235B2 (en) * | 1997-07-01 | 2002-07-22 | 松下電器産業株式会社 | Active element array substrate |
| JP3377003B2 (en) * | 2001-12-10 | 2003-02-17 | 松下電器産業株式会社 | Method for manufacturing active element array substrate |
| JP2009128761A (en) * | 2007-11-27 | 2009-06-11 | Sharp Corp | Substrate device and method for manufacturing the same, and display device |
| WO2013137081A1 (en) * | 2012-03-12 | 2013-09-19 | シャープ株式会社 | Display panel |
| JP2014095795A (en) * | 2012-11-09 | 2014-05-22 | Japan Display Inc | Liquid crystal display device and method for manufacturing the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6317174B1 (en) * | 1999-11-09 | 2001-11-13 | Kabushiki Kaisha Advanced Display | TFT array substrate, liquid crystal display using TFT array substrate, and manufacturing method thereof |
| CN102224536A (en) * | 2008-11-21 | 2011-10-19 | 夏普株式会社 | Substrate for display panel, and display panel |
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