CN103973600A - Rotate-mask-merge and deposit-field instructions for packet processing - Google Patents
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Abstract
The invention provides rotate-mask-merge and deposit-field instructions for packet processing. In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.
Description
Present patent application requires the U.S. Provisional Application 61/759 that is entitled as " Rotate-Mask-Merge andDeposit-Field Instructions for Packet Processing " of submitting on February 2nd, 2013, the priority of 661 (acting on behalf of code T I-73436PS), it is incorporated herein by reference.
Background technology
Computer hardware can be tackled and record by the flow of digital network or a part of digital network.For example, there is requirement the computer hardware unit (being commonly called " switch ") of execution Ethernet packet switching for several functions.One class function is conventionally based on grouping and the entry in flowmeter are matched to revise grouping.This coupling action is a part for OpenFlow standard.
Eurypalynous division operation is permitted in existence, and these division operations are useful, possibility or even essential function, but not by OpenFlow prescribed by standard.The desirable attributes of attempting to present the exchange of the user model based on coupling action is that they can carry out general and dissimilar division operation, so that they can realize the desired action of user of these switches of programming.
High-performance switch has the limited time and processes each grouping.For example, the switch of the every port of 64 ports × 10Gb has the 640Gb/ total bandwidth of second.Minimum Ethernet grouping taking size as 64 bytes adds the inter-packet gap of approximately 16 bytes, is about 960M grouping per second for the maximum packet rate of such switch.For example, see that with each clock cycle of hardware packet transaction streamline of 1GHz operation a stream of packets crosses streamline (together with the protection bandwidth of about 40MHz).As a result, carry out the hardware of division operation or must within the single clock cycle, complete its function, or this hardware must pipelining.In any situation, for independent grouping, can not repeatedly reuse hardware and repeatedly calculate.This makes to be hopeful to keep division operation hardware simplicity.In addition, on integrated circuit, may there are many copies of this hardware, for keeping hardware simplicity that further motivation is provided.
Brief description of the drawings
Figure 1A shows the extraction instruction that from source operand any position obtains any length field and moved down into the bit 0 in result.(prior art)
Figure 1B show obtain from the low step bit of the first source operand and replace second (backstage) source operand field deposit byte (deposit-bype) instruction.(prior art)
What Fig. 1 C showed according to one embodiment of present invention any length field of any position acquisition that can be from source operand and deposited any position in consistency operation number deposits field instruction.
Fig. 2 A illustrates the block diagram of depositing byte hardware.(prior art)
Fig. 2 B illustrates the block diagram of depositing byte hardware according to one embodiment of present invention.
Fig. 3 A illustrates the block diagram of depositing field hardware according to one embodiment of present invention.
Fig. 3 B is the block diagram that the hardware for realizing byte rotation union operation is shown according to one embodiment of present invention.
Embodiment
At an embodiment for the architecture of packet transaction, wherein after grouping is resolved, header fields is registered in the packet header vector being made up of multiple independently 8 bits, 16 bits and 32 Bit data time slots, and each time slot has one and follows significant bit.Data in this packet header vector are sequentially sent to multiple coupling actions and are processed level, wherein in every one-level, field in packet header vector can be for mating the list item (table entry) in this grade, and as the result of mating, can specify the action of the content that can revise this packet header vector.Action engine is VLIW (very long instruction word) architecture, and it has independent data processing unit for the each independent data field in packet header vector.For each data slot of packet header vector, the instruction of the operation of guiding action engine has independent instruction field.Therefore,, for each time slot of packet header vector, action is made up of independent processing instruction.
In the Ethernet grouping that comprises IPV4 (internet protocol version 4) header, the source address of 32 bit IP (Internet protocol) and destination address are conventionally by 32 bit time slots that obtain separately in packet header vector, and the value in those time slots is deposited the result for resolving this grouping by analyzer.In the Ethernet grouping that comprises IPV6 (internet protocol version 6) header, the IPV6 source address of 128 bits and destination address will be retained in the time slot of four 32 bits of packet header vector separately.
It is that 32 bit address space due to IPV4 address are about to exhaust that the IPV6 of 128 bits is introduced into.In Internet Engineering task groups IETF RFC6052, provide a standard for reference address between IPV4 and IPV6 form.It has specified the multiple arrangements for reference address between IPV4 and IPV6, as below from as shown in the table 1 of RFC6052:
Large syllable sequence:
Table 1:IPV4 embeds military IPV6 address format
This table has specified how to use the prefix (in table, PL represents prefix length) of different length to make IPV6 address can represent the multiple choices of IPV4 address.In this table, u position is necessary for 0, and suffix position should be also 0.Suppose a known particular prefix length, likely recover IPV4 address from IPV6 address, and prefix length of supposition and prefix likely become IPV6 address by IPV4 address transition.Certainly, not all IPV6 address can both convert IPV4 address to, if but known this IPV6 address is to use in this way specific prefix length from IPV4 address creation, likely recover this IPV4 address.
Although above-mentioned table 1 is specified with large syllable sequence (big-endian) form, in the time hardware being discussed below, little-endian (little-endian) is preferred, and wherein bit 0 is lsb (minimum effective bit) all the time.Represent to reappear upper table with little-endian below:
Little-endian:
Table 2: the IPV4 embedded IP V6 address format of little-endian
At packet header vector V6[3:0] four 32 bit time slots arrays in by the IPV6 address that comprises 128 bits, wherein v6[3] comprise the highest effective 32 bits, and v6[0] comprise minimum effective 32 bits, as shown in table 3 below:
Table 3:IPV6 packet header vector field
In order to carry out the conversion of IPV6 to IPV4 according to the present invention, for each selection of prefix length (PL), from IPV6 address, extract the different bits of many groups out and link together, as shown in table 4.Here, signal <bh:bl> represents the signal from higher bit bh (high position) to low bit bl (low level).If these bits are subsets of the complete bit width of primary signal, this labelling method can be regarded as extracting from original complete signal the bit field of expecting.Symbol below ":: " represent to connect two vectors, higher effective vector is in left side.For example, #xabcd::#xef is #xabcdef.
Table 4:IPV6 is to extraction and the union operation of IPV4
If the v6IPV6 address field in upper table is represented as their 32 bit groupings header vector word V6[3:0], operation becomes:
Table 5: to extraction and the union operation of packet header vector word
Although do not need operation for PL=32 or 96, must be extracted and merge from two fields of other PL of different grouping header vector word.
In this embodiment of the present invention, merging can be described to the sequence of two operations.In the first operation, two data sources are moved into respectively their correct stop bits positions in output word independently, and then, in the second operation, each bit that mask is this output is selected one or the other (the selecting by bit) in these sources.For this discussion, by convention, first in two sources will finally form the higher live part of this output, and second will form the lower live part of this output.First source will be moved to left so that its bit aligns with correct outgoing position, and second source will be moved to right.For each bit in byte, select the mask in a source or another source to there is identical value, therefore it can be designated as the vector of 4 bits, and corresponding 1 bit of each byte, as #b1110, this means binary one 110.The explanation of each mask bit is: if it is 1, select first source, and if it is 0, select second source.These operations can be accorded with representing by displacement and mask operation.Using shift operation symbol syntax is (shifted data shift amount), wherein data are words of 32 bits, shift amount is taking byte as unit, and shift operation symbol is shlb (byte of the some that moves to left) and shrb (byte of the some that moves to right).Mask operation symbol syntax is (1 source 2, mask mask value source), and wherein, for the numeral of these 32 bits, mask value is 4 bit widths, and these two sources are 32 bit widths.Displacement and mask operation for the calculating of each PL have functionally been described in table 6:
Table 6: displacement and mask operation
Generally speaking, DO symbol or zero expansion on one end of Input Data word or the other end that move to left or move to right.This is complicated is unnecessary because displacement after, do not have zero or sign extended bit selected by mask.So can replace this displacement: rotlb (byte of ring shift left some) or rotrb (byte of ring shift right some) by more simply rotating operation, as shown in table 7:
Table 7: rotation and mask operation
Finally, will be appreciated that, 32 bit source ring shift lefts rotation counting bitwise is identical with poor (mould 32) that this source ring shift right 32 deducted to this rotation counting, or ground of equal value, the rotation counting of 32 bit source ring shift lefts taking byte as unit is identical with poor (mould 4) that this source ring shift right 4 deducted to this byte rotation counting.All spinfunctions can be changed on single direction rotates, as shown in table 8:
Table 8: dextrorotation and mask function
This embodiment of the present invention is called as byte rotation and merges (byte-rotate-merge).After the description of the second creative instruction that general bit operating ability is provided, will the hardware cost of this instruction be discussed.
As byte, rotation merges a kind of alternate embodiments of embodiment, will be recognized that: if two source operands be equal to interchangeable, that is two operands can both derive from identical input, the first source can be used as the source of exporting to higher effective half, the second source can be used as the source of exporting to lower effective half, and in those situations, in order to generate IPV4 address, mask constant will be multiple 1 in higher live part all the time, after and then multiple 0 in lower live part.Then mask constant alternatively can be encoded into dibit as minimum effective 1 position.For generality, also may have with multiple higher effective 0 and higher effective 1 mask, and alternatively this mask constant is encoded to minimum effective zero position.These two kinds of methods are logically equivalent, so can be regarded as identical method.Equivalence is that this mask is encoded to the multiple least significant bytes from same source therewith.
The second embodiment of the present invention will be discussed now.It is very common that processor has an extraction instruction, and the computing of describing is before implemented as extraction by it; It obtains specific fields from a complete word, and this specific fields is shifted downward to bit position zero, and removes (or sign extended) all bits higher than its definition length, as shown in Figure 1A.For example, the sig<23:16> extracting from 32 bit signal sig<31:0> carries out by the following: by these signal right shift 16 bits, and all bits that make zero on field length, field length is 8 bits (from 23 to 16) in this case, so the bit 31 to 8 that makes zero.Be described to a function (extracting data word lobit (low step bit) length) if extracted, data right shift lobit, and all bits except the low bit of < length > all make zero (or sign extended).For example, (extracting #x12345678168) is #x34, i.e. the bit <23:16> of source data.
Second prior art instruction is to deposit byte, and wherein the low step bit of the first source operand is replaced the field of second (backstage) source operand, as shown in Figure 1B.The field that will be replaced in second operand is defined by higher bit H and low bit L, and the bit of replacing this field is the lsb of first operand.This field has width H-L+1.Of equal value with low bit and length coding instead of higher bit and low bits of encoded.Be (depositing byte source data back-end data position length) if deposit the syntax of byte instruction, (depositing byte #x12345678#xbbbbbbbb168) is #xbb78bbbb; Low 8 bits of the first source operand #x12345678 have been replaced the bit <23:16> of second (backstage) operand xbbbbbbbb.
The second embodiment of the present invention provides more powerful and bit operating ability arbitrarily.Extract instruction and can from source operand, obtain any length field in any position, and be moved down into the bit 0 in result, as shown in Figure 1A.Deposit byte instruction can be in consistency operation number any position obtain the aiming field of any length, and replaced with the low step bit of source operand, as shown in Figure 1B.One embodiment of the present of invention provide one to deposit field instruction, and this deposits field instruction can obtain any length field in any position from source operand, and it is deposited to any position in consistency operation number, as shown in Figure 1 C.
Except source data operation number and back-end data operand, this deposits field instruction also needs three shifted constants: source position, target location and length.The replaceable coding of three shifted constants is possible and equivalence, for example, uses source position, target location and target higher bit.This instruction is different from traditional extraction and deposits byte instruction, traditional extraction and deposit byte instruction and only need two shifted constants: position and length.This is deposited field instruction a kind of more general ability is provided, in order to from extracting Anywhere field and being deposited anywhere.In the situation that lacking this instruction, this general operation will need two instructions, that is and, load byte (load-byte) instruction heel and deposit byte instruction, the field that wherein the first instruction fetch will be deposited, the second instruction is deposited this field in the word of backstage.In the situation that not depositing field instruction, 4 operations of table 8 and rotation and mask function are described will all need two operations instead of one (except PL56, one of them rotation counting is 0, and one is deposited byte instruction and can complete).
Compared with depositing byte instruction with routine, this is deposited field instruction and can realize by minimum extra cost.Routine is deposited byte hardware 200 shown in Fig. 2 A.Circulator circuit 204 is by the value of source data 201 ring shift lefts (ROTL) source position independent variable 202.Select circulator data 214 instead of back-end data 215 by multiplexer (MUX) 210, wherein each bit of multiplexer 210 is independently controlled (selecting by bit).Select circulator data 214 by enable signal 216.This enable signal 216 is to produce by respectively the result 218 and 220 of two Thermometer-decoder (TH) 206 and 208 being carried out to AND functions 212, one of them Thermometer-decoder enables from source position and the bit of high position more, and another Thermometer-decoder enables from target location+length-1 and the bit of lower position more.The output of multiplexer 210 is nodes 209.
Fig. 2 B shows according to embodiments of the invention and realizes and deposit the required hardware of field instruction 222.Circulator counting changes to new rotation independent variable ROT from source position independent variable 202.This ROT independent variable equals target location and deducts source position (for the circulator with rotation counting independent variable ring shift left).Note, because all shifted constants are only constants, they can reduce complexity with interchangeable coding, should be realized that three 5 bit constants of final needs.Can specify rotation counting, the second target location and three position+length.As a result, increase without hardware or deduct shifted constant.For depositing field instruction, without the extra data path hardware more than depositing byte instruction, and unique change is, this circulator is controlled by new additional independent variable ROT.
The extra cost of execution byte rotation merge command can be deposited field schematic diagram by the simplification of inspection Fig. 3 A and be understood.The control logic of the control signal 216 of multiplexer 210 has been integrated in mask piece 302 herein, and the result of two Thermometer-decoder 218 and 220 is fed in mask piece 302.Fig. 3 B also shows and carries out the needed enhancing of byte rotation merging.Now back-end data 215 has the byte circulator 312 between it and multiplexer 210.Mask piece 302 has extra input byte mask 310, and it is controlled multiplexer 210 and selects byte rotation merge command based on each byte.Output 209 in Fig. 3 B is that byte rotation merges output.4 input multiplexers of for example 32 bits of byte circulator 312 are main additional firmware, and byte circulator 312 is controlled mask piece 302 together with some little additional logic.Note, additional circulator 312 is byte circulators, only rotate 0 bit, 8 bits, 16 bits or 24 bits, and the circulator of preexist can rotate the position of all 32 bits.
For the object that illustrates and describe, show description above.It is not intended to be limit or limit the invention to disclosed precise forms, and be possible according to the other modifications and variations of above-mentioned instruction.Selecting and describing these embodiment is in order to explain best applicable principle and practical application thereof, thereby makes those skilled in the art can utilize best various embodiment and the various amendments that are suitable for the special-purpose of expecting.Be intended to claims to be interpreted as comprising other optional embodiments, except by prior art limited range.
Claims (8)
1. for carry out a method for byte rotation merge command on computer hardware, it comprises:
Receive the first source operand and the second source operand;
Described the first source operand is obtained to the first byte rotation output by byte rotation by multiple bytes of the first rotation constant appointment;
Described the second source operand is obtained to the second byte rotation output by byte rotation by multiple bytes of the second rotation constant appointment;
Described the first byte rotation output and described the second byte rotation output are combined and create byte rotation and merge output, wherein said byte rotation merges output packet and draws together multiple bytes, and the each byte in wherein said multiple bytes has the corresponding control bit from byte mask;
When from the corresponding control bit of described byte mask being logic a period of time, for each byte that described byte rotation merges in output selects described the first byte rotation to export;
In the time being logical zero from the corresponding control bit of described byte mask, for each byte that described byte rotation merges in output is selected described the second byte rotation output.
2. method according to claim 1, wherein said byte rotation mask is encoded as the quantity of the output byte of the operand that derives from supply low order byte.
3. on computer hardware, carry out a method of depositing field instruction, it comprises:
Reception sources operand and consistency operation number;
Use from the designated length of assigned address in described source operand and replace the assigned address in described consistency operation number, wherein said replacement is determined by the first shifted constant, the second shifted constant and the 3rd shifted constant.
4. method according to claim 3, wherein said the first shifted constant assigned source rotation, described the second shifted constant is specified the minimum effective bit border of the described consistency operation number of being revised by described source operand, and described the 3rd shifted constant is specified the highest significant bit border of the described consistency operation number of being revised by described source operand.
5. on computer hardware, carry out a method of depositing field instruction, it comprises:
Reception sources operand and consistency operation number;
Receiving target position independent variable, source position independent variable and length independent variable;
Described source operand rotation ROT independent variable is obtained to byte rotation output, and wherein said ROT independent variable equals described target location independent variable and deducts described source position independent variable;
Described source position independent variable is applied to the first Thermometer-decoder, and the output enable of wherein said the first thermometer is from the bit of He Geng high position, source position;
Described target location is added to the above size operand and be applied to the second thermometer, the output enable of wherein said the second thermometer adds the above size operand and downward bit from target location;
The output of the output of described the first thermometer and described the second thermometer is applied to AND door, the output control multiplexer of wherein said AND.
6. for carry out a device for byte rotation merge command on computer hardware, comprising:
The first rotation circuit, it can operate to the first source operand is obtained to the first byte rotation output by byte rotation by multiple bytes of the first rotation constant appointment;
The second rotation circuit, it can operate to the second source operand is obtained to the first byte rotation output by byte rotation by multiple bytes of the second rotation constant appointment;
Byte mask, the output of wherein said byte mask is used to determine that byte rotation merges output;
Multiplexer, it receives, and described the first byte is rotated output and described byte rotation merging output is exported and exported in described the second byte rotation, wherein said byte rotation merges output packet and draws together multiple bytes, and the each byte in wherein said multiple bytes has the corresponding control bit from described byte mask;
Wherein, when the output of byte mask is logic a period of time, be presented on described byte rotation merging from the byte of described the first byte rotation output and export;
Wherein, in the time that the output of byte mask is logical zero, is presented on described byte rotation from the byte of described the second byte rotation output and merges in output.
7. device according to claim 6, wherein said byte rotation mask is encoded as the quantity of the output byte of the operand that derives from supply low order byte.
8. for carry out a device of depositing field instruction on computer hardware, it comprises:
The first rotation circuit, it can operate to source operand is rotated to ROT independent variable by byte, and wherein said ROT independent variable equals target location independent variable and deducts source position independent variable;
Receive the first thermometer of described source position independent variable;
Receive the second thermometer that described target location independent variable adds size operand;
AND door, it receives from the output of described the first thermometer with from the output of described the second thermometer;
Multiplexer, it receives output and the consistency operation number of the output of described AND door, described the first rotation circuit;
Wherein, the output of described the first thermometer makes can be presented in the output of described multiplexer from the bit of He Geng high position, described source position;
Wherein, the output of described the second thermometer make from described target location add the above size operand and more the bit of lower position can be presented in the output of described multiplexer.
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| Application Number | Priority Date | Filing Date | Title |
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| US201361759661P | 2013-02-01 | 2013-02-01 | |
| US61/759,661 | 2013-02-01 | ||
| US14/025,177 | 2013-09-12 | ||
| US14/025,177 US9313127B2 (en) | 2013-02-01 | 2013-09-12 | Rotate-mask-merge and deposit-field instructions for packet processing |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110290221A (en) * | 2019-07-09 | 2019-09-27 | 中星科源(北京)信息技术有限公司 | A kind of original address transmission method, system, storage medium and processor |
| CN110324437A (en) * | 2019-07-09 | 2019-10-11 | 中星科源(北京)信息技术有限公司 | A kind of original address transmission method, system, storage medium and processor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5781457A (en) * | 1994-03-08 | 1998-07-14 | Exponential Technology, Inc. | Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU |
| CN1846194A (en) * | 2003-08-28 | 2006-10-11 | 美普思科技有限公司 | Integrated mechanism for suspension and deallocation of computational threads of execution in a processor |
| CN101627365A (en) * | 2006-11-14 | 2010-01-13 | 索夫特机械公司 | Apparatus and method for processing complex instruction formats in a multi-threaded architecture supporting various context switch modes and virtualization schemes |
| US20120131312A1 (en) * | 2010-11-23 | 2012-05-24 | Arm Limited | Data processing apparatus and method |
-
2014
- 2014-01-29 CN CN201410076291.2A patent/CN103973600B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5781457A (en) * | 1994-03-08 | 1998-07-14 | Exponential Technology, Inc. | Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU |
| CN1846194A (en) * | 2003-08-28 | 2006-10-11 | 美普思科技有限公司 | Integrated mechanism for suspension and deallocation of computational threads of execution in a processor |
| CN101627365A (en) * | 2006-11-14 | 2010-01-13 | 索夫特机械公司 | Apparatus and method for processing complex instruction formats in a multi-threaded architecture supporting various context switch modes and virtualization schemes |
| US20120131312A1 (en) * | 2010-11-23 | 2012-05-24 | Arm Limited | Data processing apparatus and method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110290221A (en) * | 2019-07-09 | 2019-09-27 | 中星科源(北京)信息技术有限公司 | A kind of original address transmission method, system, storage medium and processor |
| CN110324437A (en) * | 2019-07-09 | 2019-10-11 | 中星科源(北京)信息技术有限公司 | A kind of original address transmission method, system, storage medium and processor |
| CN110324437B (en) * | 2019-07-09 | 2020-08-21 | 中星科源(北京)信息技术有限公司 | Original address transmission method, system, storage medium and processor |
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