CN103973247A - Rail-to-rail differential input circuit - Google Patents

Abstract

The invention discloses a rail-to-rail differential input circuit which comprises a PMOS differential pair, an NMOS differential pair, a PMOS switch tube, an NMOS switch tube, a PMOS current source, an NMOS current source, a PMOS current mirror and an NMOS current mirror. The currents output by the PMOS current source and the NMOS current source are equal, and the PMOS current source comprises a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor and the second PMOS transistor form a cascade structure. The NMOS current source comprises a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor and the second NMOS transistor form a cascade structure. According to the rail-to-rail differential input circuit, the tail current precision can be improved, and the better constant transconductance effect can be achieved.

Description

Rail-to-rail Differential input circuit

Technical field

The present invention relates to operational amplifier, particularly the rail-to-rail differential input stage circuit in operation amplifier circuit.

Background technology

At rail-to-rail operational amplifier (rail to rail operational amplifier, Rail-to-Rail OPAMP) in design, require input stage from power supply electronegative potential to high potential, in rail-to-rail voltage range, there is the function (constanttransconductance) of constant transconductance.Yet the input of independent PMOS or nmos differential is to will be in cut-off, subthreshold value, linearity and saturated four working regions in full voltage range, its mutual conductance changes, can be by the zero maximum that be changed to.

Due to PMOS differential pair under low-voltage in saturation region, and under high voltage in cut-off region; Nmos differential is to just the opposite, its under high voltage in saturation region, under low-voltage in cut-off region.According to this characteristic, make nmos differential pair in parallel with PMOS differential pair during as input stage, in the time of the cut-off of the right transistor of nmos differential, the transistor of PMOS differential pair is opened, or the right transistor of nmos differential is opened when the cut-off of the transistor of PMOS differential pair; Therefore the mutual conductance perseverance of circuit is greater than zero.On the other hand, at input voltage during in high or low level, input stage only have nmos differential to or PMOS differential pair open, total mutual conductance of circuit is:

$G_{m,\mathrm{total}}|\mathrm{Highlevelinputvoltage}=G_{m,\mathrm{NMOS}}=\sqrt{k_N*I_{d,\mathrm{NMOS}}}---\left(1\right)$ Or

$G_{m,\mathrm{total}}|\mathrm{Lowlevelinputvoltage}=G_{m,\mathrm{PMOS}}=\sqrt{k_P*I_{d,\mathrm{PMOS}}}---\left(2\right)$

K wherein _nand K _pfor proportionality coefficient, can, by adjusting device size and electrical parameter, it be equated; I _{d, NMOS}and I _{d, PMOS}be respectively nmos differential to the drain-source current with PMOS differential pair.Suppose parameter k and I _d, make to exist following relation:

k _N＝k _P＝k，I _d，NMOS＝I _d，PMOS＝I _d(3)

, when input voltage is high and low level, circuit mutual conductance is constant.

When input voltage is when compared with median, make PMOS differential pair and nmos differential to all opening and when the saturation region, the now mutual conductance of circuit is:

$G_{m,\mathrm{total}}|\mathrm{Middlelevelinputvoltage}=G_{m,\mathrm{NMOS}}+G_{m,\mathrm{PMOS}}=2\sqrt{k*I_d}---\left(4\right)$

This numerical value is the twice when input voltage is high or low level.Therefore,, in the input range of full voltage, difference input is not steady state value to the mutual conductance of pipe.

In prior art, for realizing constant transconductance, by change difference, input right transistorized tail current and make its mutual conductance constant under different input voltages.As shown in Figure 1, PM1, PM2 pipe is inputted right transistor for PMOS difference to its schematic diagram, and its grid receives differential input signal V _iNand V _iP, NM1, NM2 pipe is inputted right transistor for nmos differential, and grid also receives respectively differential input signal V _iNand V _iP; I _{tail, NMOS}and I _{tail, PMOS}be respectively nmos differential input to inputting right tail current source with PMOS difference, and regulating circuit parameter makes:

I _tail，NMOS＝I _tail，PMOS＝I _tail(5)

NM3 and PM3 pipe are switching transistor, and its gate voltage is respectively V _bIASNand V _bIASP; Module 3XCM_N and 3XCM_P are respectively the current-mirror structure of 1:3 and 3:1, by the leakage current of transistor NM3 and PM3 being amplified to 3 times, input to nmos differential input to inputting right source electrode with PMOS difference.

Its specific works principle is as described below:

Input voltage is in rail-to-rail voltage range time, thereby change the input of PMOS difference, to inputting right tail current with nmos differential, its drain current changed its mutual conductance is changed.V wherein _aand V _bbe respectively the voltage of A node and B node; V _thNand V _thPbe respectively nmos differential input to inputting right threshold voltage with PMOS difference.

1. as 0≤V _in< V _thN+ V _btime, nmos differential input is in cut-off region, and the input of PMOS difference is in saturation region.Input right total mutual conductance G _{m, tetal}for:

$G_{m,\mathrm{total}}=G_{m,\mathrm{NMOS}}+G_{m,\mathrm{PMOS}}\&ap;G_{m,\mathrm{PMOS}}=\sqrt{k*{4I}_{\mathrm{tail}}}=2\sqrt{k*I_{\mathrm{tail}}}---\left(6\right)$

2. work as V _a+ | V _thP|≤V _in< V _dDtime, PMOS difference input is in cut-off region, and nmos differential is inputted in saturation region, inputs right total mutual conductance G _{m, total}for:

$G_{m,\mathrm{total}}=G_{m,\mathrm{NMOS}}+G_{m,\mathrm{PMOS}}\&ap;G_{m,\mathrm{NMOS}}=\sqrt{k*{4I}_{\mathrm{tail}}}=2\sqrt{k*I_{\mathrm{tail}}}---\left(7\right)$

3. work as V _thN+ V _b< V _in< V _a+ | V _thP| time, PMOS, nmos differential are inputted all opening, and now input right total mutual conductance G _{m, total}for:

G _m，total＝G _m，NMOS+G _m，PMOS(8)

Due to I _{d, NMOS}with V _inincrease and I when increasing _{d, PMOS}reducing, so the variable quantity of its square root sum is less.Special when PMOS, nmos differential, input when all in saturation region, size is:

$G_{m,\mathrm{total}}=G_{m,\mathrm{NMOS}}+G_{m,\mathrm{PMOS}}\&ap;G_{m,\mathrm{NMOS}}=\sqrt{k*{4I}_{\mathrm{tail}}}=2\sqrt{k*I_{\mathrm{tail}}}---\left(7\right)$

Now realized input difference constant to the mutual conductance at full voltage range, 3 times of principles that current mirror mutual conductance is constant that Here it is.

Fig. 2 provides a kind of circuit diagram of realizing above-mentioned principle, wherein using NM4 and PM4 pipe respectively as nmos differential input to inputting right tail current source with PMOS difference; NM3 and PM3 are still switching transistor; NM5, NM6 pipe forms 3 times of current mirror module 3XCM_N, and PM5, PM6 pipe forms 3 times of current mirror module 3XCM_P.

Yet, in the circuit structure shown in Fig. 2, with PM4 or the such MOSFET of NM4, do current source, its current value changes greatly with the variation of its drain-source voltage, causes current precision to decline.This is that making its electric current when saturation region is not that " completely " is saturated because device exists channel-length modulation, but slightly increases along with the increase of its drain-source voltage.And in the situation that full voltage is inputted, this variation is large especially.Because the electric current of PM4 or NM4 is to input right tail current as difference, its square root is directly proportional to transistorized mutual conductance to difference input, and therefore, the variation of current source current will cause the larger variation of input stage mutual conductance under full voltage.In addition,, in 3 times of current mirror module 3XCM_N, 3XCM_P, the output current of this basic current-mirror structure also can change greatly with the variation of the drain voltage of efferent duct, the precision of the current mirror that declined.

Summary of the invention

Main purpose of the present invention is to overcome the defect of prior art, to improve operational amplifier input stage difference, inputs the right constant level that is cross over.

The present invention adopts following technical scheme: a kind of rail-to-rail Differential input circuit, comprise that PMOS differential pair transistors (PM1, PM2) and nmos differential are to transistor (NM1, NM2), and its grid receives differential input signal; PMOS switching transistor (PM3) and nmos switch transistor (NM3); PMOS current source and NMOS current source; And PMOS current mirror and NMOS current mirror, be three times of current mirrors.Wherein, the source electrode of described PMOS differential pair transistors (PM1, PM2) is connected with the output of described PMOS current source with the source electrode of described PMOS switching transistor (PM3), the output of described PMOS current mirror; Described nmos differential is connected with the output of described NMOS current source with the source electrode of described nmos switch transistor (NM3), the output of described NMOS current mirror to the source electrode of transistor (NM1, NM2).Wherein, the electric current of described PMOS current source and the output of NMOS current source is equal, and described PMOS current source comprises a PMOS transistor (PM4) and the 2nd PMOS transistor (PM7) that forms cascodes; Described NMOS current source comprises the first nmos pass transistor (NM4) and the second nmos pass transistor (NM7) that forms cascodes.

The preferred a kind of technical scheme of the present invention, described PMOS current mirror is common-source common-gate current mirror, it comprises the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor and the 6th PMOS transistor (PM5, PM6, PM8, PM9), described the third and fourth PMOS transistor (PM5, PM6) source electrode is connected to power supply jointly, grid is connected to the drain electrode of described the 4th PMOS transistor (PM6) jointly, drain electrode respectively with the described the 5th and the 6th PMOS transistor (PM8, PM9) source electrode joins, the the described the 5th and the 6th PMOS transistor (PM8, PM9) grid is jointly connected to the drain electrode of described the 6th PMOS transistor (PM9) and is connected with the drain electrode of described nmos switch transistor (NM3), the drain electrode of described the 5th PMOS transistor (PM8) is as the output of described PMOS current mirror.Described NMOS current mirror is common-source common-gate current mirror, it comprises the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor (NM5, NM6, NM8, NM9), described the third and fourth nmos pass transistor (NM5, NM6) source electrode common ground, grid is connected to the drain electrode of described the 4th nmos pass transistor (NM6) jointly, drain electrode respectively with the described the 5th and the 6th nmos pass transistor (NM8, NM9) source electrode joins, the the described the 5th and the 6th nmos pass transistor (NM8, NM9) grid is jointly connected to the drain electrode of described the 6th nmos pass transistor (NM9) and is connected with the drain electrode of described PMOS switching transistor (PM3), the drain electrode of described the 5th nmos pass transistor (NM8) is as the output of described NMOS current mirror.

The preferred a kind of technical scheme of the present invention, a described PMOS transistor (PM4) is operated in saturation region, and described the first nmos pass transistor (NM4) is operated in saturation region.

The preferred a kind of technical scheme of the present invention, described the 2nd PMOS transistor (PM7) is operated in saturation region, and described the second nmos pass transistor (NM7) is operated in saturation region.

The preferred a kind of technical scheme of the present invention, the source electrode of a described PMOS transistor (PM4) is connected to power supply, and grid is provided the first bias voltage, and drain electrode connects the source electrode of described the 2nd PMOS transistor (PM7); The grid of described the 2nd PMOS transistor (PM7) is provided the second bias voltage, and drain electrode is as the output of described PMOS current source.The source ground of described the first nmos pass transistor (NM4), grid is provided the 3rd bias voltage, and drain electrode connects the source electrode of described the second nmos pass transistor (NM7); The grid of described the second nmos pass transistor (NM7) is provided the 4th bias voltage, and drain electrode is as the output of described NMOS current source.

The preferred a kind of technical scheme of the present invention, the breadth length ratio of described the 3rd PMOS transistor (PM5) is three times of breadth length ratio of described the 4th PMOS transistor (PM6), and the breadth length ratio of described the 5th PMOS transistor (PM8) is three times of breadth length ratio of described the 6th PMOS transistor (PM9); The breadth length ratio of described the 3rd nmos pass transistor (NM5) is three times of breadth length ratio of described the 4th nmos pass transistor (NM6), and the breadth length ratio of described the 5th nmos pass transistor (NM8) is three times of breadth length ratio of described the 6th nmos pass transistor (NM9).

The preferred a kind of technical scheme of the present invention, the grid of described nmos switch transistor (NM3) is provided the 5th bias voltage, and the grid of described PMOS switching transistor (PM3) is provided the 6th bias voltage.

The present invention also provides a kind of operation amplifier circuit, and it comprises above-mentioned rail-to-rail Differential input circuit and output circuit.

Compared with prior art, rail-to-rail Differential input circuit of the present invention has adopted the current source with cascodes, using the transistor of common source configuration as supervisor, transistor with common gate structure increases resistance in current source, thereby obtain larger output resistance, improve the carrying load ability of current source, thus in the situation that current source both end voltage has identical variable quantity, the current source of cascodes has less current change quantity, weakened the transistorized short channel mudulation effect of current source in prior art, improved the precision of tail current, and then reduce the variable quantity of input difference to mutual conductance in full voltage range, can more stably reach the constant effect of mutual conductance.

Accompanying drawing explanation

Fig. 1 is the schematic diagram that the rail-to-rail Differential input circuit of prior art adopts three times of current-mirror structure.

Fig. 2 is the circuit diagram of the rail-to-rail Differential input circuit of prior art.

Fig. 3 is the circuit diagram of the rail-to-rail Differential input circuit of one embodiment of the invention.

Fig. 4 a and Fig. 4 b are the circuit diagrams of the current source part of prior art and rail-to-rail Differential input circuit of the present invention.

Embodiment

For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.

In this manual and in claims, should understand and be called as when ' attach ' to another element or " being connected " with another element when an element, it can be directly connected to another element, maybe can have intervention element.

Fig. 3 is the circuit diagram of the rail-to-rail Differential input circuit of one embodiment of the invention, and this rail-to-rail Differential input circuit can be used as the input stage of operational amplifier, as is applied in the rail-to-rail operational amplifier in 55nm CMOS technique.As shown in the figure, rail-to-rail Differential input circuit comprises PMOS differential pair transistors PM1 and PM2, and nmos differential is to transistor NM1 and NM2, PMOS switching transistor PM3 and nmos switch transistor NM3, and PMOS current source Itail, _pMOSwith NMOS current source Itail, _nMOS, PMOS current mirror 3XCM_P and NMOS current mirror 3XCM_N.The transistorized substrate lead NWL of each PMOS connects high potential, and the substrate lead PWL of each nmos pass transistor connects electronegative potential, to guarantee that transistor can normally work.

The transistor PM1 of PMOS differential pair and PM2 have identical length and width size, and the transistor NM1 that nmos differential is right and NM2 have identical length and width size.The right grid of PMOS differential pair and nmos differential receives differential input signal, and concrete transistor PM1 and the grid of NM1 receive input voltage V _iN, the grid of transistor PM2 and NM2 receives input voltage V _iP.

Transistor PM3 and NM3 are switching tube, respectively by bias voltage V _bIAS6and V _bIAS5control.Concrete, the source electrode of transistor PM3 and PMOS differential pair transistors PM1, the source electrode of PM2 is connected, and grid meets bias voltage V _bIAS6, drain electrode is connected with the input of NMOS current mirror.The source electrode of switching transistor NM3 and nmos differential are to transistor NM1, and the source electrode of NM2 is connected, and grid meets bias voltage V _bIAS5, drain electrode is connected with the input of PMOS current mirror.

PMOS current source Itail, _pMOSoutput and PMOS differential pair transistors PM1, the source electrode of the source electrode of PM2 and switching tube PM3 is connected.NMOS current source Itail, _nMOSoutput and nmos differential to transistor NM1, the source electrode of the source electrode of NM2 and switching tube NM3 is connected.Current source Itail, _pMOSwith current source Itail, _nMOSthe electric current providing equates.

NMOS current mirror 3XCM_N and PMOS current mirror 3XCM_P are three times of current mirrors, and input is connected with the drain electrode of switching tube PM3 and NM3 respectively, and the output respectively source electrode right with nmos differential is connected with the source electrode of PMOS differential pair.Current mirror 3XCM_P is NMOS current source Itail, _nMOSthe electric current of output arrives the source electrode of PMOS differential pair with the scaled mirror of 1:3, make the tail current in PMOS differential pair increase to original 4 times.Current mirror 3XCM_N is by PMOS current source Itail, and the electric current of PMOS arrives the right source electrode of nmos differential with the scaled mirror of 1:3, makes the tail current of nmos differential centering also increase to original 4 times.When differential pair transistors is from being opened to the process of shutoff, B point current potential V _breduce, as the V of switching tube NM3 pipe _gsincrease to V _gs>=V _thNtime, NM3 pipe is opened so that whole 3 times of current mirror 3XCM_P open, firing current mirror 3XCM_N in like manner, make nmos differential to PMOS differential pair complementary output electric current, thereby realize nmos differential to PMOS differential pair in full voltage range be cross over constant.

Further, in order to improve the variation of the current source current value that the variation of B point or A point current potential brings, the present invention is improved current source structure.As shown in the figure, current source Itail in the present embodiment, _pMOSand Itail, _nMOSbe cascode current source, concrete NMOS current source Itail, _nMOScomprise two the nmos pass transistor NM4 and the NM7 that form cascodes, PMOS current source Itail, _pMOScomprise two the PMOS transistor PM4 and the PM7 that form cascodes.The source ground GND of transistor NM4, grid are provided the 3rd bias voltage V _bIAS3, drain electrode is connected with the source electrode of transistor NM7.The grid of transistor NM7 is provided the 4th bias voltage V _bIAS4, drain as NMOS current source Itail, _nMOSoutput with nmos differential, the source electrode of NM1 and NM2 is connected.The source electrode of transistor PM4 is connected to power vd D, grid is provided the first bias voltage V _bIAS1, drain electrode is connected with the source electrode of transistor PM7.The grid of transistor PM7 is provided the second bias voltage VBIAS2, drains as PMOS current source Itail, _pMOSoutput be connected with the source electrode of PMOS differential pair PM1 and PM2.By to bias voltage V _bIAS1and V _bIAS3and the adjusting of transistor PM4 and NM4 size, the drain current of transistor PM4 and NM4 is equated, thereby meets current source Itail, _pMOSand Itail, _nMOSequal electric current is provided.In addition, by the adjusting to each transistor size and bias voltage, the output of differential pair is met:

(iout-n-) _max＝(iout-n+) _max＝(iout-P-) _max＝(iout-p+) _max

With NMOS current source Itail, _nMOSfor example, NM4 pipe is as the current source Itail of cascodes, _nMOSsupervisor, must operate at saturation region, the effect of NM7 pipe is in order to increase the interior resistance of current source I2, improves current source Itail, _nMOScarrying load ability.

Fig. 4 a is depicted as the NMOS current source part of rail-to-rail Differential input circuit of 3 times of current mirror constant transconductances of prior art, only usings NM4 pipe as current source, and it is operated in saturation region, and output resistance is:

R _out＝r _o，NM4(10)

Fig. 4 b is the NMOS current source part of Differential input circuit in the present embodiment, and the output resistance in NMOS cascode current source is:

When NM7 pipe is operated in saturation region:

R _out＝r _o，NM4+r _o，NM7+(g _m，NM7+g _mb，NM7)r _o，NM4r _o，NM7(11)

When NM7 manages work in linear zone:

NM7 pipe is equivalent to a resistance, and its resistance value is:

$R_{\mathrm{out},\mathrm{NM}7}={\left(\frac{W}{L}\right)}_{\mathrm{NM}7}{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}(V_{\mathrm{gs},\mathrm{NM}7}-V_{\mathrm{thN}})---\left(12\right)$

Now, NMOS cascode current source output resistance is:

$R_{\mathrm{out}}=r_{o,\mathrm{NM}4}+{\left(\frac{W}{L}\right)}_{\mathrm{NM}7}{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}(V_{\mathrm{gs},\mathrm{NM}7}-V_{\mathrm{thN}})---\left(13\right)$

Therefore, when NM7 pipe is operated in saturation region, current source output resistance obviously increases, and NM7 manages work when linear zone, and current source output resistance also increases to some extent.In order to obtain large interior resistance, by bias voltage V _bIAS4and the adjusting of transistor NM7 size, make NM7 pipe work in saturation region as far as possible.

The operation principle of PMOS current source is consistent with NMOS current source, no longer describes in detail.

Comprehensive the above, cascode current source has compared with the single tube current source of prior art and has larger output resistance, therefore its carrying load ability is stronger, in current source both end voltage, have under identical variable quantity, cascode current source has less current change quantity, can improve current precision thus.

Further, in the present embodiment, current mirror has also been adopted to cascodes.As shown in Figure 3, PMOS current mirror 3XCM_P is common-source common-gate current mirror, and it comprises PMOS transistor PM5, PM6, PM8 and PM9.The source electrode of transistor PM5 and PM6 is connected to the drain electrode that power vd D, grid are connected to PM6 pipe jointly jointly.The source electrode of the drain electrode of PM5 pipe and PM8 pipe joins, and the source electrode of the drain electrode of PM6 pipe and PM9 pipe joins.PM8 pipe is jointly connected to the drain electrode of PM9 pipe and is connected with the drain electrode of switching transistor NM3 with the grid of PM9 pipe, and the drain electrode of PM8 pipe is as the output of PMOS current mirror.Similar, NMOS current mirror 3XCM_N comprises nmos pass transistor NM5, NM6, NM8 and NM9.The source electrode common ground GND of NM5 pipe and NM6 pipe, the drain electrode that grid is connected to NM6 pipe jointly, drain electrode are joined with the source electrode of NM8 pipe and NM9 pipe respectively.NM8 pipe is jointly connected to the drain electrode of NM9 pipe and is connected with the drain electrode of switching transistor PM3 with the grid of NM9 pipe, and the drain electrode of NM8 pipe is as the output of NMOS current mirror.Wherein, the breadth length ratio of PM5 pipe is 3 glasss of breadth length ratio of PM6 pipe, and the breadth length ratio of PM8 pipe is 3 times of PM9 pipe; The breadth length ratio of NM5 pipe is 3 times of NM6 pipe, and the breadth length ratio of NM8 pipe is 3 times of NM9 pipe, to realize 3 times of amplifications of electric current.By adopting common-source common-gate current mirror structure, also can improve the output current of basic current mirror structure in prior art can be along with the variation of B point current potential marked change and cause the defect of current mirror output current precise decreasing.

Although the present invention discloses as above with preferred embodiment; so described many embodiment only give an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.

Claims (8)

1. a rail-to-rail Differential input circuit, is characterized in that, comprising:

PMOS differential pair transistors (PM1, PM2) and nmos differential are to transistor (NM1, NM2), and its grid receives differential input signal;

PMOS switching transistor (PM3) and nmos switch transistor (NM3);

PMOS current source and NMOS current source; And

PMOS current mirror and NMOS current mirror, be three times of current mirrors;

Wherein, the source electrode of described PMOS differential pair transistors (PM1, PM2) is connected with the output of described PMOS current source with the source electrode of described PMOS switching transistor (PM3), the output of described PMOS current mirror; Described nmos differential is connected with the output of described NMOS current source with the source electrode of described nmos switch transistor (NM3), the output of described NMOS current mirror to the source electrode of transistor (NM1, NM2),

Wherein, the electric current of described PMOS current source and the output of NMOS current source is equal, and described PMOS current source comprises a PMOS transistor (PM4) and the 2nd PMOS transistor (PM7) that forms cascodes; Described NMOS current source comprises the first nmos pass transistor (NM4) and the second nmos pass transistor (NM7) that forms cascodes.

2. rail-to-rail Differential input circuit as claimed in claim 1, is characterized in that,

Described PMOS current mirror is common-source common-gate current mirror, it comprises the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor and the 6th PMOS transistor (PM5, PM6, PM8, PM9), described the third and fourth PMOS transistor (PM5, PM6) source electrode is connected to power supply jointly, grid is connected to the drain electrode of described the 4th PMOS transistor (PM6) jointly, drain electrode respectively with the described the 5th and the 6th PMOS transistor (PM8, PM9) source electrode joins, the the described the 5th and the 6th PMOS transistor (PM8, PM9) grid is jointly connected to the drain electrode of described the 6th PMOS transistor (PM9) and is connected with the drain electrode of described nmos switch transistor (NM3), the drain electrode of described the 5th PMOS transistor (PM8) is as the output of described PMOS current mirror,

Described NMOS current mirror is common-source common-gate current mirror, it comprises the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor (NM5, NM6, NM8, NM9), described the third and fourth nmos pass transistor (NM5, NM6) source electrode common ground, grid is connected to the drain electrode of described the 4th nmos pass transistor (NM6) jointly, drain electrode respectively with the described the 5th and the 6th nmos pass transistor (NM8, NM9) source electrode joins, the the described the 5th and the 6th nmos pass transistor (NM8, NM9) grid is jointly connected to the drain electrode of described the 6th nmos pass transistor (NM9) and is connected with the drain electrode of described PMOS switching transistor (PM3), the drain electrode of described the 5th nmos pass transistor (NM8) is as the output of described NMOS current mirror.

3. rail-to-rail Differential input circuit as claimed in claim 1, is characterized in that, a described PMOS transistor (PM4) is operated in saturation region, and described the first nmos pass transistor (NM4) is operated in saturation region.

4. rail-to-rail Differential input circuit as claimed in claim 3, is characterized in that, described the 2nd PMOS transistor (PM7) is operated in saturation region, and described the second nmos pass transistor (NM7) is operated in saturation region.

5. rail-to-rail Differential input circuit as claimed in claim 1, is characterized in that,

The source electrode of a described PMOS transistor (PM4) is connected to power supply, and grid is provided the first bias voltage, and drain electrode connects the source electrode of described the 2nd PMOS transistor (PM7); The grid of described the 2nd PMOS transistor (PM7) is provided the second bias voltage, and drain electrode is as the output of described PMOS current source;

The source ground of described the first nmos pass transistor (NM4), grid is provided the 3rd bias voltage, and drain electrode connects the source electrode of described the second nmos pass transistor (NM7); The grid of described the second nmos pass transistor (NM7) is provided the 4th bias voltage, and drain electrode is as the output of described NMOS current source.

6. rail-to-rail Differential input circuit as claimed in claim 2, it is characterized in that, the breadth length ratio of described the 3rd PMOS transistor (PM5) is three times of breadth length ratio of described the 4th PMOS transistor (PM6), and the breadth length ratio of described the 5th PMOS transistor (PM8) is three times of breadth length ratio of described the 6th PMOS transistor (PM9); The breadth length ratio of described the 3rd nmos pass transistor (NM5) is three times of breadth length ratio of described the 4th nmos pass transistor (NM6), and the breadth length ratio of described the 5th nmos pass transistor (NM8) is three times of breadth length ratio of described the 6th nmos pass transistor (NM9).

7. rail-to-rail Differential input circuit as claimed in claim 2, is characterized in that, the grid of described nmos switch transistor (NM3) is provided the 5th bias voltage, and the grid of described PMOS switching transistor (PM3) is provided the 6th bias voltage.

8. an operation amplifier circuit, is characterized in that, comprising:

Rail-to-rail Differential input circuit as described in claim 1～7 any one; And

Output circuit.