CN103973227A - Low-voltage oscillator - Google Patents

Abstract

The invention relates to an electronic circuit technology, and particularly relates to a low-voltage oscillator. The low-voltage oscillator disclosed by the invention comprises a self-adjustment current reference module, a first mirror image circuit, a second mirror image circuit, a control module, a hysteresis inverter and a capacitor C1, wherein the output end of the self-adjustment current reference module is connected to the input end of the first mirror image circuit; the output end of the first mirror image circuit is connected with the positive power end of the second mirror image circuit; the input end of the control module is connected with the negative power end of the first mirror image circuit and the input end of the second mirror image circuit; the output end of the control module is connected with the enable end of the first mirror image circuit, the enable end of the second mirror image circuit and the input end of the hysteresis inverter; the output end of the hysteresis inverter is the output end of the oscillator. The low-voltage oscillator has the beneficial effects that the input voltage is as low as 1.2V, the duty ratio and the frequency of an output oscillator signal are not affected by supply voltage, and the structure is simple.

Description

A Low Voltage Oscillator

technical field

The invention relates to electronic circuit technology, in particular to a low-voltage oscillator.

Background technique

As shown in Figure 1, it is a circuit schematic diagram of an oscillator commonly used in the prior art, wherein MP01, MP02, MN01, MN02 and R01 form a bandgap reference source, and charge capacitor C01 after being mirrored by MP03 tube, when C01 charges When it reaches the high level V _H , the inverter INV01 outputs a high level, and the MP04 tube starts to discharge the capacitor. When C ₀₁ discharges to low level V _L , the inverter outputs low level, MP04 tube is cut off, and C01 continues to charge. Capacitor C01 is continuously charged and discharged to form a sawtooth wave signal, which is shaped by inverters INV01 and INV02 to output a square wave oscillation signal. When the power supply voltage VDD is too low, the oscillator stops working. The minimum input voltage required by the oscillator is not greater than V _GSn -V _GSp +V _DSp (or V _DSn ). In a typical CMOS process, this value is about 1.6 V. In this circuit, the difference V _H -V _L between the breakover voltage V _H in the charging stage and the breakover voltage V _L in the discharging stage of the capacitor C01 will change with the change of the input power supply voltage V _DD . Let the charging current of the capacitor be _Ir , the discharge current is I _f , it can be seen that the frequency of the oscillator is I _r *I _f /[(V _H -V _L )(I _r +I _f )]. Usually, when the input voltage V _DD changes, the relationship between 1/I _r +1/I _f and the change of V _H -V _L is not linear, so the output frequency of the oscillator changes greatly with the change of the input voltage V _DD .

Contents of the invention

What the present invention aims to solve is to propose a low-voltage oscillator for the problem that the output frequency of the above-mentioned traditional oscillator changes greatly with the change of the input voltage.

The technical solution adopted by the present invention to solve the above technical problems is: a low-voltage oscillator, which is characterized in that it includes a self-regulating current reference module, a first mirror circuit, a second mirror circuit, a control module, a hysteresis inverter and a capacitor C1 ; Wherein, the positive power supply terminal of the self-regulating current reference module is connected to the power supply VDD, its negative power supply terminal is grounded to GND, and its output terminal is connected to the input terminal of the first mirror circuit; the positive power supply terminal of the first mirror circuit is connected to the power supply VDD, and its negative power supply terminal is connected to the power supply VDD. The terminal is grounded to GND after passing through capacitor C1, and its output terminal is connected to the positive power supply terminal of the second mirror circuit; the input terminal of the second mirror circuit is grounded to GND through capacitor C1, and its negative power supply terminal is grounded to GND; the input terminal of the control module is connected to the first mirror circuit The negative power supply terminal of the circuit and the input terminal of the second mirror circuit, its output terminal is connected to the enabling terminal of the first mirror circuit, the enabling terminal of the second mirror circuit and the input terminal of the hysteresis inverter; the positive terminal of the hysteresis inverter The power supply terminal is connected to the power supply VDD, its negative power supply terminal is grounded to GND, and its output terminal is the output terminal of the oscillator; wherein the self-regulating current reference module can output different reference currents under different power supply VDD.

Specifically, the self-regulating current reference module is composed of PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, MN3, and resistor R1; wherein, the source of MP1 is connected to the power supply VDD, and its gate is connected to the gate of MP2. Connect the first mirror circuit, its drain is connected to the drain of MN1; the source of MP2 is connected to the power supply VDD, its drain is connected to the drain of MN2; the gate and drain of MN1 are interconnected, and its gate is connected to the gate of MN2 , its source is grounded to GND; the source of MN2 is connected to the drain of MN3; the gate of MN3 is connected to the drain of MP3; the gate of MN3 is grounded to GND after passing through resistor R1; the drain of MP3 is connected to the gate, and its source Pole connected to the power supply VDD;

The hysteresis inverter is composed of PMOS MP4, MP5, MP6, NMOS transistors MN4, MN5, MN6; wherein, the gates of MP4, MP5, MN4, MN5 are connected to the output of the control module; the source of MP4 is connected to the power supply VDD , its drain is connected to the source of MP4 and the source of MP6; the drain of MP5 is connected to the drain of MN5, the gate of MP6 and the gate of MN6 as the output terminal; the drain of MP6 is connected to GND; the source of MN5 Connect the drain of MN4 and the source of MN6; the source of MN4 is grounded to GND; the source of MN6 is grounded to GND.

The beneficial effect of the invention is that the minimum input voltage is as low as 1.2V, the duty cycle and frequency of the output oscillator signal are not affected by the power supply voltage, and the structure is simple.

Description of drawings

Fig. 1 is the schematic diagram of the circuit structure of traditional vibrator;

Fig. 2 is the schematic diagram of the circuit structure of embodiment;

Fig. 3 is a schematic diagram of the circuit structure of the self-regulating current reference module in the embodiment;

Fig. 4 is the schematic diagram of the circuit structure of the hysteresis inverter in the embodiment;

Fig. 5 is the emulation waveform figure when V _DD is 1.2V of embodiment;

FIG. 6 is a simulation waveform diagram of the embodiment when V _DD is 2.5V.

Detailed ways

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

As shown in Figure 2, the low-voltage oscillator of the present invention includes a self-regulating current reference module, a first mirror circuit, a second mirror circuit, a control module, a hysteresis inverter and a capacitor C1; wherein, the positive current reference module of the self-regulating The power supply terminal is connected to the power supply VDD, its negative power supply terminal is grounded to GND, and its output terminal is connected to the input terminal of the first mirror circuit; the positive power supply terminal of the first mirror circuit is connected to the power supply VDD, and its negative power supply terminal is grounded to GND after passing through the capacitor C1, and its output The terminal is connected to the positive power supply terminal of the second mirror circuit; the input terminal of the second mirror circuit is grounded to GND through capacitor C1, and its negative power supply terminal is grounded to GND; the input terminal of the control module is connected to the negative power supply terminal of the first mirror circuit and the second mirror circuit The input end of the input terminal, its output terminal is connected to the enable end of the first mirror circuit, the enable end of the second mirror circuit and the input end of the hysteresis inverter; the positive power supply terminal of the hysteresis inverter is connected to the power supply VDD, and its negative power supply terminal The ground is GND, and its output terminal is the output terminal of the oscillator; wherein the self-regulating current reference module can output different reference currents under different power supply VDD.

Example:

As shown in Figure 3, the self-regulating current reference module in this example is composed of PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, MN3, and resistor R1; wherein, the source of MP1 is connected to the power supply VDD, and its gate is connected to MP2 The gate of MP2 is connected to the first mirror circuit, and its drain is connected to the drain of MN1; the source of MP2 is connected to the power supply VDD, and its drain is connected to the drain of MN2; the gate and drain of MN1 are interconnected, and its gate is connected to The gate of MN2, its source is grounded to GND; the source of MN2 is connected to the drain of MN3; the gate of MN3 is connected to the drain of MP3; the gate of MN3 is grounded to GND after passing through the resistor R1; the drain and gate of MP3 are connected to each other Connected, its source is connected to the power supply VDD;

As shown in Figure 4, the hysteresis inverter is composed of PMOS MP4, MP5, MP6, and NMOS transistors MN4, MN5, and MN6; among them, the gates of MP4, MP5, MN4, and MN5 are connected to the output terminal of the control module; the source of MP4 The pole is connected to the power supply VDD, and its drain is connected to the source of MP4 and the source of MP6; the drain of MP5 is connected to the drain of MN5, the gate of MP6 and the gate of MN6 are connected as output terminals; the drain of MP6 is grounded to GND; The source of MN5 is connected to the drain of MN4 and the source of MN6; the source of MN4 is grounded to GND; the source of MN6 is grounded to GND.

This example works as follows:

The reference current provided by the self-regulating current reference module in this example is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; k</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}$

Among them, k is the ratio of MN2 to MN1, n is the ratio of MP2 to MP1, Rs is the equivalent resistance of MN3 in the linear region, and the relationship between the voltage and current of the MOS tube in the linear region can be obtained:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; Cox\&mu;</span>}\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; )</span>$

Among them, W _MN3 , L _MN3 and V _GS3 respectively represent the gate width, gate length and V _GS value of the NMOS transistor MN3, and C _OX , μ and V _Tn represent the gate oxide layer thickness of the MOS transistor, electron mobility and NMOS transistor The threshold voltage of , for the convenience of expression, use C ₂ to represent C ₁ Coxμ. Since the gate of MN3 is connected to a diode-connected stepped-down V _DD , we get:

I _ref ＝C ₂ (V _GS3 -V _Tn )＝C ₂ (V _DD +V _Tp -V _Tn )

Where V _Tp and V _Tn respectively represent the threshold voltage of the PMOS transistor and the threshold voltage of the NMOS transistor under a specific process.

The first mirror circuit with enable mirrors the reference current value of the self-regulating reference current module with a certain multiple (can be less than 1), and is used to charge the capacitor _C1 . When the first mirror circuit enable input is low, The module stops working, ie stops charging the capacitor _C1 .

The second mirror circuit with enable mirrors the mirror current value of the first mirror circuit with a certain multiple (can be less than 1), and is used to discharge the capacitor _C1 . When the second mirror circuit enable input is high, the The module stops working, that is, stops discharging the capacitor _C1 .

The function of the control module is as follows: the module has a hysteresis function, the input is in the rising stage, when the input is higher than V _DD +V _Tp , the control module outputs a low level; when the input is in the falling stage, when the input is lower than V _Tn , the control The module outputs a high level.

The working process of this example is as follows: when the circuit starts to work, the initial level on the capacitor C1 is 0, the output of the control module is high, the first mirror circuit starts to work, the second mirror circuit stops working, and the capacitor _C1 starts to enter the charging stage; When the capacitor C ₁ is charged to V _DD +V _Tp , the control module outputs a low level, the first mirror circuit stops working, the second mirror circuit starts to work, and the capacitor C ₁ starts to enter the discharge stage; when the capacitor is discharged to V _Tn , the control The device outputs a high level, the first mirror circuit starts to work, the second mirror circuit stops working, and the capacitor _C1 starts to re-enter the charging stage. The circuit continuously repeats the charging and discharging stages, and controls it to continuously output an oscillating signal, and the oscillating signal is optimized and adjusted by the hysteresis inverter to output an ideal oscillating signal. According to the electrical characteristics of the capacitor, the time required for the charging phase t _r and the time required for the discharging phase t _f are as follows:

${\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; u</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tp</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tp</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}}{{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}$

${\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; u</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tp</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tp</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}}{{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}$

Among them, n _r and n _f represent the ratios of the first mirror current to the variable reference current and the second mirror current to the variable reference current (both are less than 1), and C represents the capacitance value of the capacitor _C1 . Since C, C ₂ , n _r and n _f are constants independent of the power supply voltage V _DD , it can be seen that when the input power supply voltage V _DD changes, the output frequency and duty cycle of the oscillator remain unchanged.

The simulation waveforms of the oscillator when the input voltage V _DD is 1.2V and 2.5V are shown in Figure 5 and Figure 6, where C1 is the waveform of the positive terminal of the capacitor, Control is the output waveform of the control module, OSC_OUT is the output waveform of the oscillator circuit, Simulation results show that when the power supply voltage V _DD changes, the oscillator output frequency and duty cycle remain unchanged.

Claims (2)

1. a low voltage oscillator, is characterized in that, comprises self-regulation current reference module, the first mirror image circuit, the second mirror image circuit, control module, sluggish inverter and capacitor C 1; Wherein, the positive supply termination power vd D of self-regulation current reference module, its negative power end ground connection GND, its output termination first mirror is as the input of circuit; The positive supply termination power vd D of the first mirror image circuit, its negative power end is by the rear ground connection GND of capacitor C 1, and it exports the positive power source terminal of termination the second mirror image circuit; The input of the second mirror image circuit is by capacitor C 1 ground connection GND, its negative power end ground connection GND; The input termination first mirror of control module is as the negative power end of circuit and the input of the second mirror image circuit, and its output termination first mirror is as Enable Pin, the Enable Pin of the second mirror image circuit and the input of sluggish inverter of circuit; The positive supply termination power vd D of sluggish inverter, its negative power end ground connection GND, the output that its output is oscillator; Wherein self-regulation current reference module can be exported different reference currents under different power vd D.

2. a kind of low voltage oscillator according to claim 1, is characterized in that, described self-regulation current reference module by PMOS manage MP1, MP2, MP3, NMOS pipe MN1, MN2, MN3, resistance R 1 forms; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the first mirror image circuit after connecing the grid of MP2, and its drain electrode connects the drain electrode of MN1; The source electrode of MP2 meets power vd D, and its drain electrode connects the drain electrode of MN2; The grid of MN1 and drain electrode interconnection, its grid connects the grid of MN2, its source ground GND; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the drain electrode of MP3; The grid of MN3 is by the rear ground connection GND of resistance R 1; The drain electrode of MP3 and gate interconnection, its source electrode meets power vd D;

Described sluggish inverter is made up of PMOS MP4, MP5, MP6, NMOS pipe MN4, MN5, MN6; Wherein, the gate interconnection of MP4, MP5, MN4, MN5 connects the output of control module; The source electrode of MP4 meets power vd D, and its drain electrode connects the source electrode of MP4 and the source electrode of MP6; The drain electrode of MP5 is connected as output with the grid of the drain electrode of MN5, MP6 and the grid of MN6; The grounded drain GND of MP6; The source electrode of MN5 connects the drain electrode of MN4 and the source electrode of MN6; The source ground GND of MN4; The source ground GND of MN6.