CN103970709A - Communication method for FFT coprocessor and main processor - Google Patents

Abstract

The invention provides a communication method between an FFT coprocessor and a main processor, the method comprising the steps of: connecting both the CPU and the DMA controller to the AHB bus; the DMA controller integrating the bridge from the AHB bus to the APB bus; and the FFT coprocessor The slave controller integrating the APB bus; the FFT coprocessor sends an interrupt request; the CPU responds to the interrupt request; the DMA controller moves the FFT operation result to the system memory; the communication ends. Through the method provided by the invention, the problem of data exchange between the slow FFT coprocessor and the main processor is solved; according to the characteristics of the data that the FFT coprocessor needs to transmit, DMA is used to exchange data between the FFT coprocessor and the main processor , Improved CPU and bus utilization.

Description

A communication method between FFT coprocessor and main processor

technical field

The invention relates to a communication method in the field of integrated circuits, in particular to a communication method between an FFT coprocessor and a main processor.

Background technique

Fourier transform is the most commonly used analysis method for frequency domain analysis of signals to obtain signal frequency domain characteristics. The proposal of discrete Fourier transform provides a theoretical basis for frequency domain analysis of digital signals. However, the direct discrete Fourier transform has a very high amount of calculation, and it was not widely used before the fast Fourier transform (FFT) was proposed. The introduction of FFT greatly reduces the computational load of Fourier transform, making it possible for Fourier transform to be applied to real-time systems. At this time, Fourier analysis of signals began to be widely used.

FFT can be realized by general-purpose DSP, FPGA and special-purpose ASIC. Dedicated ordinary processors can also realize the FFT function through software configuration, but because ordinary processors do not have bus structures and arithmetic units optimized for complex operations like DSP, when using ordinary processors for FFT operations, a large number of FFT Multiplication and addition operations will greatly occupy CPU resources, resulting in high work and low efficiency. Therefore, general-purpose CPUs are generally not used for FFT operations. With the development of integrated circuits, it has become a development trend to integrate multiple functional modules on a single chip. This chip is called SOC (System On Chip). For specific applications, FFT can also be designed as a separate dedicated module and CPU integrated into a chip as a coprocessor of the CPU to assist the CPU to practice the function of FFT. The CPU is only responsible for simple control, and the analysis results of FFT can be obtained. In this way, the CPU can be freed from a large number of calculations to do the control work that it is good at, so as to achieve the purpose of improving efficiency and reducing power consumption.

The FFT coprocessor generally contains an embedded RAM (Random-Access Memory) for temporarily storing the intermediate and final calculation results of the FFT. Since the FFT coprocessor processes the data sent by the ADC in real time, the final calculation result cannot be stored for a long time and must be moved to the system memory before the next calculation result is input.

Contents of the invention

In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a method for FFT coprocessor to communicate with CPU through DMA, so as to realize efficient data communication between FFT coprocessor and CPU.

In order to realize the above-mentioned purpose of the invention, the present invention takes the following technical solutions:

A kind of FFT coprocessor and main processor communication method, it is characterized in that, described method comprises the steps:

A. Connect both the CPU and the DMA controller to the AHB bus;

B. The DMA controller integrates the bridge from the AHB bus to the APB bus;

C. FFT coprocessor integrates the slave controller of APB bus;

D. The FFT coprocessor sends an interrupt request;

E. CPU responds to the interrupt request;

F. The DMA controller moves the FFT operation result to the system memory;

G. Communication ends.

Preferably, step A includes: controlling the control right of the AHB bus through a selector; setting a master controller and a slave controller of the AHB bus on the DMA controller, and the master controller and the slave controller receive data from the AHB bus, And send data to the AHB bus after obtaining the bus control right.

Preferably, in step B, the bridge from the AHB bus to the APB bus completes the protocol conversion function from AHB data to APB data.

Preferably, in step C, the slave controller of the APB bus exchanges data with the outside; the APB controller on the DMA is connected to the FFT coprocessor to realize a data path based on the APB protocol.

Preferably, in step D, the FFT coprocessor sending an interrupt request includes: when the FFT coprocessor completes data operations, the FFT coprocessor sends an interrupt request to the CPU, requesting the CPU to move the data obtained by this FFT operation.

Preferably, in step E, the CPU responding to the interrupt request includes: the CPU calls the interrupt handler according to the interrupt vector; the interrupt handler configures the start address, end address and transfer mode of the data to be moved to the DMA controller through the AHB bus in the register.

Preferably, step F includes: the CPU releases the control right of the AHB bus after completing the configuration, and the DMA controller obtains the control right of the AHB bus, and moves the operation result of the FFT stored in the address corresponding to the FFT to the system memory according to the configuration of the CPU.

Preferably, step G includes: after the DMA controller completes the data transfer work, it sends an interrupt; the CPU receives the interrupt and knows that the work is completed, and the communication process ends.

Compared with prior art, the beneficial effect of the present invention is:

The FFT coprocessor of the present invention is a dedicated module for FFT analysis of power grid signals, and can directly analyze the digital signal obtained by converting an external analog signal by an analog-to-digital converter (ADC); Memory Access) controller is sent to the system memory;

This patent solves the problem of data exchange between the slow FFT coprocessor and the main processor;

According to the characteristics of the data to be transmitted by the FFT coprocessor, this patent uses DMA to exchange data between the FFT coprocessor and the main processor. By using the DMA controller, the CPU can simply configure the DMA to move the data generated by FFT directly to the memory, which reduces the data moving load of the CPU and improves the utilization of the CPU and the bus.

Description of drawings

Fig. 1 is a structural diagram of a communication system in an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings.

Method provided by the invention comprises the steps:

1. Both the CPU and the DMA controller are connected to the high-speed AHB bus, and a higher-level selector is used to control who has control over the bus. The DMA controller has a master controller and a slave controller of the AHB bus, which can receive data from the AHB bus or obtain bus control and send data to the AHB bus.

2. The DMA directly integrates the bridge from the AHB bus to the APB bus to complete the protocol conversion function from AHB data to APB data.

3. The FFT coprocessor integrates the slave controller of APB to realize data exchange with the outside world. The APB controller on the DMA is directly connected to the FFT coprocessor to realize a dedicated data path based on the APB protocol, and realize the direct communication between the FFT coprocessor and the DMA.

4. Send an interrupt request to the main processor when the FFT data operation is completed, requesting the main processor to move the data obtained by this FFT operation.

5. The main processor responds to the interrupt request of the FFT module, and calls the interrupt handler according to the corresponding interrupt vector. The interrupt handler configures the start address, end address, and transfer mode of the data to be moved to the relevant registers in the DMA controller through the AHB bus.

6. After the CPU completes the configuration, it is released to do other work. The DMA controller obtains the control right of the AHB bus, and moves the FFT operation result stored in the FFT corresponding address to the system memory according to the CPU configuration.

7. After the DMA completes the data moving work, it sends an interrupt, and the CPU receives the interrupt to know that the work is completed. Embodiment one is as follows:

The frequency of the power grid is very low (50Hz or 60Hz), and the harmonic analysis of the power grid generally requires about 50 to 100 harmonics. To obtain higher frequency domain resolution and higher precision, the storage space required by the FFT output signal is about 10-20k. For example, when the power grid frequency is 50Hz, it is required to be able to analyze the 100th harmonic, and the signal bandwidth is at least 5000. For the convenience of implementation, 256 sampling points per cycle are taken, and the Nyquist sampling rate is 12.8k. Generally, the method of interpolation filtering FFT is used to achieve higher analysis accuracy at a lower number of FFT analysis points. This application does 4096-point FFT analysis, the output signal is a complex number, and the bit width is 24 bits, so the total storage space required is 4k*2*24/8=24kB. Therefore, each FFT analysis will generate 24kB of data.

Referring to Fig. 1, when the FFT coprocessor completes an FFT operation, all the data is temporarily stored on an output RAM of the FFT coprocessor. At this time, the FFT coprocessor raises an interrupt request to the CPU. The CPU receives the interrupt request, finds the corresponding interrupt vector, jumps to the corresponding interrupt address, and executes the corresponding interrupt handler. The program controls the processor to write the configuration data into the registers in the DMA through the AHB bus. The configuration data includes the original address and length of the data to be moved, the starting address of the target address of the data to be moved, and the way of moving.

After the processor configures the registers in the DMA, it releases the control of the AHB bus to complete other tasks. At this time, the DMA controller obtains the control right of the AHB bus according to the configuration of the CPU. At the same time, the DMA controller reads the data in the FFT coprocessor according to the provisions of the APB protocol through the dedicated APB bus connected with the FFT coprocessor. The read data is written into the system memory through the AHB bus after the protocol conversion of the DMA controller. After the data transfer is completed, the DMA raises an interrupt to the processor.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the scope of the claims of the present invention.

Claims (8)

1. a kind of FFT coprocessor and main processor communication method, it is characterized in that, described method comprises the steps: A. Connect both the CPU and the DMA controller to the AHB bus; B. The DMA controller integrates the bridge from the AHB bus to the APB bus; C. FFT coprocessor integrates the slave controller of APB bus; D. The FFT coprocessor sends an interrupt request; E. CPU responds to the interrupt request; F. The DMA controller moves the FFT operation result to the system memory; G. Communication ends. 2. The method according to claim 1, wherein step A comprises: controlling the control right of the AHB bus by a selector; setting the master controller and the slave controller of the AHB bus on the DMA controller, the master control The controller and the slave controller receive data from the AHB bus, and send data to the AHB bus after obtaining bus control. 3. The method according to claim 1, characterized in that: in step B, the bridge from the AHB bus to the APB bus completes the protocol conversion function from AHB data to APB data. 4. the method for claim 1 is characterized in that: in step C, the slave controller of described APB bus exchanges data with the outside world; The APB controller on the DMA connects FFT coprocessor, realizes the data based on APB agreement path. 5. The method according to claim 1, wherein, in step D, the FFT coprocessor sending an interrupt request comprises: when the FFT coprocessor has data operations to complete, the FFT coprocessor sends an interrupt request to the CPU , requesting the CPU to move the data obtained by this FFT operation. 6. The method according to claim 1, wherein in step E, the CPU responding to the interrupt request comprises: the CPU calls the interrupt handler according to the interrupt vector; The address and transfer mode are configured into registers in the DMA controller through the AHB bus. 7. The method according to claim 1, wherein step F comprises: releasing the control right of the AHB bus after the CPU completes the configuration, and the DMA controller obtains the control right of the AHB bus, and transfers the FFT corresponding address to The operation result of the stored FFT is moved to the system memory. 8. The method according to claim 1, wherein step G comprises: after the DMA controller completes the data transfer work, sending an interrupt; the CPU receives the interrupt and knows that the work is completed, and the communication process ends.