CN103970485B

CN103970485B - A kind of Nonvolatile memory expanding unit, memory array and computer installation

Info

Publication number: CN103970485B
Application number: CN201410173292.9A
Authority: CN
Inventors: 江韬; H.F.黄; 李惊雷
Original assignee: WUXI YUNDONG TECHNOLOGY DEVELOPMENT Co Ltd
Current assignee: WUXI YUNDONG TECHNOLOGY DEVELOPMENT Co Ltd
Priority date: 2014-04-28
Filing date: 2014-04-28
Publication date: 2016-10-12
Anticipated expiration: 2034-04-28
Also published as: CN103970485A

Abstract

The invention belongs to calculator memory technical field, it is provided that a kind of Nonvolatile memory expanding unit, memory array and computer installation；Wherein this Nonvolatile memory expanding unit includes main control module and some volatile storage of main control module parallel join and some Nonvolatile memory devices, electric source monitoring circuit, serial line interface, charge-discharge modules, the SMB module that is arranged between volatile storage and serial line interface, parallel data stream between volatile storage and Nonvolatile memory devices or CPU, according to the serial communication protocol of CPU Memory Controller Hub, is converted into serial data stream by described SMB module.Pass through the present invention, the Nonvolatile memory density being effectively improved in computer, avoid and too much DIMM socket is set on mainboard, and the memory bar that unit capacity is less can be used to have non-volatile memory array with composition Large Copacity, reduce the manufacturing cost of computer, improve the service efficiency to existing low capacity memory bar.

Description

Nonvolatile memory expansion device, memory array and computer device

Technical Field

The invention belongs to the technical field of computer memories, and particularly relates to a serialization-based nonvolatile memory expansion device and a memory array suitable for a server or a high-performance computer device, and a computer device based on the technical scheme.

Background

The server or high-performance computer includes: CPU, main memory, peripheral I/O, disk array (RAID) and heat dissipation system. With the development of semiconductor process technology, the memory controller (memory controller) is currently integrated into the CPU.

See the fully buffered dual in-line memory module (FB-DIMM) shown in FIG. 1. An Advanced Memory Buffer chip (AMB) is added on a PCB of a traditional Memory bank, and the AMB, the DRAM particles and a Memory controller are connected by a serial interface.

Meanwhile, FB-DIMM adopting DRAM particles adopts pins (namely metal contacts) with large quantity to be mutually spliced with Dual Inline Memory Modules (DIMMs) through 168-pins (DDR-2) or 240-pins (DDR-3) and DDR-4 (288-pins) to be pushed out, and is spliced with a Mainboard (MB).

Meanwhile, a Hybrid-type nonvolatile memory (H-DIMM) includes: NV-DIMM, NV-RAMDISK, SATA-DIMM, etc., which typically include several DRAM pellets and NAND FLASH pellets, and a Super Capacitor (Super Capacitor) to provide emergency power.

The H-DIMM is capable of backing up data in the DRAM to NAND FLASH upon an abnormal power down of the system Power Supply (PSU) and restoring data in NAND FLASH to the DRAM upon a computer power-up. Therefore, the H-DIMM has the characteristics of high speed and random access of the DRAM and also has the characteristic of non-volatility of FLASH. Therefore, it is widely used as a permanent Data storage device In applications such as Big Data (Big Data), High Performance Computing (HPC), In-Memory database (IMDB), File system (File-system), and Storage Area Network (SAN).

However, simply increasing the number of DIMM sockets on a motherboard to match with the H-DIMM socket plugging increases the difficulty of motherboard manufacture (wiring, layout, wire length, board layer) and significantly increases the cost of the motherboard. Taking TB level main memory scale as an example, with the currently mainstream 4GB H-DIMM, 256 DIMM sockets need to be installed on the motherboard.

Obviously, this solution is not feasible on the premise that the volume of the main board is very valuable. At the same time, it is not economical to use high unit capacity H-DIMMs to form the same memory size. This will inevitably result in a dramatic increase in the cost of manufacturing the motherboard and the entire computer. Because the increase in H-DIMM capacity is an "exponential" relationship to manufacturing costs, simply increasing the unit capacity of an H-DIMM also results in an increase in computer manufacturing costs.

Finally, since NAND FLASH in the MLC/SLC type of the prior art is much more integrated than DRAM, the bandwidth is much less than DRAM. Therefore, the large-capacity NAND FLASH DRAM pellets required by matching with the relatively small-capacity DRAM pellets are often wasted in the nonvolatile storage space; the use of small volumes of NAND FLASH pellets tends to be costly; especially, in order to compensate for the non-uniform bandwidth of the two memory devices, a plurality of NAND FLASH granules with small capacity are needed, which further increases the manufacturing cost of the whole H-DIMM.

In view of the above, there is a need to improve the above technical defects in the prior art to solve the above defects.

Disclosure of Invention

The invention aims to provide a nonvolatile memory expansion device which is used for improving the capacity density of a nonvolatile memory in a computer, avoiding the arrangement of excessive DIMM slots on a mainboard, reducing the manufacturing cost of a computer with a large capacity or an ultra-large memory specification and realizing the downward compatibility with memory banks with various specifications. Based on the above invention, the invention also provides a non-volatile memory array and a computer device based on the memory array.

To achieve the above object, the present invention provides a nonvolatile memory expansion apparatus, including:

the device comprises a main control module, a plurality of volatile storage devices and a plurality of nonvolatile storage devices which are connected with the main control module in parallel, a power supply monitoring circuit, a serial interface and a charge-discharge module connected with a voltage conversion circuit; the main control module can control data backup and recovery between the volatile storage device and the nonvolatile storage device according to at least the power-off and recovery signals of the system voltage monitored by the power supply monitoring circuit; and

and the SMB module is arranged between the volatile storage device and the serial interface and converts the parallel data stream between the volatile storage device and the nonvolatile storage device or the CPU into a serial data stream according to the serial communication protocol of the CPU memory controller.

As a further improvement of the present invention, the main control module comprises: a data transfer engine, a working state machine, a volatile storage device controller and a non-volatile storage device controller; wherein,

the working state machine issues a queue command to the data transmission engine;

the data transmission engine is used for receiving a queue command issued by the working state machine, splitting the queue command into a sub-command set in a matrix form, splitting data to be transmitted into sub-data sets with the same matrix scale, binding the sub-command in the sub-command set and the sub-data in the sub-data sets according to matrix coordinates, and then transmitting data between the volatile storage controller and the nonvolatile storage controller;

a volatile storage device controller which performs read-write control on the volatile storage device;

a nonvolatile memory device controller that performs read/write control on the nonvolatile memory device; wherein

The matrix form includes a one-dimensional matrix form, a two-dimensional matrix form, or a three-dimensional matrix form.

As a further improvement of the present invention, the SMB module is disposed within the main control module and between the volatile storage controller and the serial interface to convert a parallel data stream between the volatile storage and the CPU into a serial data stream.

As a further refinement of the present invention, the volatile memory device controller is a serial DRAM controller.

As a further improvement of the present invention, the SMB module is not provided in the main control module, but is provided between the volatile storage device and the serial interface and connected to the serial DRAM controller to convert a parallel data stream between the volatile storage device and the nonvolatile storage device or between the volatile storage device and the CPU into a serial data stream.

As a further improvement of the invention, the voltage conversion circuit is composed of a low dropout linear regulator and/or a DC-DC converter.

Meanwhile, to achieve the second object of the present invention, the present invention further provides a memory array, including:

the nonvolatile memory expansion devices comprise a plurality of sub storage units; each sub-storage unit comprises a plurality of groups of volatile storage devices and nonvolatile storage devices with equal capacity; and the number of the first and second groups,

a plurality of redundant storage modules which are respectively connected with all the nonvolatile storage devices in the sub storage units in parallel through Flash synchronous buses; wherein,

the memory array is provided with an even number of SMI sockets between the CPU and the heat dissipation device through the mainboard so as to realize the electrical connection with the mainboard.

As a further development of the invention, the redundant memory module is a non-volatile memory device or a battery-powered volatile memory device.

Finally, to achieve the final object of the present invention, the present invention further provides a computer device, comprising a motherboard, a plurality of CPUs, a power supply, a disk array module, a heat dissipation device, and a peripheral I/O;

the computer device further comprises the memory array.

As a further improvement of the present invention, the computer device further includes a charge-discharge module embedded in the disk array bracket and electrically connected to the power supply and the voltage conversion circuit through the PCB in the disk array bracket.

Compared with the prior art, the invention has the beneficial effects that: in the invention, the nonvolatile memory expansion device is inserted into the SMI socket on the mainboard through the SMI serial interface, thereby effectively improving the nonvolatile memory density in the computer, avoiding the arrangement of excessive DIMM sockets on the mainboard, forming a large-capacity nonvolatile memory array by using a memory with smaller unit capacity in the existing memory specification, reducing the manufacturing cost of the computer and improving the use efficiency of a small-capacity memory bank. The technical effect of the invention is especially obvious in the field of Storage Class Memory (SCM).

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. Wherein,

FIG. 1 is a schematic diagram of a prior art FB-DIMM architecture;

FIG. 2 is a schematic diagram of a memory array;

FIG. 3 is a block diagram of a first embodiment of a nonvolatile memory expansion apparatus according to the present invention;

FIG. 4 is a schematic diagram of the main control module of FIG. 3;

FIG. 5 is a block diagram of a nonvolatile memory expansion apparatus according to a second embodiment of the present invention;

FIG. 6 is a schematic diagram of the main control module of FIG. 5;

FIG. 7 is a block diagram of a nonvolatile memory expansion apparatus according to a third embodiment of the present invention;

FIG. 8 is a schematic diagram of the main control module of FIG. 7;

FIG. 9 is a diagram of a nonvolatile memory expansion device in the memory array shown in FIG. 2 with redundant memory modules;

FIG. 10 is a schematic diagram of a computer device;

FIG. 11 is a schematic diagram of another computer device.

Wherein, the reference numbers of each embodiment in the specification are described as follows:

computer means-10; a main board-100; a server-200; CPU-101, 102, 103, 104; local memory-110; peripheral I/O-120; heat sinks-130 a, 130b, 130 c; disk array module (RAID) -140; a charge and discharge module-150; a power supply-160; serial data stream-310; memory controller-1011; a memory array-300; nonvolatile memory expansion devices-301, 302, 303, 304, 305, 306, 307, 308; a voltage conversion circuit-3010; DIMM socket-3011; a memory bank-3012; NANDFLASH socket-3013; a main control module-3014; a power supply monitoring circuit 3015; serial interface-3016; NAND FLASH-3017; working state machine-3114; DRAM controller-3214; SMB modules-3018, 3314; a data transmission engine-3414; NAND controller-3514; a redundant memory module-331; sub-memory cells-311, 312, 313, 314; AMB-400; FB-DIMM-500; DRAM grain-111; flash synchronization bus 3118; MUX (multiplexer) -3019.

Detailed Description

The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.

An In-Memory database (IMDB) is a database management system that relies on main Memory as a data storage medium. IMDB is faster, can be accessed directly by the CPU, and has a qualitative leap in I/O path and latency. In addition, atomic operations, memory barriers, and cache flush instructions provided by the CPU itself may provide simple and efficient atomicity and coherency services for the IMDB.

File-system, method and data structure in an Operating System (OS) for specifying files on a disk or partition.

Example one：

Referring to fig. 2 to 4, an embodiment of a nonvolatile memory expansion apparatus according to the present invention is shown.

Referring to fig. 3, in the present embodiment, a nonvolatile memory expansion device 301, 302, 303, 304, 305, 306, 307, 308 is provided (in each embodiment of the present disclosure, the nonvolatile memory expansion device 301 is taken as an example for a technical solution, and an example is given).

The nonvolatile memory expansion apparatus 301 includes:

the main control module 3014, a plurality of volatile memory devices (composed of a plurality of memory banks 3012 and a plurality of DIMM sockets 3011) and a plurality of nonvolatile memory devices (composed of a plurality of NAND FLASH3017 and a plurality of NAND FLASH sockets 3013) connected in parallel with the main control module, a power monitoring circuit 3015, a serial interface 3016, and a charging and discharging module 150 connected with the voltage conversion circuit 3010.

The memory stick 3012 is plugged into the DIMM socket 3011, and the NAND FLASH3017 may be electrically connected to the NAND FLASH socket 3013 by soldering or may be electrically connected to a high-speed interface (not shown) of various specifications. The memory bank 3012 can adopt standard memory bank specifications such as U-DIMM, R-DIMM, SO-DIMM and the like, and can be downward compatible with DDR-3, DDR-2 and upward compatible with DDR-4.

Therefore, in this embodiment, a large number of memory banks 3012 with a small unit capacity can be combined into a large-capacity memory system by using a Stack Structure (Stack Structure), thereby avoiding direct connection to a motherboard using a DIMM socket.

The main control module 3014 can control data backup and recovery between the volatile memory device and the nonvolatile memory device according to at least the power-off and recovery signals of the system voltage monitored by the power monitoring circuit 3015.

In the present embodiment, the nonvolatile memory expansion devices 301 to 308 further include an SMB module (scalable memory Buffer) 3314 provided between the volatile memory device and the serial interface 3016, and converts the parallel data stream between the volatile memory device and the nonvolatile memory device or between the CPUs 101, 102, 103, and 104 into the serial data stream 310 according to the serial communication protocol of the memory controller 1011 provided in the CPUs 101, 102, 103, and 104.

As shown in fig. 2, when the nonvolatile memory expansion devices 301 to 308 are plugged into a motherboard to work normally or when a computer is abnormally powered off, a serial data stream 310 conforming to the FB-DIMM standard is formed between the CPU101 and the designated nonvolatile memory expansion devices 301 and 302 in fig. 2, and between the CPU104 and the designated nonvolatile memory expansion devices 307 and 308.

Specifically, the SMB module 3314 is disposed within the main control module 3014 and between the volatile memory device controller and the serial interface 3016 to convert the parallel data stream between the volatile memory device and the CPU101 or 102 or 103 or 104 into the serial data stream 310.

In this embodiment, the serial port 3016 is preferably a SMI plug (Scalable Memory Interface) that is adapted to communicate with the SMB module 3314 to drive the serial data stream 310 to be transmitted between the CPUs 101-104 and the nonvolatile Memory expansion devices 301-308.

Further, the main control module 3014 includes: a data transfer engine 3414, an operating state machine 3114, a volatile storage controller 3214, and a non-volatile storage controller 3514. The volatile memory device controller 3214 is preferably a DRAM controller, so as to transmit control signals RAS \ CAS \ WE \ CS \ CKE \ ODT through the DRAM controller and a plurality of volatile memory devices connected in parallel; a power source; data DQ [63:0], DQS [0:17 ]; address signals A [15:0], BA [2:0 ].

As shown in fig. 3, when the power monitoring circuit 3015 monitors the power signal VSS and the voltage of VCC exceeds the normal voltage range by 80%, it sends a system power down signal to the main control module 3014.

Referring to fig. 4, the operating state machine 3114 in the main control module 3014 receives a system Power-down signal or Power _ OK signal (both are digital signals) sent by the Power monitoring circuit 3015. When a system power-down signal is received, data in the memory strip 3012 is backed up to NAND FLASH 3017; when Power _ OK is received, data in the memory bank 3012 is controlled to be directly accessed by the CPU101 via the serial interface 3016 by the DRAM controller 3214 and the SMB module 3314.

Specifically, the operating state machine 3114 is preferably an FPGA chip, but may be another semiconductor chip having a logic operation function, for example, an ASIC chip. The charging and discharging module 150 is formed by connecting 5 Super capacitors (Super capacitors) with rated output voltage of 2.7V and unit Capacity of 100F in series to form an energy storage device with output voltage of 12V-13.5V and Capacity of 20F.

Meanwhile, in the present embodiment, the voltage conversion circuit 3010 is a Low drop out regulator (LDO) or a DC-DC converter, and is used to perform voltage conversion, voltage stabilization, filtering, and other processing on the direct current supplied by the charging and discharging unit 150.

When the computer is powered off abnormally, the power monitoring circuit 3015 monitors the power signal VSS in the serial port 3016 (see fig. 8 or fig. 9), and the voltage of VCC exceeds the lower limit of the normal voltage range, and then the power monitoring circuit 3015 sends a system power-down signal to the main control module 3014; then, the main control module 3014 sends an enable signal to the voltage conversion circuit 3010, so as to connect the charge and discharge module 150 to the nonvolatile memory device, and to electrically connect the charge and discharge module 150 to the main control module 3014, and the charge and discharge module 150 to the nonvolatile memory device, thereby ensuring that the charge and discharge module 150 provides power supply to the volatile memory device, the main control module 3014, and the nonvolatile memory device within a certain time. Meanwhile, the main control module 3014 may concurrently save data dynamically running in the volatile memory devices to the non-volatile memory devices in parallel.

When the computer is normally powered on, the data exchanged between the memory bank 3012 and the main control module 3014 is a parallel data stream. As shown in fig. 4, after receiving the parallel data stream, the DRAM controller 3214 in the main control module 3014 converts the parallel data stream into a serial data stream 310 through the SMB module 3314, and finally transmits the serial data stream to the CPU101 through the serial interface 3016.

In this embodiment, the operating state machine 3114 issues a queue command to the data transfer engine 3414; the data transmission engine 3414 is configured to receive a queue command issued by the operating state machine 3114, split the queue command into sub-command sets in a matrix form, split data to be transmitted into sub-command sets in the same matrix scale, bind the sub-command in the sub-command set and the sub-data in the sub-command sets according to matrix coordinates, and transmit data between the volatile storage controller 3214 and the nonvolatile storage controller 3514; a volatile memory device controller 3214 that performs read/write control on the volatile memory device;

the nonvolatile memory device controller 3514 controls reading and writing of the nonvolatile memory device.

Specifically, the matrix form includes a one-dimensional matrix form, a two-dimensional matrix form, or a three-dimensional matrix form, and is preferably a two-dimensional matrix.

Example two：

Referring to fig. 2, fig. 5 and fig. 6, a second embodiment of a nonvolatile memory expansion apparatus according to the present invention is shown.

The main difference between this embodiment and the first embodiment is that the SMB module 3018 is not provided in the main control module 3014, but an SMB integrated chip is used. The SMB module 3018 is disposed between the volatile memory device and the serial interface 3016 and connected to the serial DRAM controller 3402 to convert parallel data streams between the volatile memory device and the nonvolatile memory device or between the volatile memory device and the CPU101 into a serial data stream 310. More specifically, the volatile memory device controller is a serial DRAM controller 3402.

Specifically, the voltage conversion circuit 3010 is formed by a low dropout regulator (LDO) and a DC-DC converter. Since low dropout linear regulator (LDO) and DC-DC converter are well established prior art, they will not be described in detail herein.

Compared to the second embodiment, in this embodiment, the complicated parallel DRAM controller 3402 is replaced with a serial DRAM controller 3402 that only needs to analyze data streams, so that the number of logic units and pins of the main control module 3014 (e.g., FPGA) can be greatly reduced. The reduction in the number of pins of the main control module 3014 means that multiple serial DRAM controllers 3402 can be integrated, thereby enabling connection of a greater number of DRAMs, and thus increasing the memory deployment density in the single non-volatile memory expansion devices 301-308 shown in the present invention.

In addition, the main control module 3014 only needs to analyze data, and is independent of the specifications of the memories plugged in the nonvolatile memory expansion devices 301, 302, 303, 304, 305, 306, 307, and 308 and the SMB chip, so that the compatibility of the main control module 3014 is further improved.

EXAMPLE III：

Referring to fig. 2, fig. 7 and fig. 8, a third embodiment of a nonvolatile memory expansion apparatus according to the present invention is shown. Referring to fig. 7 and 8, the main difference between this embodiment and the first and second embodiments is that in this embodiment, a MUX3019 is disposed between the DIMM socket 3011 and the SMB module 3018 in the nonvolatile memory expansion devices 301 to 308, and the MUX3019 is controlled by the main control module 3014.

The MUX is a high-speed electronic switch with a multi-path selection function, and is essentially a multi-input and single-output combinational logic circuit, which is commonly used to schedule data according to an address code in the implementation of an arithmetic circuit. It can only alternatively restore data between the memory banks 3012 and NAND FLASH3017 or establish a data path between the memory bank 3012 and the CPU.

The MUX3019 may be selected from an 8-way 1-bit specification, where the selected specification is selected according to a quantity ratio between NAND FLASH3017 and memory banks 3012 of the nonvolatile memory expansion devices 301-308. Of course, the MUX3019 may also adopt the specification of 16-way 1-bit, 2-way 4-bit, 4-way 2-bit, 4-way 1-bit.

In this embodiment, please refer to the detailed description of the first embodiment and/or the corresponding parts of the second embodiment in this specification for the introduction of the data transmission engine 3414, the operating state machine 3114, the DRAM controller 3214, and the NAND controller 3514, which will not be described herein again.

Referring to fig. 2, when the computer is normally powered on, the MUX3019 selects a DIMM socket 3011 to establish a data transmission channel with the SMB module 3018 under the control of the main control module 3014, converts the parallel data stream into a serial data stream 310 through the SMB module 3018, sends the serial data stream to the serial interface 3016, and finally performs data communication with a designated CPU through the serial interface 3016. In this state, the MUX3019 has only one data path, i.e., memory bank 3012 to DIMM socket 3011 to MUX3019 to SMB module 3018 to serial interface 3016 to CPU 101.

Referring to fig. 8, when the computer is abnormally powered down, the main control module 3014 controls the MUX3019 to cut off the data path from the memory bank 3012 to the DIMM socket 3011 to the MUX3019 to the SMB module 3018 to the serial interface 3016 to the CPU101, and then establishes a data backup path between the memory bank 3012 to the DIMM socket 3011 to the MUX3019 to the DRAM controller 3214 to the data transmission engine 3414 to the NAND controller 3514 to the NAND sockets 3013 to NAND FLASH 3017.

After the computer is powered on, the main control module 3014 rewrites the data backed up to NAND FLASH3017 into the memory bank 3012 according to the reverse direction of the data backup path, so that the memory bank 3012 recovers the memory data running in the DRAM when the computer is abnormally powered off;

then, the main control module 3014 controls the MUX3019 to cut off the data backup path, and then re-establishes the data path between the memory bank 3012 to the DIMM socket 3011 to the MUX3019 to the SMB module 3018 to the serial interface 3016 to the CPU101 during normal power supply of the computer.

Example four：

Referring to fig. 2 and 9, an embodiment of a memory array according to the present invention is shown.

In fig. 9, in the present embodiment, a memory array 300 electrically connected to a motherboard (refer to the motherboard 100 in fig. 10) includes: in the nonvolatile memory expansion apparatus 301 according to some of the above embodiments, the nonvolatile memory expansion apparatus 301 includes a plurality of sub memory units 311, 312, 313, and 314. For simplicity of illustration, the sub-memory cells 312 and 313 are omitted from FIG. 9.

Each sub-storage unit 311 includes a plurality of groups of volatile storage devices 3012 and nonvolatile storage devices 3017 with equal capacity, and a plurality of redundant storage modules 331 connected in parallel to all the nonvolatile storage devices 3017 in the sub-storage units 311, 312, 313, and 314 through a Flash synchronization bus 3118.

Referring to fig. 2, in the present embodiment, the redundant memory module 331 may reserve an independent storage area for redirecting bad blocks for each of the nonvolatile memory expansion devices 301 to 308. In this embodiment, the redundant memory module 331 is preferably a non-volatile memory device, such as NAND FLASH; of course, a volatile memory device (not shown) powered by a battery may also be used.

Further, the capacity of the redundant memory module 331 is greater than or equal to the capacity of the single nonvolatile memory device 3017 in each sub-memory unit, and more preferably, the capacity of the redundant memory module 331 is: the ratio of the capacities of the individual nonvolatile memory devices 3017 in each sub memory cell is 1.5: 1-1: 1, and further preferably 1.2: 1.

Referring to fig. 10 and 11, in the present embodiment, the memory array 300 is electrically connected to the motherboard 10 by an even number of SMI sockets (not shown) disposed between the CPUs 101, 102, 103, and 104 and the heat dissipation devices 130a, 130b, and 130c through the motherboard 10. Among them, the number of SMI sockets is preferably 4 or 8, and further preferably 8.

Specifically, as shown in fig. 9, in the present embodiment, the storage capacity that requires addition of nonvolatile storage in the plurality of nonvolatile storage devices 3017 can be concentrated on the redundant memory module 331. The cost of a single large capacity NAND FLASH is lower than the cost of a non-volatile storage device of the same capacity size consisting of multiple small capacities NAND FLASH.

Therefore, by providing such a redundant memory module 331 and connecting it to all the nonvolatile memory devices 3017 in the sub-memory unit 311 through the Flash synchronization bus 3118, the entire memory array 300 can be reduced to the maximum extent, and in particular, the manufacturing cost of the memory array 300 with power-down data protection can be reduced, thereby reducing the manufacturing cost of a computer device using the memory array 300.

EXAMPLE five：

Referring to fig. 10, an embodiment of a computer device according to the present invention is shown.

In this embodiment, a computer device 10 includes a motherboard 100, CPUs 101, 102, 103, and 104, a power supply 160, a disk array module 140, heat sinks 130a, 130b, and 130c, and a peripheral I/O120. The computer device 10 further includes a memory array 300 as described in the third implementation.

The computer device 10 further includes a charge-discharge module 150 embedded in the disk array bracket and electrically connected to the power supply 160 and the voltage conversion circuit 3010 through the PCB in the disk array bracket.

Specifically, the charge and discharge module 150 at least includes a sub-charge and discharge module (not shown) with a rated working voltage of 12-13.5V and a capacity of 20F. The sub-charge-discharge module consists of five Super capacitors (Super capacitors) with rated working voltage of 2.7V and unit capacity of 100F.

The disk array bracket in the prior art is of a specified size, the length is 132mm, the width is 101mm, and the height is 25 mm; the single rated operating voltage is 2.7V, and the diameter of the super capacitor with the unit capacity of 100F is 23mm, and the length of the super capacitor is 52 mm. Therefore, two groups of sub-charge-discharge modules connected in parallel can be arranged in a cell of a disk array bracket, and a switch (not shown) is used for switching between the two groups of sub-charge-discharge modules, so as to prevent a certain sub-charge-discharge module from being incapable of providing enough direct current for the nonvolatile memory expansion devices 301-308 when the computer is abnormally powered off, and further improve the overall safety and reliability of the computer.

In this embodiment, four local memories 110 are further disposed on the main board 100 of the computer device 10, and together with the memory array 300, form a memory system of the computer device 10. Local memory 110 is directly connected to CPUs 101, 102, 103, 104. The local memory 110 has the characteristics of fast access speed and short delay, and can be used for storing temporary calculation results and information.

Specifically, the memory array 300 can be used to store permanent data, such as data of a memory database and a file system, and has functions of both a memory and a hard disk.

EXAMPLE six：

Referring to fig. 11, another embodiment of a computer device 10 according to the present invention is shown.

The main differences between this embodiment and the fourth embodiment are: in this embodiment, the motherboard 100 is not provided with a local memory socket (i.e., a DIMM socket into which the local memory 110 shown in fig. 8 is plugged) for directly communicating with the CPUs 101, 102, 103, and 104; rather, the function of local memory 110 in FIG. 8 is implemented by providing an expandable memory array 300 between disk array module 140 and heat sinks 130a, 130b, 130 c.

As shown in fig. 11, in the present embodiment, a charging/discharging module 150 may be further disposed in the power supply 160 of the computer device 10 to provide a backup power supply for the computer in case of abnormal power failure, and store the work site in the main memory (i.e., the nonvolatile memory expansion devices 301 to 308) during operation. The entire computer device 10 may use all of the nonvolatile memory expansion devices 301 to 308 shown in the first to third embodiments of this specification as main memory.

Specifically, the charging and discharging module 150 in the power supply 160 can provide a working site preservation time of 15 seconds to 30 seconds for the whole computer device 10; meanwhile, the charging and discharging module 150 arranged in the disk array module 140 is combined; therefore, the function of supporting WSP (white-System Persistence) is realized, and the runtime overhead (RuntimeOverheads) of data processing is reduced.

The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A non-volatile memory expansion device, comprising:

the device comprises a main control module, a plurality of volatile storage devices and a plurality of nonvolatile storage devices which are connected with the main control module in parallel, a power supply monitoring circuit, a serial interface and a charge-discharge module connected with a voltage conversion circuit; the main control module can control data backup and recovery between the volatile storage device and the nonvolatile storage device according to at least the power-off and recovery signals of the system voltage monitored by the power supply monitoring circuit;

the system is characterized by also comprising an SMB module which is arranged between the volatile storage device and the serial interface and converts parallel data stream between the volatile storage device and the nonvolatile storage device or between the CPUs into serial data stream according to the serial communication protocol of the CPU memory controller;

the main control module comprises: a data transfer engine, a working state machine, a volatile storage device controller and a non-volatile storage device controller; wherein,

a nonvolatile memory device controller that performs read/write control on the nonvolatile memory device; wherein,

2. The nonvolatile memory expansion device of claim 1, wherein the SMB module is disposed within the main control module and between the volatile storage controller and the serial interface to convert a parallel data stream between the volatile storage and the CPU into a serial data stream.

3. The non-volatile memory expansion device of claim 1, wherein the volatile storage device controller is a serial DRAM controller.

4. The nonvolatile memory expansion device of claim 3, wherein the SMB module is not provided in the main control module, but is provided between the volatile storage device and the serial interface, and is connected to the serial DRAM controller to convert a parallel data stream between the volatile storage device and the nonvolatile storage device or between the volatile storage device and the CPU into a serial data stream.

5. The non-volatile memory expansion device of claim 1, wherein the voltage conversion circuit is comprised of a low dropout linear regulator and/or a DC-DC converter.

6. A memory array, comprising:

the plurality of nonvolatile memory expansion devices of any one of claims 1 to 5, the nonvolatile memory expansion devices comprising a plurality of sub-storage units; each sub-storage unit comprises a plurality of groups of volatile storage devices and nonvolatile storage devices with equal capacity; and the number of the first and second groups,

7. The memory array of claim 6, wherein the redundant memory module is a non-volatile memory device or a battery-powered volatile memory device.

8. A computer device comprises a mainboard, a plurality of CPUs (central processing units), a power supply, a disk array module, a heat dissipation device and peripheral I/O (input/output);

the computer device further comprising a memory array according to any one of claims 6 to 7.

9. The computer device of claim 8, further comprising a charge-discharge module embedded in the disk array tray and electrically connected to the power supply and the voltage conversion circuit via a PCB in the disk array tray.